1
2000 Integrated Device Technology, Inc.
MAY 2000
DSC 3198/6
I/O
Control
Address
Decoder
64Kx8
MEMORY
ARRAY
7008
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/
W
L
A
15L
A
0L
I/O
0-7L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
R/
W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/
W
R
CE
0R
A
15R
A
0R
I/O
0-7R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/
S
(1)
CE
1L
R/
W
R
CE
0R
OE
R
CE
1R
3198 drw 01
1L
CE
1R
CE
16
16
Functional Block Diagram
x
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
x
M/
S = V
IH
for
BUSY output flag on Master,
M/
S = V
IL
for
BUSY input on Slave
x
Interrupt Flag
x
On-chip port arbitration logic
x
Full on-chip hardware support of semaphore signaling
between ports
x
Fully asynchronous operation from either port
x
TTL-compatible, single 5V (10%) power supply
x
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
x
Industrial temperature range (40C to +85C) is available
for selected speeds
Features
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
High-speed access
Military: 25/35/55ns (max.)
Industrial: 55ns (max.)
Commercial: 20/25/35/55ns (max.)
x
Low-power operation
IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
x
Dual chip enables allow for depth expansion without
external logic
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT7008S/L
NOTES:
1.
BUSY is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/
S = V
IH
).
2.
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
2
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Description
The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (
CE
0
and CE
1
) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA),
a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad
Flatpack (TQFP).
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
Pin Configurations
(1,2,3)
NC
GND
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
Vcc
O
E
L
R
I
W
L
S
E
M
L
C
E
1
L
C
E
0
L
N
C
A
1
5
L
A
1
4
L
A
1
3
L
A
8
L
A
7
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
G
N
D
V
c
c
N
C
N
C
N
C
A
1
4
R
N
C
G
N
D
N
C
G
N
D
N
C
S
E
M
R
C
E
1
R
C
E
0
R
O
E
R
R
/
W
R
N
C
A
1
5
R
A
1
2
R
A
1
3
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/
S
BUSY
L
INT
L
NC
A
0L
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
GND
14
15
16
17
18
19
20
INDEX
21
22
23
24
11 10 9
8 7
6 5
4 3
2 1 84 83
33 34 35 36 37 38 39 40 41 42 43 44 45
13
12
25
26
27
28
29
30
31
32
46 47 48 49 50 51 52 53
72
71
70
69
68
67
66
65
64
63
62
73
74
61
60
59
58
57
56
55
54
82 81 80 79 78 77 76 75
IDT7008J
J84-1
(4)
84-Pin PLCC
Top View
(5)
3198 drw 02
G
N
D
G
N
D
,
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
3
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
Pin Configurations
(1,2,3)
(con't.)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT7008PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
GND
OE
R
R/
W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
NC
3198 drw 03
NC
NC
GND
OE
L
R/
W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
Vcc
NC
A
15L
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
N
C
N
C
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
V
c
c
I
/
O
2
R
I
/
O
0
R
G
N
D
V
c
c
I
/
O
0
L
I
/
O
1
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
G
N
D
N
C
N
C
N
C
N
C
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
I
N
T
R
B
U
S
Y
R
M
/
S
B
U
S
Y
L
I
N
T
L
N
C
A
0
L
G
N
D
A
2
L
A
3
L
A
5
L
A
6
L
N
C
N
C
A
1
L
A
4
L
,
4
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Pin Configurations
(1,2,3)
(con't)
3198 drw 04
63
61
60
58
55
54
51
48
46
45
66
67
69
72
75
76
79
81
82
83
1
2
5
7
8
11
10
12
14
17
20
23
26
28
29
32
31
33
35
38
41
43
IDT7008G
G84-3
(4)
84-Pin PGA
Top View
(5)
A
B
C
D
E
F
G
H
J
K
L
42
59
56
49
50
40
25
27
30
36
34
37
39
84
3
4
6
9
15
13
16
18
22
24
19
21
68
71
70
77
80
11
10
09
08
07
06
05
04
03
02
01
64
65
62
57
53
52
47
44
73
74
78
INDEX
NC
GND
GND
OE
L
R/
W
L
SEM
L
CE
1L
CE
0L
NC
A
15L
A
14L
A
13L
A
8L
A
7L
A
12L
A
11L
A
10L
A
9L
GND
Vcc
NC
NC
NC
A
14R
GND
NC
GND
NC
CE
1R
CE
0R
OE
R
R/
W
R
SEM
R
NC
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/
S
BUSY
L
INT
L
NC
A
0L
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
Vcc
GND
NC
GND
,
Left Port
Right Port
Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
15L
A
0R
- A
15R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power
GND
Ground
3198 tbl 01
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
5
Truth Table I: Chip Enable
(1)
Truth Table II: Non-Contention Read/Write Control
NOTES:
1. A
0L
A
15L
A
0R
A
15R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from all the I/Os (I/O
0
-I/O
7
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE is a reference only.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
CC
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
3198 tbl 02
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to memory
L
H
L
H
DATA
OUT
Read memory
X
X
H
X
High-Z
Outputs Disabled
3198 tbl 03
Inputs
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-7
H
H
L
L
DATA
OUT
Read Semaphore Flag Data Out
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
______
Not Allowed
3198 tbl 04
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