Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

DSC-2740/6

IDT7024S/L

HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM

more than one device

· M/

= H for

BUSY

output flag on Master

= L for

BUSY

input on Slave

· Busy and Interrupt Flags
· On-chip port arbitration logic
· Full on-chip hardware support of semaphore signaling

between ports

· Devices are capable of withstanding greater than 2001V
electrostatic discharge.
· Fully asynchronous operation from either port
· Battery backup operation--2V data retention
· TTL-compatible, single 5V (

10%) power supply

· Available in 84-pin PGA, 84-pin quad flatpack, 84-pin

PLCC, and 100-pin Thin Quad Plastic Flatpack

· Industrial temperature range (40

C to +85

C) is avail-

able, tested to military electrical specifications

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

· True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

· High-speed access

-- Military: 20/25/35/55/70ns (max.)
-- Commercial: 15/17/20/25/35/55ns (max.)

· Low-power operation

-- IDT7024S

Active: 750mW (typ.)
Standby: 5mW (typ.)

-- IDT7024L

Active: 750mW (typ.)
Standby: 1mW (typ.)

· Separate upper-byte and lower-byte control for

multiplexed bus compatibility

· IDT7024 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading

NOTES:
1. (MASTER):

BUSY

is output;

(SLAVE):

BUSY

is input.

BUSY

outputs

and

INT

outputs

are non-tri-stated
push-pull.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.15

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

BUSY

11L

2740 drw 01

I/O

-I/O

15L

I/O

-I/O

SEM

INT

BUSY

I/O

-I/O

15R

I/O

-I/O

11R

SEM

INT

(2)

(1,2)

(2)

1 2

6.15

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

(1,2)

2740 drw 02

INDEX

11 10 9

1 84 83

33 34 35 36 37 38 39 40 41 42 43 44 45

GND

I/O

46 47 48 49 50 51 52 53

82 81 80 79 78 77 76 75

GND

BUSY

GND

IDT7024

J84-1
F84-2

84-PIN PLCC /

FLATPACK

TOP VIEW

(3)

INT

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

I/O

BUSY

I/O

SEM

N/C

11L

GND

I/O

10L

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

GND

N/C

11R

10R

SEM

Index

75
74

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT7024
PN100-1

100-PIN

TQFP

TOP VIEW

(3)

N/C
N/C
N/C
N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

GND

I/O

N/C
N/C
N/C
N/C

2740 drw 03

N/C
N/C
N/C
N/C
A

INT

GND
M/

BUSY

INT

N/C
N/C
N/C
N/C

BUSY

I/O

GND

I/O

SEM

N/C

11L

10L

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

SEM

GND

N/C

11R

10R

NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.

DESCRIPTION:

The IDT7024 is a high-speed 4K x 16 Dual-Port Static

RAM. The IDT7024 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
Dual-Port RAM for 32-bit or more word systems. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or
wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.

This device provides two independent ports with separate

control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by chip
enable (

) permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT's CMOS high-performance technol

ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500

W from a 2V

battery.

The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-

pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited
to military temperature applications demanding the highest
level of performance and reliability.

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.15

Left Port

Right Port

Names

Chip Enable

Read/Write Enable

Output Enable

11L

11R

Address

I/O

15L

I/O

15R

Data Input/Output

SEM

Semaphore Enable

Upper Byte Select

Lower Byte Select

INT

Interrupt Flag

BUSY

Busy Flag

Master or Slave Select

Power

GND

Ground

PIN NAMES

2740 tbl 1

2740 drw 04

I/O

IDT7024

G84-3

84-PIN PGA

TOP VIEW

(3)

GND

SEM

N/C

GND

SEM

INT

BUSY

INT

11L

N/C

Index

I/O

10L

I/O

11L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

10L

10R

11R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

PIN CONFIGURATIONS (CONT'D)

(1,2)

NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade

Temperature

GND

Military

C to +125

5.0V

10%

Commercial

C to +70

5.0V

10%

2740 tbl 02

6.15

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

TERM

(2)

Terminal Voltage 0.5 to +7.0

0.5 to +7.0

with Respect
to GND

Operating

0 to +70

55 to +125

Temperature

BIAS

Temperature

55 to +125

65 to +135

Under Bias

STG

Storage

55 to +125

65 to +150

Temperature

OUT

DC Output

Current

NOTES:

2740 tbl 05

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM

must not exceed Vcc +0.5V for more than 25% of the cycle time or

10ns maximum, and is limited to < 20ma for the period over V

TERM >

Vcc

+ 0.5V

TRUTH TABLE I NON-CONTENTION READ/WRITE CONTROL

Inputs

(1)

Outputs

SEM

I/O

8-15

I/O

0-7

Mode

High-Z

Deselected: Power-Down

High-Z

Both Bytes Deselected

DATA

High-Z

Write to Upper Byte Only

High-Z

DATA

Write to Lower Byte Only

DATA

Write to Both Bytes

DATA

OUT

High-Z

Read Upper Byte Only

High-Z

DATA

OUT

Read Lower Byte Only

DATA

OUT

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

NOTE:

2740 tbl 03

1. A

-- A

11L

are not equal to A

-- A

11R.

RECOMMENDED DC OPERATING
CONDITIONS

Symbol

Parameter

Min.

Typ.

Max. Unit

Supply Voltage

4.5

5.0

5.5

GND

Supply Voltage

Input High Voltage

2.2

6.0

(2)

Input Low Voltage

0.5

(1)

0.8

NOTES:

2740 tbl 06

1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 0.5V.

Symbol

Parameter

Condition

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

Output Capacitance

OUT

= 3dV

NOTES:

2740 tbl 07

1. This parameter are determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

CAPACITANCE

(1)

TRUTH TABLE II SEMAPHORE READ/WRITE CONTROL

(1)

Inputs

Outputs

SEM

I/O

8-15

I/O

0-7

Mode

DATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

DATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

DATA

Write I/O

into Semaphore Flag

DATA

Write I/O

into Semaphore Flag

Not Allowed

2740 tbl 04

NOTE:
1. There are eight semaphore flags written to via I/O

and read from all of the I/O's (I/O

- I/O

). These eight semaphores are addressed by A

- A

= +25

C, F = 1.0MHZ) TQFP ONLY

IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.15

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

= 5.0V

10%)

7024X15

7024X17

7024X20

7024X25

Test

Com'l. Only

Symbol

Parameter

Condition

Version Typ.

(2)

Max.

Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

Dynamic Operating

"A"

, Outputs Open

MIL

160

370

155

340 mA

Current

SEM

= V

160

320

155

280

(Both Ports Active)

f = f

MAX

(3)

COM S

170

310

170

310

160

290

155

265

170

260

170

260

160

240

155

220

SB1

Standby Current

= V

MIL

(Both Ports -- TTL

SEM

= V

Level Inputs) f = f

MAX

(3)

COM S

SB2

Standby Current

"A"

and

"B"

(5)

MIL

240

215 mA

(One Port -- TTL Active Port Outputs Open

210

180

Level Inputs) f = f

MAX

(3)

COM S

105

190

105

190

180

170

SEM

= V

105

160

105

160

150

140

SB3

Full Standby Current Both Ports

and

MIL

1.0

(Both Ports -- All

- 0.2V

0.2

CMOS Level Inputs) V

> V

- 0.2V or

COM S

1.0

< 0.2V, f = 0

(4)

0.2

SEM

> V

- 0.2V

SB4

Full Standby Current

"A"

< 0.2 and

MIL

225

200 mA

(One Port -- All

"B"

> V

- 0.2V

(5)

200

170

CMOS Level Inputs)

SEM

> V

- 0.2V

> V

- 0.2V or

COM S

100

170

100

170

155

145

< 0.2V, Active Port

100

140

100

140

130

120

Outputs Open,

f = f

MAX

(3)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

= 5.0V

10%)

IDT7024S

IDT7024L

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

Output Leakage Current

= V

, V

OUT

= 0V to V

Output Low Voltage

= 4mA

0.4

Output High Voltage

= -4mA

2.4

2740 tbl 08

NOTES:

2740 tbl 09

1. "X" in part numbers indicates power rating (S or L).
2. V

= 5V, T

= +25

C, and are not production tested. I

CC DC

= 120mA (typ.)

3. At f = f

MAX

address and I/O'

are cycling at the maximum frequency read cycle of 1/ t

, and using "AC Test Conditions" of input levels of GND to 3V.

4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTE:
1. At Vcc < 2.0V input leakages are undefined.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT7024S17PF

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT7024S17PF