APRIL 2004

DSC-5675/4

I/O

Control

Address
Decoder

12L

(1)

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

5675 drw 01

SEM

INT

SEM

INT

(3)

12R

(1)

Address

Decoder

I/O

Control

BUSY

I/O

-I/O

15L

I/O

-I/O

BUSY

I/O

-I/O

15R

I/O

-I/O

(2,3)

INPUT

READ REGISTER

AND

OUTPUT

DRIVE REGISTER

IRR

,IRR

OD R

ODR

SFEN

IDT70P258/248L

VERY LOW POWER 1.8V
8K/4K x 16 DUAL-PORT
STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous
reads of the same memory location

High-speed access
 Industrial: 55ns (max.)

Low-power operation

IDT70P258/248L
Active: 27mW (typ.)
Standby: 3.6

W (typ.)

Separate upper-byte and lower-byte control for multiplexed
bus compatibility

IDT70P258/248 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device

S = V

for

BUSY output flag on Master

S = V

for

BUSY input on Slave

Input Read Register

Output Drive Register

BUSY and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling
between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 1.8V (±100mV) power supply

Available in 100 Ball 0.5mm-pitch BGA

Industrial temperature range (-40°C to +85°C)

Functional Block Diagram

NOTES:
1. A

12X

is a NC for IDT70P248.

2. (MASTER):

BUSY is output; (SLAVE): BUSY is input.

BUSY outputs and INT outputs are non-tri-stated push-pull.

Supports 3.0V, 2.5V and 1.8V I/O's

6.42

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Description

The IDT70P258/248 is a very low power 8K/4K x 16 Dual-Port

Static RAM. The IDT70P258/248 is designed to be used as a stand-alone
128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE Dual-
Port SRAM for 32-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port SRAM approach in 32-bit or wider memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by

CE permits the on-chip circuitry of each port to enter

a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology,

these devices typically operate on only 27mW of power.

The IDT70P258/248 is packaged in a 100 ball 0.5mm- pitch Ball

Grid Array. The package is a 1mm thick and designed to fit in wireless
handset applications.

Pin Configurations

(2,3,4)

C10

D10

A10

B10

E10

F10

G10

H10

J10

K10

5675 drw 02b

09/04/03

11R

Vss

SEM

I/O

15R

I/O

12R

I/O

10R

Vss

I/O

11R

I/O

14R

Vss

SFEN

Vss

I/O

12R

(1)

10R

INT

I/O

13R

I/O

BUSY

I/O

ODR

I/O

ODR

INT

IRR

I/O

ODR

BUSY

I/O

15L

DDQL

ODR

12L

(1)

I/O

11L

I/O

12L

I/O

14L

I/O

13L

I/O

DDQL

I/O

10L

IRR

I/O

11L

SEM

I/O

Vss

70P258/248BY

BY-100

100-Ball 0.5mm Pitch BGA

Top View

(5)

NOTES:
1. A

12X

is a NC for IDT70P248.

2. All V

pins must be connected to power supply.

3. All V

pins must be connected to ground supply.

4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

6.42

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Pin Names

Left Port

Right Port

Names

Chip Enable (Input)

Read/Write Enable (Input)

Output Enable (Input)

- A

12L

(1)

- A

12R

(1)

Address (Input)

I/O

- I/O

15L

I/O

- I/O

15R

Data Input/Output

SEM

Semaphore Enable (Input)

Upper Byte Select (Input)

Lower Byte Select (Input)

INT

Interrupt Flag (Output)

BUSY

Busy Flag

IRR

, IRR

Input Read Register (Input)

ODR

- ODR

Output Drive Register (Output)

SFEN

(2)

Special Function Enable (Input)

Master or Slave Select (Input)

Power (1.8V) (Input)

DDQL

Left Port I/O Supply Voltage
(3.0V) (Input)

Ground (0V) (Input)

5675 tbl 01

NOTE:
1. A

12X

is a NC for IDT70P248.

SFEN is active when either CE

= V

SFEN is inactive when CE

= V

NOTE:

1. A

-- A

12L

-- A

12R

Truth Table I: Non-Contention Read/Write Control

Inputs

(1)

Outputs

Mode

SEM

I/O

8-15

I/O

0-7

High-Z

Deselected: Power Down

High-Z

Both Bytes Deselected

DATA

High-Z

Write to Upper Byte Only

High-Z

DATA

Write to Lower Byte Only

DATA

Write to Both Bytes

DATA

OUT

High-Z

Read Upper Byte Only

High-Z

DATA

OUT

Read Lower Byte Only

DATA

OUT

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

5675 tbl 02

6.42

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Truth Table II: Semaphore Read/Write Control

(1)

NOTE:

1. There are eight semaphore flags written to via I/O

and read from all of the I/O's (I/O

-I/O

). These eight semaphores are addressed by A

-A

Inputs

Outputs

Mode

SEM

I/O

8-15

I/O

0-7

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

Write D

IN0

into Semaphore Flag

DATA

Write D

IN0

into Semaphore Flag

____

Not Allowed

____

Not Allowed

5675 tbl 03

Absolute Maximum Ratings

(1)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period over V

TERM

= V

+ 0.3V

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. V

DDQLMAX

+ 0.3V for left port.

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage with

Respect to GND

-0.5 to V

DDMAX

+0.3V

(4)

BIAS

(3)

Temperature Under Bias

-55 to +125

STG

Storage Temperature

-65 to +150

Junction Temperature

+150

OUT

(for

DDQL

3.0V)

DC Output Current

OUT

(for

DDQL

1.8V)

DC Output Current

5675 tbl 04

6.42

IDT70P258/248L
Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range

Capacitance

(TA = +25°C, f = 1.0MHz)

NOTES:
1.

This parameter is determined by device characterization but is not production
tested.

3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

Output Capacitance

OUT

= 3dV

5675 tbl 07

Maximum Operating Temperature
and Supply Voltage

(1)

NOTES:
1. This is the parameter T

. This is the "instant on" case temperature.

Grade

Ambient

Temperature

GND

Industrial

-40

C to +85

1.8V

100mV

5675 tbl 05

Recommended DC Operating Conditions

DDQL

= 3.0V±300mV)

NOTES:
1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed V

+ 0.3V.

SFEN operates at the 1.8V V

and V

voltage levels.

4. M/

S operates at the V

and V

voltage levels.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

(4)

1.7

1.8

1.9

DDQL

Left Port Supply Voltage

2.7

3.0

3.3

Ground

IHL

Input High Voltage (V

DDQL

= 3.0V)

2.0

___

DDQL

+ 0.2

ILL

Input Low Voltage (V

DDQL

= 3.0V)

-0.2

___

0.6

IHR

Input High Voltage

(3)

1.2

___

+ 0.2

ILR

Input Low Voltage

(3)

-0.2

___

0.4

5675 tbl 06

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

(4)

1.7

1.8

1.9

DDQL

Left Port Supply Voltage

2.4

2.5

2.6

Ground

IHL

Input High Voltage (V

DDQL

= 2.5V)

1.7

___

DDQL

+ 0.3

ILL

Input Low Voltage (V

DDQL

= 2.5V)

-0.3

___

0.7

IHR

Input High Voltage

(3)

1.2

___

+ 0.2

ILR

Input Low Voltage

(3)

-0.2

___

0.4

5675 tbl 06_5

Recommended DC Operating Conditions

DDQL

= 2.5V±100mV)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT70P258