APRIL 2004

DSC 5666/6

Functional Block Diagram

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port

Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-
pin PQFP package

HIGH-SPEED 2.5V
256/128/64K x 36

SYNCHRONOUS

DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70T3519/99/89S

REPEAT

CNTEN

ADS

Dout0-8_R

Dout9-17_R

I/O

- I/O

35R

Din_R

ADDR_R

1/0

/PIPE

1a 0a

1b 0b

1c 0c

1d 0d

CLK

Counter/

Address

Reg.

d c b a

0/1

0d 1d

0c 1c

0b 1b

0a 1a

B
W
2
R

B
W
1
R

B
W
0
R

/PIPE

Counter/

Address

Reg.

CNTEN

ADS

REPEAT

Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L

D out18-26_R
D out27-35_R

B
W
0
L

B
W
1
L

B
W
2
L

B
W
3
L

I/O

- I/O

35L

17L(1)

Din_L

ADDR_L

5666 drw 01

256/128/64K x 36

MEMORY

ARRAY

CLK

a bc d

/PIPE

0/1

1d 0d

1c 0c 1b 0b 1a 0a

B
W
3
R

JTAG

TCK

TRST

TMS

TDO

TDI

1/0

0d 1d

0c 1c

0b 1b

0a 1a

/PIPE

1/0

INTERRUPT

COLLISION

DETECTION

LOGIC

R /

0 L

CE1L

0 R

CE1R

INT

COL

INT

COL

CONTROL

LOGIC

(2)

17R(1)

Features:

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed data access
 Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

 Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without
additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports
5ns cycle time, 200MHz operation (14Gbps bandwidth)
Fast 3.4ns clock to data out
1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

1. Address A

is a NC for the IDT70T3599. Also, Addresses A

and A

are NC's for the IDT70T3589.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOTES:

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(3,4,5,6,9)

NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be V

REFL

and V

REFR

respectively for future HSTL device.

70T3519/99/89BC

BC-256

(7)

256-Pin BGA

Top View

(8)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

PIPE/

TDO

I/O

20L

I/O

19R

I/O

19L

TDI

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L

I/O

22R

I/O

23R

DDQL

I/O

24R

I/O

24L

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L

I/O

28R

I/O

27R

DDQL

I/O

29R

I/O

29L

I/O

28L

DDQL

I/O

30L

I/O

31R

I/O

30R

DDQR

I/O

32R

I/O

32L

I/O

31L

DDQR

I/O

33L

I/O

34R

I/O

33R

PIPE/

I/O

35R

I/O

34L

TMS

I/O

35L

TRST

TCK

13R

15R

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

I/O

P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R11

REPEAT

11R

11L

B10

C13

10R

R10

T10

INT

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

COL

INT

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

COL

F11

5666 drw 02d

06/19/02

17R

(1)

17L

(1)

16L

(2)

16R

(2)

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

70T3519/99/89DR

DR-208

(7)

208-Pin PQFP

Top View

(8)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

I
/
O

I
N

(
1

)

(
2

)

I
/
O

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

I
/
O

I
N

(
1

)

(
2

)

I
/
O

5666 drw 02a

06/19/02

Pin Configuration

(3,4,5,6,9,10)

(con't.)

NOTES:

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Due to limited pin count, JTAG is not supported in the DR-208 package.
10. Pins 162 and 99 will be V

REFL

and V

REFR

respectively for future HSTL device.

1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

NOTES:

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be V

REFL

and V

REFR

respectively for future HSTL device.

Pin Configuration

(3,4,5,6,9)

(con't.)

1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.

A17

B17

I/O

15R

C17

D17

I/O

14R

E16

E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

B15

DDQR

C15

I/O

16R

D15

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

13L

14L

11L

COL

INT

15L

TDO

TDI

PL/

I/O

20L

I/O

18R

DDQR

I/O

21L

I/O

19R

I/O

18L

I/O

19L

I/O

20R

DDQL

I/O

22L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

28R

I/O

27R

I/O

29R

I/O

28L

DDQR

I/O

27L

DDQL

I/O

29L

I/O

30R

I/O

31L

I/O

31R

I/O

30L

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

33L

I/O

34R

TCK

I/O

33R

I/O

34L

DDQL

TMS

I/O

35L

PL/

COL

TRST

11R

P12

U10

P10

T11

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

13R

INT

U14

T14

R14

P14

I/O

P15

I/O

R15

DDQL

T15

I/O

U15

OPT

U16

I/O

U17

I/O

T16

T17

I/O

R17

DDQR

R16

I/O

P17

I/O

P16

N17

I/O

N16

I/O

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

I/O

M14

L17

I/O

L16

L15

I/O

L14

I/O

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

10R

H16

H15

I/O

H14

G17

I/O

11R

G16

I/O

10L

G15

DDQL

G14

I/O

F17

DDQR

F16

I/O

11L

F14

70T3519/99/89BF

BF-208

(7)

208-Pin fpBGA

Top View

(8)

F15

I/O

12R

R11

ADS

14R

B10

C13

R10

T10

10R

15R

5666 drw 02c

17R

(1)

17L

(1)

16L

(2)

16R

(2)

01/23/03

CNTEN

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

Chip Enables (Input)

(7)

R/W

Read/Write Enable (Input)

Output Enable (Input)

- A

17L

(6)

- A

17R

(6)

Address (Input)

I/O

- I/O

35L

I/O

- I/O

35R

Data Input/Output

CLK

Clock (Input)

PL/FT

Pipeline/Flow-Through (Input)

ADS

Address Strobe Enable (Input)

CNTEN

Counter Enable (Input)

REPEAT

Counter Repeat

(3)

- BE

Byte Enables (9-bit bytes) (Input)

(7)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

(Input)

OPT

Option for selecting V

DDQX

(1,2)

(Input)

Sleep Mode pin

(4)

(Input)

Power (2.5V)

(1)

(Input)

Ground (0V) (Input)

TDI

(5)

Test Data Input

TDO

(5)

Test Data Output

TCK

(5)

Test Logic Clock (10MHz) (Input)

TMS

(5)

Test Mode Select (Input)

TRST

(5)

Reset (Initialize TAP Controller) (Input)

INT

Interrupt Flag (Output)

COL

Collision Alert (Output)

5666 tbl 01

NOTES:
1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to V

(2.5V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to V

(0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.

3. When REPEAT

is asserted, the counter will reset to the last valid address loaded

via ADS

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.

5. Due to limited pin count, JTAG is not supported in the DR-208 package.
6. Address A

17x

is a NC for the IDT70T3599. Also, Addresses A

17x

and A

16x

are

NC's for the IDT 70T3589.

7. Chip Enables and Byte Enables are double buffered when PL/FT = V

, i.e., the

signals take two cycles to deselect.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

2. ADS, CNTEN, REPEAT = V

3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I--Read/Write and Enable Control

(1,2,3,4)

CLK

R/W

Byte 3

I/O

27-35

Byte 2

I/O

18-26

Byte 1
I/O

9-17

Byte 0

I/O

0-8

MODE

High-Z

DeselectedPower Down

High-Z

DeselectedPower Down

High-Z

All Bytes Deselected

High-Z

Write to Byte 0 Only

High-Z

Write to Byte 1 Only

High-Z

Write to Byte 2 Only

High-Z

Write to Byte 3 Only

High-Z

Write to Lower 2 Bytes Only

High-Z

Write to Upper 2 bytes Only

Write to All Bytes

High-Z

OUT

Read Byte 0 Only

High-Z

OUT

High-Z

Read Byte 1 Only

High-Z

OUT

High-Z

Read Byte 2 Only

OUT

High-Z

Read Byte 3 Only

High-Z

OUT

Read Lower 2 Bytes Only

OUT

High-Z

Read Upper 2 Bytes Only

OUT

Read All Bytes

High-Z

Outputs Disabled

High-Z

Sleep Mode

5666 tbl 02

Truth Table II--Address Counter Control

(1,2)

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE

, CE

, BEn and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE

, CE

and BEn

5. The address counter advances if CNTEN = V

on the rising edge of CLK, regardless of all other memory control signals including CE

, CE

, BEn.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

Address

Previous

Internal

Address

Internal

Address

Used

CLK

ADS

CNTEN

REPEAT

(6)

I/O

(3)

MODE

(4)

I/O

(n)

External Address Used

An + 1

(5)

I/O

(n+1)

Counter Enabled--Internal Address generation

An + 1

I/O

(n+1)

External Address Blocked--Counter disab led (An + 1 reused)

(4)

I/O

(n)

Counter Set to last valid ADS load

5666 tbl 03

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

(1)

NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.

Grade

Ambient

Temperature

GND

Commercial

C to +70

2.5V

100mV

Industrial

-40

C to +85

2.5V

100mV

5666 tbl 04

Recommended DC Operating

Conditions with V

DDQ

at 3.3V

NOTES:
1. V

(min.) = -1.0V for pulse width less than t

CYC

/2, or 5ns, whichever is less.

2. V

(max.) = V

DDQ

+ 1.0V for pulse width less than t

CYC

/2 or 5ns, whichever is less.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin

for that port must be set to V

(2.5V), and V

DDQX

for that port must be supplied as indicated

above.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

2.4

2.5

2.6

DDQ

I/O Supply Voltage

(3)

3.15

3.3

3.45

Ground

Input High Voltage
(Address, Control
&Data I/O Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Input High Voltage

JTAG

1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, PIPE/FT

- 0.2V

____

+ 100mV

(2)

Input Low Voltage

-0.3

(1)

____

0.8

Input Low Voltage -

ZZ, OPT, PIPE/FT

-0.3

(1)

____

0.2

5666 tbl 05b

Recommended DC Operating

Conditions with V

DDQ

at 2.5V

NOTES:
1. V

(min.) = -1.0V for pulse width less than t

CYC

/2 or 5ns, whichever is less.

2. V

(max.) = V

DDQ

+ 1.0V for pulse width less than t

CYC

/2 or 5ns, whichever is less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT

pin for that port must be set to V

(0V), and V

DDQX

for that port must be supplied as indicated

above.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

2.4

2.5

2.6

DDQ

I/O Supply Voltage

(3)

2.4

2.5

2.6

Ground

Input High Volltage
(Address, Control &
Data I/O Inputs)

(3)

1.7

____

DDQ

+ 100mV

(2)

Input High Voltage

JTAG

1.7

____

+ 100mV

(2)

Input High Voltage -

ZZ, OPT, PIPE/FT

- 0.2V

____

+ 100mV

(2)

Input Low Voltage

-0.3

(1)

____

0.7

Input Low Voltage -

ZZ, OPT, PIPE/FT

-0.3

(1)

____

0.2

5666 tbl 05a

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings

(1)

Symbol

Rating

Commercial

& Industrial

Unit

TERM

)

Terminal Voltage

with Respect to GND

-0.5 to 3.6

TERM

(2)

DDQ

)

DDQ

Terminal Voltage

with Respect to GND

-0.3 to V

DDQ

+ 0.3

TERM

(2)

(INPUTS and I/O's)

Input and I/O Terminal

Voltage with Respect to GND

-0.3 to V

DDQ

+ 0.3

BIAS

(3)

Temperature Under Bias

-55 to +125

STG

Storage Temperature

-65 to +150

Junction Temperature

+150

OUT

(For V

DDQ

3.3V) DC Output Current

OUT

(For V

DDQ

2.5V) DC Output Current

5666 tbl 06

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has reached its

nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed V

DDQ

during power supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, F = 1.0MH

) PQFP ONLY

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

10.5

5666 tbl 07

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 2.5V ± 100mV)

Symbol

Parameter

Test Conditions

70T3519/99/89S

Unit

Min.

Max.

Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

µA

JTAG & ZZ Input Leakage Current

(1,2)

DD =

Max.

= 0V to V

___

±30

µA

Output Leakage Current

(1,3)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

µA

(3.3V)

Output Low Voltage

(1)

= +4mA, V

DDQ

= Min.

___

0.4

(3.3V)

Output High Voltage

(1)

= -4mA, V

DDQ

= Min.

2.4

___

(2.5V)

Output Low Voltage

(1)

= +2mA, V

DDQ

= Min.

___

0.4

(2.5V)

Output High Voltage

(1)

= -2mA, V

DDQ

= Min.

2.0

___

5666 tbl 08

NOTES:
1. V

DDQ

is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(3)

= 2.5V ± 100mV)

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS".

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V

= 2.5V, T

= 25°C for Typ, and are not production tested. I

DD DC

(f=0)

= 15mA (Typ).

5. CE

= V

means CE

= V

and CE

= V

means CE

= V

or CE

= V

< 0.2V means CE

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means CE

> V

- 0.2V or CE

- 0.2V

"X" represents "L" for left port or "R" for right port.

6. I

, I

and

will all reach full standby levels

(

on the appropriate port(s) if ZZ

and/or ZZ

= V

7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DR-208 packages.

70T3519/99/89

S200

Com'l Only

(8)

70T3519/99/89

S166

Com'l

& Ind

(7)

70T3519/99/89

S133

Com'l

& Ind

Symbol

Parameter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynamic Operating
Current (Both
Ports Active)

and CE

= V

Outputs Disabled,

f = f

MAX

(1)

COM'L

375

525

320

450

260

370

IND

___

320

510

260

450

SB1

(6)

Standby Current
(Both Ports - TTL
Level Inputs)

= CE

= V

f = f

MAX

(1)

COM'L

205

270

175

230

140

190

IND

___

175

275

140

235

SB2

(6)

Standby Current
(One Port - TTL
Level Inputs)

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,
f=f

MAX

(1)

COM'L

300

375

250

325

200

250

IND

___

250

365

200

310

SB3

Full Standby Current
(Both Ports - CMOS
Level Inputs)

Both Ports CE

and

> V

DDQ

- 0.2V, V

> V

DDQ

- 0.2V

or V

< 0.2V, f = 0

(2)

COM'L

IND

___

SB4

(6)

Full Standby Current
(One Port - CMOS
Level Inputs)

"A"

< 0.2V and CE

"B"

> V

DDQ

- 0.2V

(5)

> V

DDQ

- 0.2V or V

< 0.2V

Active Port, Outputs Disabled, f = f

MAX

(1)

COM'L

300

375

250

325

200

250

IND

___

250

365

200

310

Izz

Sleep Mode Current
(Both Ports - TTL
Level Inputs)

L =

R =

f=f

MAX

(1)

COM'L

IND

___

5666 tbl 09

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)

(2,3)

= 2.5V ± 100mV, T

= 0°C to +70°C)

NOTES:
1. The Pipelined output parameters (t

CYC2

, t

CD2

) apply to either or both left and right ports when FT/PIPE

= V

(2.5V). Flow-through parameters (t

CYC1

, t

CD1

)

apply when FT/PIPE = V

(0V) for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be

treated as DC signals, i.e. steady state during operation.

3. These values are valid for either level of V

DDQ

(3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.

4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DR-208 packages.
6. Guaranteed by design (not production tested).

70T3519/99/89

S200

Com'l Only

(5)

70T3519/99/89

S166

Com'l

& Ind

(4)

70T3519/99/89

S133

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC1

Clock Cycle Time (Flow-Through)

(1)

____

CYC2

Clock Cycle Time (Pipelined)

(1)

____

7.5

____

CH1

Clock High Time (Flow-Through)

(1)

____

CL1

Clock Low Time (Flow-Through)

(1)

____

CH2

Clock High Time (Pipelined)

(2)

____

2.4

____

CL2

Clock Low Time (Pipelined)

(1)

____

2.4

____

Address Setup Time

1.5

____

1.7

____

1.8

____

Address Hold Time

0.5

____

0.5

____

0.5

____

Chip Enable Setup Time

1.5

____

1.7

____

1.8

____

Chip Enable Hold Time

0.5

____

0.5

____

0.5

____

Byte Enable Setup Time

1.5

____

1.7

____

1.8

____

Byte Enable Hold Time

0.5

____

0.5

____

0.5

____

R/W Setup Time

1.5

____

1.7

____

1.8

____

R/W Hold Time

0.5

____

0.5

____

0.5

____

Input Data Setup Time

1.5

____

1.7

____

1.8

____

Input Data Hold Time

0.5

____

0.5

____

0.5

____

SAD

ADS

Setup Time

1.5

____

1.7

____

1.8

____

HAD

ADS

Hold Time

0.5

____

0.5

____

0.5

____

SCN

CNTEN

Setup Time

1.5

____

1.7

____

1.8

____

HCN

CNTEN

Hold Time

0.5

____

0.5

____

0.5

____

SRPT

REPEAT

Setup Time

1.5

____

1.7

____

1.8

____

HRPT

REPEAT

Hold Time

0.5

____

0.5

____

0.5

____

Output Enable to Data Valid

____

4.4

____

4.4

____

4.6

OLZ

(6)

Output Enable to Output Low-Z

____

OHZ

(6)

Output Enable to Output High-Z

3.4

3.6

4.2

CD1

Clock to Data Valid (Flow-Through)

(1)

____

CD2

Clock to Data Valid (Pipelined)

(1)

____

3.4

____

3.6

____

4.2

Data Output Hold After Clock High

____

CKHZ

(6)

Clock High to Output High-Z

3.4

3.6

4.2

CKLZ

(6)

Clock High to Output Low-Z

____

INS

Interrupt Flag Set Time

____

INR

Interrupt Flag Reset Time

____

COLS

Collision Flag Set Time

____

3.4

____

3.6

____

4.2

COLR

Collision Flag Reset Time

____

3.4

____

3.6

____

4.2

ZZSC

Sleep Mode Set Cycles

____

cycles

ZZRC

Sleep Mode Recovery Cycles

____

cycles

Port-to-Port Delay

Clock-to-Clock Offset

____

OFS

Clock-to-Clock Offset for Collision Detection

Please refer to Collision Detection Timing Table on Page 21

5666 tbl 11

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(3)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

5666 drw 05

(1)

(4)

(1 Latency)

(5)

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE

'X'

= V

)

(1,2)

NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = V

, CNTEN and REPEAT = V

3. The output is disabled (High-Impedance state) by CE

= V

, CE

= V

, BE

= V

following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If BE

was HIGH, then the appropriate Byte of DATA

OUT

for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

Timing Waveform of Read Cycle for Flow-through Output

(FT/PIPE

"X"

= V

)

(1,2,6)

An + 1

An + 2

An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

CKHZ

5666 drw 06

(5)

(1)

(3)

(4)

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

0(B1)

ADDRESS

(B1)

CLK

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

5666 drw 07

Timing Waveform of a Multi-Device Pipelined Read

(1,2)

NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3519/99/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

2. BE

, OE, and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/W, CNTEN, and REPEAT = V

Timing Waveform of a Multi-Device Flow-Through Read

(1,2)

0(B1)

ADDRESS

(B1)

CLK

5666 drw 08

CD1

CKLZ

CKHZ

(1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

CLK

"A"

ADDRESS

"A"

DATA

IN"A"

CLK

"B"

ADDRESS

"B"

DATA

OUT"B"

(3)

CD2

MATCH

VALID

MATCH

VALID

5666 drw 09

Timing Waveform of Left Port Write to Pipelined Right Port Read

(1,2,4)

NOTES:
1. CE

, BE

, and ADS = V

; CE

, CNTEN, and REPEAT = V

2. OE = V

for Port "B", which is being read from. OE = V

for Port "A", which is being written to.

3. If t

< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

+ 2 t

CYC2

+ t

CD2

). If t

> minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port

will be t

+ t

CYC2

+ t

CD2

4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

Timing Waveform with Port-to-Port Flow-Through Read

(1,2,4)

DATA

IN "A"

CLK

"B"

ADDRESS

"A"

CLK

"A"

ADDRESS

"B"

MATCH

VALID

CD1

DATA

OUT "B"

5666 drw 10

VALID

CD1

(3)

NOTES:
1. CE

, BEn, and ADS = V

; CE

, CNTEN, and REPEAT = V

2. OE = V

for the Right Port, which is being read from. OE = V

for the Left Port, which is being written to.

3. If t

< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

+ t

CYC

+ t

CD1

). If t

> minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will

be t

+ t

CD1

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5666 drw 11

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(3)

(1)

WRITE

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = V

)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE

, BE

, and ADS = V

; CE

, CNTEN, and REPEAT = V

. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

5666 drw 12

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ

WRITE

READ

(3)

(1)

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE

, BE

, and ADS = V

; CE

, CNTEN, and REPEAT = V

3. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = V

)

(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE

, BEn, and ADS = V

; CE

, CNTEN, and REPEAT = V

3. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5666 drw 13

DATA

OUT

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ

NOP

READ

CKLZ

(3)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

(3)

DATA

Dn + 2

CLK

5666 drw 14

DATA

OUT

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ

WRITE

READ

CKLZ

(1)

Dn + 3

OHZ

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

CYC2

CLK

DATA

REPEAT

5666 drw 18

INTERNAL

(3)

ADDRESS

ADS

CNTEN

WRITE TO

ADS

ADDRESS

ADVANCE
COUNTER
WRITE TO

An+1

ADVANCE
COUNTER
WRITE TO

An+2

HOLD

COUNTER
WRITE TO

An+2

REPEAT

READ LAST

ADS

ADDRESS

DATA

OUT

SAD

HAD

SCN

HCN

SRPT

HRPT

CD1

An+1

An+2

An+1

An+2

An+1

An+2

ADVANCE
COUNTER

READ

An+1

ADVANCE
COUNTER

READ

An+2

HOLD

COUNTER

READ

An+2

(4)

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)

(1)

Timing Waveform of Counter Repeat

(2,6)

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5666 drw 17

INTERNAL

(3)

ADDRESS

(7)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

HCN

NOTES:

1. CE

, BE

, and R/W = V

; CE

and REPEAT = V

2. CE

, BE

= V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when ADS = V

and equals the counter output when ADS = V

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS

load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is

written to during this cycle.

6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Truth Table III -- Interrupt Flag

(1)

Left Port

Right Port

Function

CLK

R/W

(2)

17L

-A

(3,4,5)

INT

CLK

R/W

(2)

17R

-A

(3,4,5)

INT

3FFFF

Set Right INT

Flag

3FFFF

Reset Right INT

Flag

3FFFE

Set Left INT

Flag

3FFFE

Reset Left INT

Flag

5666 tbl 12

NOTES:

1. INT

and INT

must be initialized at power-up by Resetting the flags.

2. CE

0 =

and

1 =

R/W and CE

are synchronous with respect to the clock and need valid set-up and hold times.

3. A17

is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.

4. A17

and A16

are NC's for IDT70T3589, therefore Interrupt Addresses are FFFF and FFFE.

5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Waveform of Interrupt Timing

(2)

NOTES:

1. CE

0 =

and

1 =

2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

3FFFF

CLK

(1)

ADDRESS

(3)

3FFFF

INR

CLK

ADDRESS

(3)

(1)

5666 drw 19

INT

INS

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

(3)

COLS

COLR

COLS

COLR

5666 drw 20

COL

(4)

CLK

ADDRESS

OFS

(4)

CLK

ADDRESS

OFS

Waveform of Collision Timing

(1,2)

Both

Ports Writing with Left Port Clock Leading

NOTES:

1. CE

= V

, CE

= V

2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t

CYC

+ t

COLS

after Address match.

4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Collision Detection Timing

(3,4)

Cycle Time

OFS

(ns)

Region 1 (ns)

(1)

Region 2 (ns)

(2)

5ns

0 - 2.8

2.81 - 4.6

6ns

0 - 3.8

3.81 - 5.6

7.5ns

0 - 5.3

5.31 - 7.1

5666 tbl 13

NOTES:

1. Region 1

Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.

2. Region 2

Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.

3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.

Left Port

Right Port

Function

CLK

R/W

(1)

17L

-A

(2)

COL

CLK

R/W

(1)

17R

-A

(2)

COL

MATCH

Both ports reading. Not a valid collision.

No flag output on either port.

MATCH

Left port reading, Right port writing.

Valid collision, flag output on Left port.

MATCH

Right port reading, Left port writing.

Valid collision, flag output on Right port.

MATCH

Both ports writing. Valid collision. Flag

output on both ports.

5666 tbl 14

Truth Table IV -- Collision Detection Flag

NOTES:

1. CE

0 =

and

1 =

R/W and CE

are synchronous with respect to the clock and need valid set-up and hold times.

2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70T3519/99/89 provides a true synchronous Dual-Port Static

RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.

An asynchronous output enable is provided to ease asyn-

chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.

A HIGH on CE

or a LOW on CE

for one clock cycle will power down

the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3519/99/89s for depth
expansion configurations. Two cycles are required with CE

LOW and

HIGH to re-activate the outputs.

Interrupts

If the user chooses the interrupt function, a memory location (mail

box or message center) is assigned to each port. The left port interrupt
flag (INT

) is asserted when the right port writes to memory location

3FFFE (HEX), where a write is defined as CE

= R/W

= V

per the

Truth Table. The left port clears the interrupt through access of
address location 3FFFE when CE

= V

and R/WL = V

. Likewise, the

right port interrupt flag (INT

) is asserted when the left

port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INT

), the right port must read the memory location 3FFFF (1FFFF

or 1FFFE for IDT70T3599 and FFFF or FFFE for IDT70T3589). The
message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T3599
and FFFF or FFFE for IDT70T3589) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3599 and
FFFF or FFFE for IDT70T3589) are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table III for the interrupt
operation.

Collision Detection

Sleep Mode

The IDT70T3519/99/89 is equipped with an optional sleep or low

power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagram shows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.

For normal operation all inputs must meet setup and hold times prior

to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V

) and three cycles after de-asserting ZZ (ZZx = V

), the device

must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = V

)when chip enable is asserted, and the chip

enable must be valid for one full cycle before a read will result in the output
of valid data.

During sleep mode the RAM automatically deselects itself. The RAM

disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (I

). All outputs will remain in

high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.

Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port's
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.

The alert flag

(COL

) is asserted on the 2nd or 3rd rising clock

edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision Detection Timing table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert

Collision detection on the IDT70T3519/99/89 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3519/99/89 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problem within the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD's or
FPGA's. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.

flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timing waveform on Page
21.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

JTAG AC Electrical

Characteristics

(1,2,3,4)

70T3519/99/89

Symbol

Parameter

Min.

Max.

Units

JCYC

JTAG Clock Input Period

100

____

JCH

JTAG Clock HIGH

____

JCL

JTAG Clock Low

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset

____

JRSR

JTAG Reset Recovery

____

JCD

JTAG Data Output

____

JDC

JTAG Data Output Hold

____

JTAG Setup

____

JTAG Hold

____

5666 tbl 15

NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5666 drw 24

Figure 5. Standard JTAG Timing

NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.

6.42

IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field

Value

Description

Revision Number (31:28)

0x0

Reserved for version number

IDT Device ID (27:12)

0x330

(1)

Defines IDT part number

IDT JEDEC ID (11:1)

0x33

Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0)

Indicates the presence of an ID register

5666 tbl 16

NOTE:
1. Device ID for IDT70T3599 is 0x331. Device ID for IDT70T3589 is 0x332.

Scan Register Sizes

Register Name

Bit Size

Instruction (IR)

Bypass (BYR)

Identification (IDR)

Boundary Scan (BSR)

Note (3)

5666 tbl 17

System Interface Parameters

Instruction

Code

Description

EXTEST

0000

Forces contents of the boundary scan cells onto the device outputs

(1)

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS

1111

Places the bypass register (BYR) between TDI and TDO.

IDCODE

0010

Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.

HIGHZ

0100

Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.

CLAMP

0011

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

SAMPLE/PRELOAD

0001

Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs

(2)

to be captured in the

boundary scan cells and shifted serially through TDO. PRELOAD allows

data to be input serially into the boundary scan cells via the TDI.

RESERVED

0101, 0111, 1000, 1001,

1010, 1011, 1100

Several combinations are reserved. Do not use codes other than those

identified above.

PRIVATE

0110,1110,1101

For internal use only.

5666 tbl 18

NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

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