6.07
MARCH 2000
DSC-2942/7
1
2000 Integrated Device Technology, Inc.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
13L
A
0L
2942 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/
W
L
SEM
L
INT
L
M/
S
BUSY
R
I/O
0R
-I/O
7R
A
13R
A
0R
SEM
R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
14
14
R/W
R
,
IDT70V06S/L
HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
Features
x
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
x
x
x
x
High-speed access
Commercial: 15/20/25/35/55ns (max.)
Industrial: 20/25/35/55ns (max.)
x
x
x
x
x
Low-power operation
IDT70V06S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
IDT70V06L
Active: 380mW (typ.)
Standby: 660mW (typ.)
x
x
x
x
x
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
x
x
x
x
x
M/
S = V
IH
for
BUSY output flag on Master
M/
S = V
IL
for
BUSY input on Slave
x
x
x
x
x
Interrupt Flag
x
x
x
x
x
On-chip port arbitration logic
x
x
x
x
x
Full on-chip hardware support of semaphore signaling
between ports
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
Battery backup operation--2V data retention
x
x
x
x
x
TTL-compatible, single 3.3V (0.3V) power supply
x
x
x
x
x
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
x
x
x
x
x
Industrial temperature range (-40C to +85C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER):
BUSY is output; (SLAVE): BUSY is input.
2.
BUSY outputs and INT outputs are non-tri-stated push-pull.
2
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2942 drw 02
12
13
14
15
16
17
18
INDEX
19
20
21
22
9
8
7
6
5
4
3
2
1 68 67 66 65
27 28 29 30 31 32 33 34 35 36 37 38 39
V
C
C
V
CC
I/O
1R
I/O
2R
I/O
3R
I/O
4R
INT
L
GND
A
4L
A
3L
A
2L
A
1L
A
0L
A
3R
A
0R
A
1R
A
2R
I/O
2L
A
5L
R
/
W
L
11
10
M/
S
23
24
25
26
40 41 42 43
58
57
56
55
54
53
52
51
50
49
48
59
60
47
46
45
44
64 63 62 61
I/O
3L
GND
I/O
0R
V
CC
A
4R
BUSY
L
GND
BUSY
R
INT
R
A
1
2
R
I
/
O
7
R
N
/
C
G
N
D
O
E
R
R
/
W
R
S
E
M
R
C
E
R
O
E
L
S
E
M
L
C
E
L
N
/
C
I
/
O
0
L
I
/
O
1
L
IDT70V06J
J68-1
(4)
68-Pin PLCC
Top View
(5)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
5R
I/O
6R
N
/
C
A
1
2
L
N
/
C
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
A
6
L
A
1
3
R
A
1
3
L
Description
The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port
Static RAM or as a combination MASTER/SLAVE Dual-Port Static
RAM for 16-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port Static RAM approach in 16-bit or wider memory
system applications results in full-speed, error-free operation without
the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 400mW of power.
The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations
(1,2,3)
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in
PN-64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
INDEX
70V06PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
I/O
2L
V
CC
GND
GND
A
4R
BUSY
L
BUSY
R
INT
R
INT
L
GND
M/
S
O
E
L
A
5
L
I
/
O
1
L
R
/
W
L
C
E
L
S
E
M
L
V
C
C
O
E
R
C
E
R
R
/
W
R
S
E
M
R
A
1
2
R
G
N
D
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I
/
O
6
R
I
/
O
7
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
3R
A
2R
A
1R
A
0R
A
0L
A
1L
A
2L
A
3L
A
4L
A
6
L
A
7
L
A
8
L
A
9
L
A
1
0
L
A
1
1
L
A
1
2
L
I
/
O
0
L
2942 drw 03
A
1
3
R
A
1
3
L
,
6.42
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Names
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Configurations
(1,2,3)
(con't.)
2942
drw 04
51
50
48
46
44
42
40
38
36
53
55
57
59
61
63
65
67
68
66
1
3
5
7
9
11
13
15
20
22
24
26
28
30
32
35
IDT70V06G
G68-1
(4)
68-Pin PGA
Top View
(5)
A
B
C
D
E
F
G
H
J
K
L
47
45
43
41
34
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
19
17
56
58
60
62
64
11
10
09
08
07
06
05
04
03
02
01
52
54
49
39
37
A
5L
INT
L
N/C
SEM
L
CE
L
V
CC
OE
L
R/
W
L
I/O
0L
N/C
GND
GND
I/O
0R
V
CC
N/C
OE
R
R/
W
R
SEM
R
CE
R
GND
BUSY
R
BUSY
L
M/
S
INT
R
N/C
GND
A
1R
INDEX
A
4L
A
2L
A
0L
A
3R
A
2R
A
4R
A
5R
A
7R
A
6R
A
9R
A
8R
A
11R
A
10R
A
12R
A
0R
A
7L
A
6L
A
3L
A
1L
A
9L
A
8L
A
11L
A
10L
A
12L
V
CC
I/O
2R
I/O
3R
I/O
5R
I/O
6R
I/O
1R
I/O
4R
I/O
7R
I/O
1L
I/O
2L
I/O
4L
I/O
7L
I/O
3L
I/O
5L
I/O
6L
A
13R
A
13L
,
Left Port
Right Port
Names
CE
L
CE
R
Chip Enable
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/
S
Master or Slave Select
V
CC
Power
GND
Ground
2942 tbl 01
4
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Truth Table II: Semaphore Read/Write Control
(1)
NOTE:
1.
A
0L
-- A
13L
A
0R
-- A
13R
NOTE:
1.
There are eight semaphore flags written to via I/O
0
and read from I/O
0
- I/O
7
. These eight semaphores are addressed by A
0
- A
2
.
Inputs
(1)
Outputs
Mode
CE
R
/
W
OE
SEM
I/O
0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to Memory
L
H
L
H
DATA
OUT
Read Memory
X
X
H
X
High-Z
Outputs Disabled
2942 tbl 02
Inputs
Outputs
Mode
CE
R/
W
OE
SEM
I/O
0-7
H
H
L
L
DATA
OUT
Read Data in Semaphore Flag
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
____
Not Allowed
2942 tbl 03
6.42
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage
(1)
Absolute Maximum Ratings
(1)
Capacitance
(T
A
= +25C, f = 1.0MHz)
NOTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 0.3V.
NOTE:
1.
This is the parameter T
A
.
NOTES:
1.
V
IL
> -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed V
CC
+0.3V.
NOTES:
1.
This parameter is determined by device characterization but is not production
tested.
2.
3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
I
OUT
DC Output
Current
50
mA
2942 tbl 04
Grade
Ambient Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
2942 tbl 05
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
2942 tbl 07
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2942 tbl 06
Symbol
Parameter
Test Conditions
70V06S
70V06L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
2942 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
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