2003 Integrated Device Technology, Inc.
1
JUNE 2003
DSC-5643/1
I/O
Control
Address
Decoder
32Kx9
MEMORY
ARRAY
70V17
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/
W
L
A
14L
A
0L
I/O
0-8L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
R/
W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/
W
R
CE
0R
A
14R
A
0R
I/O
0-8R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/
S
(1)
CE
1L
R/
W
R
CE
0R
OE
R
CE
1R
5643 drw 01
1L
CE
1R
CE
15
15
.
Functional Block Diagram
M/S = V
IH
for BUSY output flag on Master,
M/S = V
IL
for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (40C to +85C) is available
for selected speeds
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
Commercial: 15/20ns (max.)
Industrial: 20ns (max.)
Low-power operation
IDT70V17L
Active: 440mW (typ.)
Standby: 660W (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V17 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
HIGH-SPEED 3.3V
32K x 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V17L
NOTES:
1. BUSY is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
IDT70V17L Preliminary
High-Speed 3.3V 32K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V17 is a high-speed 32K x 9 Dual-Port Static RAM. The
IDT70V17 is designed to be used as a stand-alone 288K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-
or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 18-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete
logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by the chip enables (either CE
0
or CE
1
)
permit the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT's CMOS high-performance technology,
these devices typically operate on only 440mW of power.
The IDT70V17 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations
(1,2,3)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V17PF
PN100-1
(4)
100-Pin
TQFP
Top View
(5)
NC
Vss
Vss
OE
R
R/
W
R
SEM
R
CE
1R
CE
0R
NC
NC
Vss
NC
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
NC
5643 drw 02
NC
NC
Vss
OE
L
R/
W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
V
DD
NC
NC
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
N
C
N
C
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
V
D
D
I
/
O
2
R
I
/
O
0
R
V
s
s
V
D
D
I
/
O
0
L
I
/
O
1
L
V
s
s
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
V
s
s
I
/
O
8
L
I
/
O
8
R
N
C
N
C
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
I
N
T
R
B
U
S
Y
R
M
/
S
B
U
S
Y
L
I
N
T
L
N
C
A
0
L
V
s
s
A
2
L
A
3
L
A
5
L
A
6
L
N
C
N
C
A
1
L
A
4
L
06/12/03
3
IDT70V17L Preliminary
High-Speed 3.3V 32K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage
Pin Names
Capacitance
(1)
(T
A
= +25C, f = 1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
N
OTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+ 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50
mA
5643 tbl 02
Grade
Ambient
Temperature
(1)
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5643 tbl 03
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
5643 tbl 05
Left Port
Right Port
Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
DD
Power (3.3V)
Vss
Ground (0V)
5643 tbl 01
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
ss
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
DD
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5643 tbl 04
IDT70V17L Preliminary
High-Speed 3.3V 32K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Truth Table III Semaphore Read/Write Control
(1)
Truth Table I Chip Enable
(1,2)
NOTES:
1. Chip Enable references are shown above with the actual CE
0
and CE
1
levels; CE is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or >V
DD
-0.2V.
Truth Table II Non-Contention Read/Write Control
NOTES:
1. A
0L
-- A
14L
A
0R
-- A
14R
2. Refer to Chip Enable Truth Table.
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
8
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
DD
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
DD
-0.2V
X
(3)
Port Deselected (CMOS Inactive)
X
(3)
<0.2V
Port Deselected (CMOS Inactive)
5643 bl 06
Inputs
(1)
Outputs
Mode
CE
(2)
R/W
OE
SEM
I/O
0-8
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to Memory
L
H
L
H
DATA
OUT
Read Memory
X
X
H
X
High-Z
Outputs Disabled
5643 tbl 07
Inputs
Outputs
Mode
CE
(2)
R/W
OE
SEM
I/O
0-8
H
H
L
L
DATA
OUT
Read Semaphore Flag Data Out
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
______
Not Allowed
5643 tbl 08
5
IDT70V17L Preliminary
High-Speed 3.3V 32K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
DD
= 3.3V 0.3V)
NOTES:
1. V
DD
= 3.3V, T
A
= +25C, and are not production tested. I
DDDC
= 90mA (Typ.)
2. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using "AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V 0.3V)
NOTES:
1. At V
DD
<
2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
Symbol
Parameter
Test Conditions
70V17L
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
5
A
|I
LO
|
Output Leakage Current
CE
(2)
= V
IH
, V
OUT
= 0V to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
V
5643 tbl 09
70V17L15
Com'l Only
70V17L20
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.
(1)
Max.
Typ.
(1)
Max.
Unit
I
DD
Dynamic Operating
Current
(Both Ports Active)
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(2)
COM'L
L
145
235
135
205
mA
IND
L
___
___
135
220
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(2)
COM'L
L
40
70
35
55
mA
IND
L
___
___
35
65
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2)
,
SEM
R
= SEM
L
= V
IH
COM'L
L
100
155
90
140
mA
IND
L
___
___
90
150
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and CE
R
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or V
IN
< 0.2V, f = 0
(3)
SEM
R
= SEM
L
> V
DD
- 0.2V
COM'L
L
0.2
3.0
0.2
3.0
mA
IND
L
___
___
0.2
3.0
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and CE
"B"
> V
DD
- 0.2V
(4)
,
SEM
R
= SEM
L
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or V
IN
< 0.2V,
Active Port Outputs Disabled, f = f
MAX
(2)
COM'L
L
95
150
90
135
mA
IND
L
___
___
90
145
5643 tbl 10
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