Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
9.4
DSC-2966/5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
256K x 4 advanced high-speed CMOS static RAM
Equal access and cycle times
-- Commercial: 12/15/17/20ns
One Chip Select plus one Output Enable pin
Bidirectional data Inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 400 mil Plastic SOJ package
DESCRIPTION:
The IDT71028 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT's high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71028 has an output enable pin which operates as
fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71028 are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ
package.
FUNCTIONAL BLOCK DIAGRAM
A
17
A
0
I/O CONTROL
I/O
0
I/O
3
CONTROL
LOGIC
WE
OE
CS
2966 drw 01
4
4
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
1
CMOS STATIC RAM
1 MEG (256K x 4-BIT)
IDT71028
9.4
2
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter Min. Typ. Max.
Unit
V
CC
Supply Voltage 4.5 5.0 5.5
V
GND
Supply Voltage 0 0 0
V
V
IH
Input High Voltage 2.2 -- V
CC
+0.5
V
V
IL
Input Low Voltage 0.5
(1)
-- 0.8
V
NOTE:
2966 tbl 04
1. V
IL
(min.) = 1.5V for pulse width less than 10ns, once per cycle.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com'l.
Unit
V
TERM
(2)
Terminal Voltage with
0.5 to +7.0
V
Respect to GND
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
55 to +125
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
NOTES:
2966 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
PIN CONFIGURATION
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
8
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
8
pF
NOTE:
2966 tbl 03
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
(3)
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
10%
IDT71028
Symbol
Parameter
Test Condition
Min. Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
-- 5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
-- 5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
-- 0.4
V
V
OH
Output High Voltage
I
OH
= 4mA, V
CC
= Min.
2.4 --
V
2966 tbl 05
SOJ
TOP VIEW
5
6
7
8
9
12
13
14
GND
A
0
A
1
A
2
1
2
3
4
28
27
26
25
24
23
22
21
20
17
16
15
SO28-6
A
3
A
4
A
5
A
7
A
17
A
16
A
15
A
14
NC
A
13
OE
WE
I/O
0
2966 drw 02
A
8
10
19
A
12
A
9
11
18
A
11
A
10
V
CC
A
6
CS
I/O
1
I/O
2
I/O
3
TRUTH TABLE
(1,2)
CS
CS
OE
OE
WE
WE
I/O
Function
L
L
H DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected - Standby (I
SB
)
V
HC
X
X
High-Z
Deselected - Standby (I
SB1
)
NOTES:
2966 tbl 01
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
V
HC
or
V
LC
.
9.4
3
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
71028S12
(3)
71028S15
71028S17
71028S20
Symbol
Parameter
Com'l. Mil.
Com'l. Mil.
Com'l. Mil. Com'l. Mil.
Unit
I
CC
Dynamic Operating Current,
155
--
150
--
145
--
145
--
mA
CS
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
I
SB
Standby Power Supply Current
35
--
35
--
35
--
35
--
mA
(TTL Level),
CS
V
IH
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
I
SB1
Full Standby Power Supply Current
10
--
10
--
10
--
10
--
mA
(CMOS Level),
CS
V
HC
, Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
V
LC
or V
IN
V
HC
NOTES:
2966 tbl 06
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
3. 12ns specification is preliminary.
2966 drw 04
480
255
5pF*
DATA
OUT
5V
*Including jig and scope capacitance.
2966 drw 03
480
255
30pF
DATA
OUT
5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2966 tbl 07
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
9.4
4
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
10%, Commercial Temperature Range)
71028S12
(1)
71028S15
71028S17
71028S20
Symbol
Parameter
Min. Max.
Min. Max. Min.
Max. Min. Max.
Unit
Read Cycle
t
RC
Read Cycle Time
12
--
15
--
17
--
20
--
ns
t
AA
Address Access Time
--
12
--
15
--
17
--
20
ns
t
ACS
Chip Select Access Time
--
12
--
15
--
17
--
20
ns
t
CLZ
(2)
Chip Select to Output in Low-Z
3
--
3
--
3
--
3
--
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
0
6
0
7
0
8
0
8
ns
t
OE
Output Enable to Output Valid
--
6
--
7
--
8
--
8
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
0
--
0
--
0
--
0
--
ns
t
OHZ
(2)
Output Disable to Output in High-Z
0
5
0
5
0
6
0
7
ns
t
OH
Output Hold from Address Change
4
--
4
--
4
--
4
--
ns
t
PU
(2)
Chip Select to Power Up Time
0
--
0
--
0
--
0
--
ns
t
PD
(2)
Chip Deselect to Power Down Time
--
12
--
15
--
17
--
20
ns
Write Cycle
t
WC
Write Cycle Time
12
--
15
--
17
--
20
--
ns
t
AW
Address Valid to End of Write
10
--
12
--
13
--
15
--
ns
t
CW
Chip Select to End of Write
10
--
12
--
13
--
15
--
ns
t
AS
Address Set-up Time
0
--
0
--
0
--
0
--
ns
t
WP
Write Pulse Width
10
--
12
--
13
--
15
--
ns
t
WR
Write Recovery Time
0
--
0
--
0
--
0
--
ns
t
DW
Data Valid to End of Write
7
--
8
--
9
--
9
--
ns
t
DH
Data Hold Time
0
--
0
--
0
--
0
--
ns
t
OW
(2)
Output Active from End of Write
3
--
3
--
3
--
4
--
ns
t
WHZ
(2)
Write Enable to Output in High-Z
0
5
0
5
0
7
0
8
ns
NOTES:
2966 tbl 08
1. 12ns specification is preliminary.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
9.4
5
IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
ADDRESS
2966 drw 05
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
V
CC
SUPPLY
CURRENT
t
PU
t
PD
I
CC
I
SB
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
200mV from steady state.
DATA
OUT
ADDRESS
2966 drw 6
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
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