Integrated Device Technology, Inc.
FEATURES:
32K x 8 CMOS static RAM
Equal access and cycle times
-- Commercial: 70ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 28-pin 30 mil Plastic SOJ, 28-pin 300 mil
Plastic Dip, 28-pin 300 mil TSOP Type I, and 28-pin 600
mil Plastic Dip.
DESCRIPTION:
The IDT71256SA is a 262,144-bit medium-speed Static
RAM organized as 32K x 8. It is fabricated using IDT's high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
All bidirectional inputs and outputs of the IDT71256SA are
TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71256SA is packaged in a 28-pin 300 mil Plastic
SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I
and 28-pin 600 mil Plastic Dip.
FUNCTIONAL BLOCK DIAGRAM
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JULY 1996
1996 Integrated Device Technology, Inc.
3567/1
A
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
I/O CONTROL
3567 drw 01
INPUT
DATA
CIRCUIT
WE
CS
V
CC
GND
0
A
14
I/O
0
I/O
7
CONTROL
CIRCUIT
OE
CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256SA70
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
2
PIN CONFIGURATION
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz, SOJ package)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
11
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
11
pF
NOTE:
3567 tbl 03
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
3567 tbl 05
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
10%
IDT71256SA
Symbol
Parameter
Test Condition
Min. Max.
Unit
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
-- 5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
-- 5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
-- 0.4
V
V
OH
Output High Voltage
I
OH
= 4mA, V
CC
= Min.
2.4 --
V
TRUTH TABLE
(1,2)
CS
CS
OE
OE
WE
WE
I/O
Function
L
L
H DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Outputs Disabled
H
X
X
High-Z
Deselected -- Standby (I
SB
)
V
HC
X
X
High-Z
Deselected -- Standby (I
SB1
)
NOTES:
3567 tbl 04
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
0.2V.
3. Other inputs
V
HC
or
V
LC
.
(3)
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter Min. Typ. Max.
Unit
V
CC
Supply Voltage 4.5 5.0 5.5
V
GND
Supply Voltage 0 0 0
V
V
IH
Input High Voltage 2.2 -- V
CC
+0.5
V
V
IL
Input Low Voltage 0.5
(1)
-- 0.8
V
NOTE:
3567 tbl 01
1. V
IL
(min.) = 1.5V for pulse width less than 10ns, once per cycle.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com'l.
Unit
V
TERM
(2)
Terminal Voltage 0.5 to +7.0
V
with Respect
to GND
T
A
Operating
0 to +70
C
Temperature
T
BIAS
Temperature 55 to +125
C
Under Bias
T
STG
Storage
55 to +125
C
Temperature
P
T
Power
1.0
W
Dissipation
I
OUT
DC Output
50
mA
Current
NOTES:
3567 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
3567 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
SO28-5
P28-1
P28-2
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
A
14
WE
A
13
A
8
A
10
A
11
OE
A
12
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
9
16
15
SOJ/DIP
TOP VIEW
3567 drw 03
22
23
24
25
26
27
28
1
2
3
4
5
7
6
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
SO28-8
OE
A
11
A
9
A
8
A
13
A
14
A
7
A
6
A
5
A
4
A
3
A
12
WE
V
CC
TSOP
TOP VIEW
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
3
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
3567 tbl 07
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 1. AC Test Load
*Including jig and scope capacitance.
3567 drw 04
480
255
30pF*
DATA
OUT
5V
3567 drw 05
480
255
5pF*
DATA
OUT
5V
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
71256SA70
Symbol
Parameter
Com'l.
Unit
I
CC
Dynamic Operating Current
130
mA
CS
V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
I
SB
Standby Power Supply Current (TTL Level)
20
mA
CS
V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
I
SB1
Standby Power Supply Current (CMOS Level)
15
mA
CS
V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
V
IN
V
LC
or V
IN
V
HC
NOTES:
3567 tbl 06
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing
.
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
4
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
10%, CommercialTemperature Range Only)
71256SA70
Symbol
Parameter
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
70
--
ns
t
AA
Address Access Time
--
70
ns
t
ACS
Chip Select Access Time
--
70
ns
t
CLZ
(2)
Chip Select to Output in Low-Z
4
--
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
0
11
ns
t
OE
Output Enable to Output Valid
--
11
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
0
--
ns
t
OHZ
(2)
Output Disable to Output in High-Z
0
10
ns
t
OH
Output Hold from Address Change
3
--
ns
t
PU
(2)
Chip Select to Power Up Time
0
--
ns
t
PD
(2)
Chip Deselect to Power Down Time
--
25
ns
Write Cycle
t
WC
Write Cycle Time
70
--
ns
t
AW
Address Valid to End of Write
20
--
ns
t
CW
Chip Select to End of Write
20
--
ns
t
AS
Address Set-up Time
0
--
ns
t
WP
Write Pulse Width
20
--
ns
t
WR
Write Recovery Time
0
--
ns
t
DW
Data Valid to End of Write
13
--
ns
t
DH
Data Hold Time
0
--
ns
t
OW
(2)
Output Active from End of Write
4
--
ns
t
WHZ
(2)
Write Enable to Output in High-Z
0
11
ns
NOTES:
3567 tbl 08
1. 0
to +70
C temperature range only.
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
ADDRESS
OE
CS
DATA
OUT
V
CC
SUPPLY
CURRENT
3567 drw 06
(5)
(5)
(5)
(5)
DATA VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
OUT
t
PU
t
PD
I
CC
I
SB
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
5
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WE
WE
CONTROLLED TIMING)
(1,2,3,5)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn
off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified t
WP
.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CS
CS
CONTROLLED TIMING)
(1,2,5)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address must be valid prior to or coincident with the later of
CS
transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
200mV from steady state.
DATA
OUT
ADDRESS
3567 drw 07
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
ADDRESS
CS
WE
DATA
OUT
DATA
IN
3567 drw 08
(6)
(4)
(4)
(3)
(6)
(6)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
WR
t
AW
t
DH
CS
ADDRESS
WE
3567 drw 09
DATA
IN
VALID
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
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