Integrated Device Technology, Inc.

HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM

IDT7130SA/LA
IDT7140SA/LA

FEATURES

· High-speed access

--Military: 25/35/55/100ns (max.)
--Commercial: 25/35/55/100ns (max.)
--Commercial: 20ns 7130 in PLCC and TQFP

· Low-power operation

--IDT7130/IDT7140SA

Active: 550mW (typ.)

Standby: 5mW (typ.)

--IDT7130/IDT7140LA

Active: 550mW (typ.)

Standby: 1mW (typ.)

· MASTER IDT7130 easily expands data bus width to

16-or-more-bits using SLAVE IDT7140

· On-chip port arbitration logic (IDT7130 Only)
·

BUSY

output flag on IDT7130;

BUSY

input on IDT7140

· Interrupt flags for port-to-port communication
· Fully asynchronous operation from either port
· Battery backup operation2V data retention (LA only)
· TTL-compatible, single 5V

10% power supply

· Military product compliant to MIL-STD-883, Class B
· Standard Military Drawing #5962-86875
· Industrial temperature range (40

C to +85

C) is avail-

able, tested to military electrical specifications

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION

The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port

Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-
Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

Both devices provide two independent ports with sepa-

rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by

, permits the on chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance tech-

nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200

W from a 2V battery.

The IDT7130/IDT7140 devices are packaged in 48-pin

sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B, making it ideally suited to military tem-
perature applications demanding the highest level of per-
formance and reliability.

FUNCTIONAL BLOCK DIAGRAM

6.01

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

DSC-2689/7

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

BUSY

2689 drw 01

I/O

- I/O

INT

BUSY

I/O

-I/O

INT

(2)

(1,2)

(2)

NOTES:
1. IDT7130 (MASTER):

BUSY

is open

drain output and requires pullup
resistor of 270

IDT7140 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup
resistor of 270

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

PIN CONFIGURATIONS

(1,2)

NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

INDEX

IDT7130/40

PP64-1 & PN64-1

64-PIN STQFP

64-PIN TQFP
TOP VIEW

(3)

8
9

10
11
12
13
14
15
16

1
2
3
4
5
6
7

46
45
44
43
42
41
40
39
38
37
36
35
34

I/O

N/C

I/O

N/C
N/C

I/O

N/C

2689 drw 05

N/C

BUSY

INT

N/C

GND

N/C

GND

N/C

BUSY

INT

I/O

IDT7130/40

L48-1

F48-1

48-PIN LCC/ FLATPACK

TOP VIEW

(3)

INDEX

6 5

4 3

48 47 46 45 44 43

19 20 21 22 23

25 26 27 28 29 30

2689 drw 03

GND

I/O

INT

BUSY

INT

I/O

IDT7130/40

J52-1

52-PIN PLCC
TOP VIEW

(3)

INDEX

N/C

GND

N/C

I/O

2689 drw 04

INT

BUSY

INT

I/O

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

IDT7130/

IDT7140

P48-1

C48-2

DIP

TOP

VIEW

(3)

2689 drw 02

GND

I/O

INT

BUSY

INT

I/O

6.01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7130SA

7130LA

7140SA

7140LA

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Input Leakage

= 5.5V,

Current

(1)

= 0V to V

= GND to V

Output Leakage

= 5.5V,

Current

(1)

= V

, V

OUT

= 0V to V

Output Low Voltage

= 4mA

0.4

(l/O0-l/O

)

= 16mA

Open Drain Output

= 16mA

0.5

Low Voltage (

BUSY

INT

)

Output High Voltage

= -4mA

2.4

mbol

Parameter

Conditions

(2)

Max. Unit

Input Capacitance

= 3dV

OUT

Output Capacitance

= 3dV

2689 tbl 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

TERM

(2)

Terminal Voltage

0.5 to +7.0

with Respect to
GND

Operating

0 to +70

55 to +125

Temperature

BIAS

Temperature

55 to +125

65 to +135

Under Bias

STG

Storage

55 to +125

65 to +150

Temperature

OUT

DC Output

Current

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time

or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.

2689 tbl 01

RECOMMENDED
DC OPERATING CONDITIONS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Supply Voltage

Input High Voltage

2.2

6.0

(2)

Input Low Voltage 0.5

0.8

NOTES:
1. V

(min.) > -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 0.5V.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade

Temperature

GND

Military

C to +125

5.0V

10%

Commercial

C to +70

5.0V

10%

2689 tbl 03

(1)

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

= 5.0V

10%)

NOTES:
1. This parameter is determined by device characterization but is not

production tested.

2. 3dv references the interpolated capacitance when the input and

output signals switch from 0V to 3V or from 3V to 0V.

3. 11pF max. for other packages.

2689 tbl 05

CAPACITANCE

(1)

= +25

C, f = 1.0MHz) TQFP ONLY

(3)

NOTE:

2689 tbl 04

1. At Vcc

2.0V leakages are undefined.

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1,6)

= 5.0V

10%)

7130X20

(2)

7130X25

(3)

7130X35

7130X55

7130X100

7140X25

(3)

7140X35

7140X55

7140X100

Symbol

Parameter

Test Conditions

Version

Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.

Unit

Dynamic Operating

and

= V

, MIL.

110

280

110

230

110 190

Current (Both Ports

Outputs open,

110

220

110

170

110 140

Active)

f = f

MAX

(4)

COM'L. SA

110

250

110

220

110

165

110 155

110

200

110

170

110

120

110 110

SB1

Standby Current

and

= V

, MIL.

(Both Ports - TTL

f = f

MAX

(4)

Level Inputs)

COM'L. SA

SB2

Standby Current

and

MIL.

160

150

125

(One Port - TTL

(7)

125

115

Level Inputs)

Active Port Outputs COM'L. SA

165

150

125

110

Open, f = f

MAX

(4)

125

115

SB3

Full Standby Current

and

MIL.

1.0

(Both Ports - All

> V

-0.2V,

0.2

CMOS Level Inputs

> V

-0.2V or

COM'L. SA

1.0

< 0.2V,f = 0

(5)

0.2

SB4

Full Standby Current

0.2V and

MIL.

155

145

110

(One Port - All

> V

-0.2V

(7)

115

105

CMOS Level Inputs)

> V

-0.2V or

COM'L. SA

155

145

110

100

< 0.2V,

115

105

Active Port Outputs
Open, f = f

MAX

(4)

NOTES:

2689 tbl 06

1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0

C to +70

C temperature range. PLCC and TQFP packages.

3. Not available in DIP packages.
4. At f = f

Max

, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

, and using "AC TEST CONDITIONS"

of input levels of GND to 3V.

5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, T

=+25

C for Typ and is not production tested. Vcc

= 100 mA (Typ.)

7. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

for Data Retention

2.0

CCDR

Data Retention Current

100

4000

100

1500

CDR

Chip Deselect to Data

Retention Time

Operation Recovery

Time

DATA RETENTION CHARACTERISTICS

(LA Version Only)

lDT7130LA/IDT7140LA

Mil.

Com'l.

= 2.0V,

> V

-0.2V

> V

-0.2V or V

< 0.2V

(3)

Test Conditions

2689 tbl 07

(2)

NOTES:
1. V

= 2V, T

= +25

C, and is not production tested.

2. t

= Read Cycle Time

3. This parameter is guaranteed but not production tested.

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(3)

7130X20

(2)

7130X25

(5)

7130X35

7130X55

7130X100

7140X25

(5)

7140X35

7140X55

7140X100

Symbol

Parameter

Min. Max.

Min. Max. Min.

Max. Min. Max. Min.

Max. Unit

Read Cycle

Read Cycle Time

100

Address Access Time

100

ACE

Chip Enable Access Time

100

AOE

Output Enable Access Time

Output Hold From Address Change

Output Low-Z Time

(1,4)

Output High-Z Time

(1,4)

Chip Enable to Power Up Time

(4)

Chip Disable to Power Down Time

(4)

NOTES:

2689 tbl 09

1. Transition is measured

500mV from Low or High-impedance voltage Output Test Load (Figure 2).

2. Com'l Only, 0

C to +70

C temperature range. PLCC and TQFP package.

3. "X" in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

(1)

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

2689 drw 08

BDD

(2,3)

BUSY

OUT

NOTES:
1. R/

= V

, and is

= V

. Address is valid prior to the coincidental with

transition Low.

2. t

BDD

delay is required only in the case where the opposite port is completing a write operation to the same the

address location. For simultaneous read operations,

BUSY

has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last t

AOE

, t

ACE

, t

, and t

BDD

6.01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

(3)

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(5)

7130X20

(2)

7130X25

(6)

7130X35

7130X55

7130X100

7140X25

(6)

7140X35

7140X55

7140X100

Symbol

Parameter

Min.

Max.

Min. Max.

Min.

Max. Min.

Max.

Min.

Max.

Unit

Write Cycle

Write Cycle Time

(3)

100

Chip Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

(4)

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time

(1)

Data Hold Time

Write Enabled to Output in High-Z

(1)

Output Active From End-of-Write

(1)

NOTES:

2689 tbl 10

1. Transition is measured

500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by

device characterization but is not production tested.
2. 0

C to +70

C temperature range only, PLCC and TQFP packages.

3. For MASTER/SLAVE combination, t

= t

BAA

+ t

, since R/

= V

must occur after t

BAA.

4. If

is low during a R/

controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off

data to be placed on the bus for the required t

. If

is High during a R/

controlled write cycle, this requirement does not apply and the

write pulse can be as short as the specified t

5. "X" in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.

tACE

AOE

VALID DATA

50%

DATA

OUT

CURRENT

50%

2689 drw 09

(4)

(1)

(2)

(4)

NOTES:
1. Timing depends on which signal is asserted last,

2. Timing depends on which signal is deaserted first,

3. R/

= V

and the address is valid prior to or coincidental with

transition Low.

4. Start of valid data depends on which timing becomes effective last t

AOE

, t

ACE

, t

, and t

BDD

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (

CONTROLLED TIMING)

(1,5)

NOTES:
1. R/

must be High during all address transitions.

2. A write occurs during the overlap (t

or t

) of

and R/

IL.

3. t

is measured from the earlier of

or R/

going High to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the

Low transition occurs simultaneously with or after the R/

Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

or R/

) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state

with the Output Test Load (Figure 2).

8. If

is low during a R/

controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off

and data to be placed on the bus for the required t

. If

is High during a R/

controlled write cycle, this requirement does not apply and

the write pulse can be as short as the specified t

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/

CONTROLLED TIMING)

(1,5,8)

ADDRESS

DATA

OUT

DATA

WP(2)

(4)

2689 drw 10

(6)

(7)

(3)

(7)

ADDRESS

DATA

2689 drw 11

(6)

(2)

(3)

6.01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(7)

M824S258M824S30

7132158M824S4

7130X20

(1)

7130X25

(9)

7130X35

7130X55

7130X100

7140X25

(9)

7140X35

7140X55

7140X100

Symbol

Parameter

Min. Max.

Min. Max. Min. Max.

Unit

Busy Timing (For Master lDT7130 Only)

BAA

BUSY

Access Time from Address

BDA

BUSY

Disable Time from Address

BAC

BUSY

Access Time from Chip Enable

BDC

BUSY

Disable Time from Chip Enable

Write Hold After

BUSY

(6)

WDD

Write Pulse to Data Delay

(2)

120

DDD

Write Data Valid to Read Data Delay

(2)

100

APS

Arbitration Priority Set-up Time

(3)

BDD

BUSY

Disable to Valid Data

(4)

Busy Timing (For Slave IDT7140 Only)

Write to

BUSY

Input

(5)

Write Hold After

BUSY

(6)

WDD

Write Pulse to Data Delay

(2)

120

DDD

Write Data Valid to Read Data Delay

(2)

100

NOTES:

2689 tbl 11

1. Com'l Only, 0

C to +70

C temperature range. PLCC and TQFP packages only.

2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

BUSY

3. To ensure that the earlier of the two ports wins.
4. t

BDD

is a calculated parameter and is the greater of 0, t

WDD

(actual), or t

DDD

(actual).

5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. "X" in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages.

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND

BUSY

BDD

DDD

BDA

WDD

ADDR

'B'

DATA

OUT'B'

DATA

IN'A'

ADDR

'A'

MATCH

VALID

MATCH

VALID

'A'

BUSY

'B'

APS

2689 drw 12

(1)

NOTES:

1. To ensure that the earlier of the two ports wins.

BDD

is ignored for slave (IDT7140).

= V

IL.

3. OE = V

for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

(2,3,4)

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

TIMING WAVEFORM OF WRITE WITH

BUSY

(3)

BUSY

'B'

2689 drw 13

'A'

'B'

(2)

(1)

NOTES:
1. t

must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY

TIMING

(1)

TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING

(1)

NOTES:
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. If t

APS

is not satisified, the

BUSY

will be asserted on one side or the other, but there is no guarantee on which side

BUSY

will be

asserted (7130 only).

APS

ADDR

'A'

AND

'B'

ADDRESSES MATCH

BAC

BDC

'B'

'A'

BUSY

'A'

2689 drw 14

(2)

BUSY

'B'

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

APS

ADDR

'A'

ADDR

'B'

2689 drw 15

(2)

BAA

BDA

6.01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(2)

8M824S25

8M824S308M824S35

7130X20

(1)

7130X25

(3)

7130X35

7130X55

7130X100

7140X25

(3)

7140X35

7140X55

7140X100

Symbol

Parameter

Min.

Max.

Min.

Max.

Min. Max.

Min.

Max.

Min.

Max.

Unit

Interrupt Timing

Address Set-up Time

Write Recovery Time

INS

Interrupt Set Time

INR

Interrupt Reset Time

2689 tbl 12

NOTES:
1.

C to +70

C temperature range only, PLCC and TQFP packages.

"X" in part numbers indicates power rating (SA or LA).

Not available in DIP packages .

INT

SET:

TIMING WAVEFORM OF INTERRUPT MODE

INT

CLEAR:

NOTES:.
1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (

or R/

) is asserted last.

4. Timing depends on which enable signal (

or R/

) is de-asserted first.

INS

ADDR

'A'

INT

'B'

INTERRUPT ADDRESS

'A'

2689 drw 16

(3)

(2)

(4)

INTERRUPT CLEAR ADDRESS

ADDR

'B'

INR

INT

'B'

2689 drw 17

(3)

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.01

TRUTH TABLES

TABLE I -- NON-CONTENTION
READ/WRITE CONTROL

(4)

Left or Right Port

(1)

W CE

07

Function

Port Disabled and in Power-
Down Mode, I

SB2

or I

SB4

, Power-Down

Mode, I

SB1

or I

SB3

DATA

Data on Port Written Into Memory

(2)

DATA

OUT

Data in Memory Output on Port

(3)

High Impedance Outputs

NOTES:

2689 tbl 13

1. A

10L

10R

2. If

BUSY

= L, data is not written.

3. If

BUSY

= L, data may not be valid, see t

WDD

and t

DDD

timing.

4. 'H' = V

, 'L' = V

, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE

TABLE III -- ADDRESS BUSY ARBITRATION

Inputs

Outputs

-A

BUSY

(1)

BUSY

(1)

Function

NO MATCH

Normal

MATCH

Normal

MATCH

Normal

MATCH

(2)

Write Inhibit

(3)

NOTES:

2689 tbl 15

1. Pins

BUSY

and

BUSY

are both outputs for IDT7130 (master). Both are

inputs for IDT7140 (slave).

BUSY

outputs on the IDT7130 are open drain,

not push-pull outputs. On slaves the

BUSY

input internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and

enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either

BUSY

= Low will result.

BUSY

and

BUSY

outputs can

not be low simultaneously.

3. Writes to the left port are internally ignored when

BUSY

outputs are

driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when

BUSY

outputs are driving Low regard-

less of actual logic level on the pin.

TABLE II -- INTERRUPT FLAG

(1,4)

Left Port

Right Port

 A

INT

 A

INT

Function

3FF

(2)

Set Right

INT

Flag

3FF

(3)

Reset Right

INT

Flag

(3)

3FE

Set Left

INT

Flag

3FE

(2)

Reset Left

INT

Flag

NOTES:

2689 tbl 14

1. Assumes

BUSY

= V

2. If

BUSY

= V

, then No Change.

3. If

BUSY

= V

, then No Change.

4. 'H' = HIGH,' L' = LOW,' X' = DON'T CARE

6.01

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

The IDT7130/IDT7140 provides two ports with separate con-
trol, address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by

. The

controls on-chip power down circuitry that permits

the respective port to go into a standby mode when not
selected (

= V

). When a port is enabled, access to the

entire memory array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (

INT

) is asserted when the

right port writes to memory location 3FE (HEX), where a write
is defined as the

= R/

= V

per the Truth Table. The left

port clears the interrupt by access address location 3FE
access when

R =

IL,

is a "don't care". Likewise,

the right port interrupt flag (

INT

) is asserted when the left port

writes to memory location 3FF (HEX) and to clear the interrupt
flag (

INT

), the right port must access the memory location

3FF. The message (8 bits) at 3FE or 3FF is user-defined,
since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FE and 3FF are not
used as mail boxes, but as part of the random access
memory. Refer to Table II for the interrupt operation.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is "Busy". The Busy pin can then
be used to stall the access until the operation on the other side
is completed. If a write operation has been attempted from the
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the

BUSY

pin operates solely as a

write inhibit input pin. Normal operation can be programmed
by tying the

BUSY

pins High. If desired, unintended write

operations can be prevented to a port by tying the Busy pin for
that port Low.

The Busy outputs on the IDT7130 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS

When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy
pin is an output if the part is Master (IDT7130), and the Busy
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 4.

If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.

The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/

signal or the byte enables. Failure to

observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.

2689 drw 18

MASTER
Dual Port
RAM

BUSY

(L)

BUSY

(R)

MASTER
Dual Port
RAM

BUSY

(L)

BUSY

(R)

SLAVE
Dual Port
RAM

BUSY

(L)

BUSY

(R)

SLAVE
Dual Port
RAM

BUSY

(L)

BUSY

(R)

BUSY

DECODER

5 V

270

Figure 4. Busy and chip enable routing for both width and depth

expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs.

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