Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

DSC-2720/4

IDT7134SA/LA

HIGH-SPEED
4K x 8 DUAL-PORT
STATIC RAM

FEATURES:

· High-speed access

-- Military: 25/35/45/55/70ns (max.)
-- Commercial: 20/25/35/45/55/70ns (max.)

· Low-power operation

-- IDT7134SA

Active: 500mW (typ.)
Standby: 5mW (typ.)

-- IDT7134LA

Active: 500mW (typ.)
Standby: 1mW (typ.)

· Fully asynchronous operation from either port
· Battery backup operation--2V data retention
· TTL-compatible; single 5V (

10%) power supply

· Available in several popular hermetic and plastic packages
· Military product compliant to MIL-STD-883, Class B
· Industrial temperature range (40

C to +85

C) is available,

tested to military electrical specifications

systems which cannot tolerate wait states or are designed to
be able to externally arbitrate or withstand contention when
both sides simultaneously access the same Dual-Port RAM
location.

The IDT7134 provides two independent ports with separate

control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. It is the user's responsibility to ensure data integrity
when simultaneously accessing the same memory location
from both ports. An automatic power down feature, controlled
by

, permits the on-chip circuitry of each port to enter a very

low standby power mode.

Fabricated using IDT's CMOS high-performance

technology, these Dual-Port typically on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200

from a 2V battery.

The IDT7134 is packaged on either a sidebraze or plastic

48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Ceramic
Flatpack. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

DESCRIPTION:

The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM

designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those

FUNCTIONAL BLOCK DIAGRAM

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

6.04

COLUMN

I/O

COLUMN

I/O

MEMORY

ARRAY

LEFT SIDE

ADDRESS

DECODE

LOGIC

RIGHT SIDE

ADDRESS

DECODE

LOGIC

- A

11L

I/O

- I/O

2720 drw 01

- A

11R

I/O

- I/O

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

(1,2)

NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of actual part-marking.

10R

2720 drw 02

I/O

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

I/O

IDT7134

P481

C482

DIP

TOP

VIEW

(3)

11R

11L

10L

GND

2720 drw 04

IDT7134

L48-1

F48-1

LCC/Flatpack

TOP VIEW

(3)

INDEX

6 5

4 3

48 47 46 45 44 43

19 20 21 22 23

25 26 27 28 29 30

GND

I/O

10L

11L

11R

10R

2720 drw 03

IDT7134

J52-1

PLCC

TOP VIEW (3)

INDEX

N/C

GND

I/O

N/C

I/O

10L

11L

11R

10R

N/C

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Com'l.

Mil.

Unit

TERM

(2)

Terminal Voltage

0.5 to +7.0

with Respect
to Ground

Operating

0 to +70

55 to +125

Temperature

BIAS

Temperature

55 to +125

65 to +135

Under Bias

STG

Storage

55 to +125

65 to +150

Temperature

(3)

Power Dissipation

1.5

OUT

DC Output Current

2720 tbl 01

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2. V

TERM

must not exceed Vcc + 0.5V for more than 25%of the cycle time or

10 ns maximum, and is limited to < 20mA for the period of V

TERM

> Vcc

+0.5V.

CAPACITANCE

(1)

= +25

C, f = 1.0MHz)

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dv

OUT

Output Capacitance

OUT

= 3dv

2720 tbl 02

NOTES:
1. This parameter is determined by device characterization but is not

production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V and from 3V to 0V.

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

= 5.0V

10%)

7134X20

(4)

7134X25

7134X35

7134X45

7134X55

7134X70

Symbol

Parameter

Test Conditions

Version Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

Dynamic Operating

= V

MIL.

160

310

150

300

140

280

140

270

140

270

Current

Outputs Open

160

260

150

250

140

240

140

220

140

220

(Both Ports Active)

f = f

MAX

(3)

COM'L. S

170

280

160

280

150

260

140

240

140

240

140

240

170

240

160

220

150

210

140

200

140

200

140

200

SB1

Standby Current

and

= V

MIL.

100

(Both Ports--TTL

f = f

MAX

(3)

Level Inputs)

COM'L. S

110

SB2

Standby Current

"A"

= V

and

MIL.

210

200

190

180

(One Port--TTL

"B"

= V

170

160

150

Level Inputs)

Active Port Outputs COM'L. S

105

180

170

160

Open, f = f

MAX

(3)

105

150

140

130

SB3

Full Standby Current Both Ports

and MIL.

1.0

(Both Ports--All

- 0.2V

0.2

CMOS Level Inputs) V

- 0.2V or

COM'L. S

1.0

0.2V, f = 0

(3)

0.2

4.5

0.2

4.0

0.2

4.0

0.2

4.0

0.2

4.0

0.2

4.0

SB4

Full Standby Current One Port

"A"

MIL.

210

190

180

170

(One Port--All

"B"

- 0.2V

150

130

120

CMOS Level Inputs) V

- 0.2V or

COM'L. S

105

170

160

150

0.2V

105

130

120

110

100

Active Port Outputs
Open, f = f

MAX

(3)

NOTES:

2720 tbl 06

1. "X" in part number indicates power rating (SA or LA).
2. V

= 5V, T

= +25

C for typical, and parameters are not production tested.

3. f

MAX

= 1/t

= All inputs cycling at f = 1/t

(except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level

standby I

SB3.

4. (Commercial only) 0

C to +70

C temperature range.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade

Temperature

GND

Military

C to +125

5.0V

10%

Commercial

C to +70

5.0V

10%

2720 tbl 03

RECOMMENDED DC OPERATING CONDITIONS

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Ground

Input High Voltage

2.2

6.0

(2)

Input Low Voltage

0.5

(1)

0.8

NOTES:

2720 tbl 04

1. V

(min.) > 1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 0.5V.

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

= 5V

10%)

IDT7134SA

IDT7134LA

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

Output Leakage Current

= V

, V

OUT

= 0V to V

Output Low Voltage

= 6mA

0.4

= 8mA

0.5

Output High Voltage

= 4mA

2.4

NOTE:

2720 tbl 05

1. At Vcc

2.0V input leakages are undefined.

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(LA Version Only) V

= 0.2V, V

= V

- 0.2V

Symbol

Parameter

Test Condition

Min.

Typ.

(1)

Max.

Unit

VCC for Data Retention

= 2V

2.0

CCDR

Data Retention Current

MIL.

100

4000

or < V

COM'L.

100

1500

CDR

(3)

Chip Deselect to Data Retention Time

(3)

Operation Recovery Time

(2)

NOTES:

2720 tbl 07

1. V

= 2V, T

= +25

C, and are not production tested.

2. t

= Read Cycle Time.

3. This parameter is guaranteed by device characterization, but not production tested.

DATA RETENTION WAVEFORM

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

Figures 1 and 2

2720 tbl 08

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for t

, t

)

+5V

1250

30pF *

775

DATA

OUT

2720 drw 06

+5V

1250

5pF *

775

DATA

OUT

2720 drw 07

*Including scope and jig

DATA RETENTION MODE

4.5V

CDR

2720 drw 05

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

(4)

(CONT'D)

7134X45

7134X55

7134X70

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

Address Access Time

ACE

Chip Enable Access Time

AOE

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time

(1, 2)

Output High-Z Time

(1, 2)

Chip Enable to Power Up Time

(2)

Chip Disable to Power Down Time

(2)

NOTES:

2720 tbl 09

1. Transition is measured

500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.
3. (Commercial only) 0

C to +70

C temperature range only.

4. "X" in part number indicates power rating (SA or LA).

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE

(1, 2, 3)

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

(4)

7134X20

(3)

7134X25

7134X35

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

Read Cycle Time

Address Access Time

ACE

Chip Enable Access Time

AOE

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time

(1, 2)

Output High-Z Time

(1, 2)

Chip Enable to Power Up Time

(2)

Chip Disable to Power Down Time

(2)

NOTES:
1. Timing depends on which signal is asserted last,

2. Timing depends on which signal is de-asserted first,

3. R/

= V

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

2720 drw 08

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE

(1, 3)

2720 drw 09

DATA

OUT

VALID DATA

(4)

AOE

(4)

ACE

(2)

(1)

50%

CURRENT

(2)

NOTES:
1. Timing depends on which signal is asserted last,

2. Timing depends on which signal is de-asserted first,

3. R/

= V

4. Start of valid data depends on which timing becomes effective , t

AOE

, t

ACE

or t

5. t

for RAM Address Access and t

SAA

for Semaphore Address Access.

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

(6)

7134X20

(5)

7134X25

7134X35

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

Write Cycle Time

Chip Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

Write RecoveryTime

Data Valid to End-of-Write

Output High-Z Time

(1, 2)

Data Hold Time

(3)

Write Enabled to Output in High-Z

(1, 2)

Output Active from End-of-Write

(1, 2, 3)

WDD

Write Pulse to Data Delay

(4)

DDD

Write Data Valid to Read Data Delay

(4, 7)

NOTES:

2720 tbl 10

1. Transition is measured

500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t

must be met by the device supplying write data to the RAM under all operating conditions. Although t

and t

values will vary

over voltage and temperature, the actual t

will always be smaller than the actual t

4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read".
5. (Commercial only), 0

C to +70

C temperature range .

6. "X" in part number indicates power rating (SA or LA).
7. t

DDD

= 35ns for military temperature range.

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE

(6)

(CONT'D)

7134X45

7134X55

7134X70

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

Write Cycle Time

Chip Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

Write RecoveryTime

Data Valid to End-of-Write

Output High-Z Time

(1, 2)

Data Hold Time

(3)

Write Enabled to Output in High-Z

(1, 2)

Output Active from End-of-Write

(1, 2, 3)

WDD

Write Pulse to Data Delay

(4)

DDD

Write Data Valid to Read Data Delay

(4)

NOTES:
1. Transition is measured

500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t

must be met by the device supplying write data to the RAM under all operating conditions. Although t

and t

values will vary

over voltage and temperature, the actual t

will always be smaller than the actual t

4. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read".
5. (Commercial only), 0

C to +70

C temperature range .

6. "X" in part number indicates power rating (SA or LA).

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ

(1)

2720 tbl 10

L =

R =

IL.

"B"

= V

IL.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.

2720 drw 10

"A"

VALID

MATCH

VALID

MATCH

WDD

DDD

ADDR

"A"

DATA

IN "A"

DATA

OUT "B"

ADDR

"B"

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

CONTROLLED TIMING

(1, 5, 8)

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CONTROLLED TIMING

(1, 5)

NOTES:
1. R/

must be High during all address transitions.

2. A write occurs during the overlap (t

or t

) of a

and R/

= V

3. t

is measured from the earlier of

or R/

going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the

Low transition occurs simultaneously with or after the R/

Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (

or R/

)is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output

Test Load (Figure 2).

8. If

is Low during a R/

controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off data to

be placed on the bus for the required t

. If

is High during an R/

controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified t

2720 drw 12

ADDRESS

DATA

1.20 in

WR(3)

EW(2)

AS(6)

2720 drw 11

AS(6)

DATA

ADDRESS

DATA

OUT

(7)

(4)

(2)

(7)

WR(3)

6.04

IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

TRUTH TABLE I READ/WRITE CONTROL

(2)

Left or Right Port

(1)

0-7

Function

Port Disabled and in Power
Down Mode, I

SB2

or I

SB4

= H, Power Down

Mode, I

SB1

or I

SB3

DATA

Data on port written into
memory

DATA

OUT

Data in memory output on port

High impedance outputs

2720 tbl 11

NOTES:
1. A

- A

11L

- A

11R

2. "H" = HIGH, "L" = LOW, "X" = Don't Care, and "Z" = High-impedance

FUNCTIONAL DESCRIPTION

The IDT7134 provides two ports with separate control,

address, and I/O pins that permit independent access for
reads or writes to any location in memory. These devices have
an automatic power down feature controlled by

. The

controls on-chip power down circuitry that permits the
respective port to go into standby mode when not selected
(

high). When a port is enabled, access to the entire

memory array is permitted. Each port has its own Output
Enable control (

). In the read mode, the port's

turns on

the output drivers when set LOW. Non-contention READ/
WRITE conditions are illustrated in the table below.

2720 drw 13

IDT

XXXX

999

Device Type

Power

Speed

Package

Process/

Temperature

Range

Blank

P
C
J
L48
F

20
25
35
45
55
70

LA
SA

7134

Commercial (0

C to +70

Military (55

C to +125

Compliant to MIL-STD-883, Class B

48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)

Speed in nanoseconds

Low Power
Standard Power

32K (4K x 8-Bit) Dual-Port RAM

Commercial Only

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT7134SA45L48

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT7134SA45L48