JUNE 2002
DSC-3101/07
1
2000 Integrated Device Technology, Inc.
Features
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Ideal for high-performance processor secondary cache
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Commercial (0C to +70C) and Industrial (40C to +85C)
temperature range options
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x
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x
Fast access times:
Commercial and Industrial: 10/12/15/20ns
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x
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x
Low standby current (maximum):
2mA full standby
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x
Small packages for space-efficient layouts:
28-pin 300 mil SOJ
28-pin TSOP Type I
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Produced with advanced high-performance CMOS
technology
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Inputs and outputs are LVTTL-compatible
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Single 3.3V(0.3V) power supply
Description
The IDT71V256SA is a 262,144-bit high-speed static RAM organized
as 32K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOS technology.
The IDT71V256SA has outstanding low power characteristics while
at the same time maintaining very high performance. Address access
times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V
desktop designs.
When power management logic puts the IDT71V256SA in standby
mode, its very low power characteristics contribute to extended battery life.
By taking
CS HIGH, the SRAM will automatically go to a low power standby
mode and will remain in standby as long as
CS remains HIGH. Further-
more, under full standby mode (
CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically will be much
smaller.
The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin
300 mil TSOP Type I.
Functional Block Diagram
A
0
ADDRESS
DECODER
262,144 BIT
MEMORY ARRAY
I/O CONTROL
3101 drw 01
INPUT
DATA
CIRCUIT
WE
CS
V
CC
GND
A
14
I/O
0
I/O
7
CONTROL
CIRCUIT
OE
,
Lower Power
3.3V CMOS Fast SRAM
256K (32K x 8-Bit)
IDT71V256SA
2
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configurations
Absolute Maximum Ratings
(1)
Capacitance
(T
A
= +25C, f = 1.0MHz, SOJ package)
Truth Table
(1)
DIP/SOJ
Top View
Pin Descriptions
TSOP
Top View
3101 drw 02
5
6
7
8
9
10
11
12
A
12
1
2
3
4
24
23
22
21
20
19
18
17
SO28-5
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
V
CC
WE
A
8
A
9
A
11
OE
A
10
CS
I/O
7
16
15
I/O
2
GND
I/O
6
I/O
5
I/O
4
I/O
3
A
14
A
13
,
3101 drw 03
22
23
24
25
26
27
28
1
2
3
4
5
7
6
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
SO28-8
OE
A
11
A
9
A
8
A
13
A
14
A
7
A
6
A
5
A
4
A
3
A
12
WE
V
CC
,
Name
Description
A
0
- A
14
Addresses
I/O
0
- I/O
7
Data Input/Output
CS
Chip Select
WE
Write Enable
OE
Output Enable
GND
Ground
V
CC
Power
3101 tbl 01
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't Care
WE
CS
OE
I/O
Function
X
H
X
High-Z
Standby (I
SB
)
X
V
HC
X
High-Z
Standby (I
SB1
)
H
L
H
High-Z
Output Disable
H
L
L
D
OUT
Read
L
L
X
D
IN
Write
3101 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
Symbol
Rating
Com'l.
Unit
V
CC
Supply Voltage
Relative to GND
-0.5 to +4.6
V
V
TERM
(2)
Terminal Voltage
Relative to GND
-0.5 to V
CC
+0.5
V
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
3101 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
6
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
7
pF
3101 tbl 04
Grade
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V 0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V 0.3V
3101 tbl 05
6.42
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
3
Recommended DC Operating
Conditions
NOTE:
1. V
IL
(min.) = 2.0V for pulse width less than 5ns, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage - Inputs
2.0
____
5.0
V
V
IH
Input High Voltage - I/O
2.0
____
V
CC
+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
3101 tbl 06
DC Electrical Characteristics
(V
CC
= 3.3V 0.3V)
DC Electrical Characteristics
(1)
(V
CC
= 3.3V 0.3V, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V, Commercial and Industrial Temperture Ranges)
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
, only address inputs cycling at f
MAX
; f = 0 means that no inputs are cycling.
Symbol
Parameter
71V256SA10
71V256SA12
71V256SA15
71V256SA20
Unit
I
CC
Dynamic Operating Current
CS < V
IL
, Outputs
Open, V
CC
= Max., f = f
MAX
(2)
100
90
85
85
mA
I
SB
Standby Power Supply Current (TTL Level)
CS = V
IH
, V
CC
= Max., Outputs Open, f = f
MAX
(2)
20
20
20
20
mA
I
SB1
Full Standby Power Supply Current (CMOS Level)
CS > V
HC
, V
CC
= Max., Outputs Open, f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
2
2
2
2
mA
3101 tbl 07
Symbol
Parameter
Test Conditions
IDT71V256SA
Unit
Min.
Typ.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
GND to V
CC
___
___
2
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= GND to V
CC
___
___
2
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
___
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
___
___
V
3101 tbl 08
4
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 3.3V 0.3V, Commercial and Industrial Temperature Ranges)
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
*Includes scope and jig capacitances
AC Test Conditions
3101 drw 04
320
30pF*
350
DATA
OUT
3.3V
,
3101 drw 05
320
5pF*
350
DATA
OUT
3.3V
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
3101 tbl 09
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
Symbol
Parameter
71V256SA10
71V256SA12
71V256SA15
71V256SA20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
____
20
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
5
____
5
____
5
____
5
____
ns
t
CHZ
(1)
Chip Select to Output in High-Z
0
8
0
8
0
9
0
10
ns
t
OE
Outp ut Enable to Output Valid
____
6
____
6
____
7
____
8
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
3
____
3
____
0
____
0
____
ns
t
OHZ
(1)
Output Disable to Output in High-Z
2
6
2
6
0
7
0
8
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
Write Cycle
t
WC
Write Cycle Time
10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write
9
____
9
____
10
____
15
____
ns
t
CW
Chip Select to End-of-Write
9
____
9
____
10
____
15
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
9
____
9
____
10
____
15
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
t
DW
Data to Write Time Overlap
6
____
6
____
7
____
8
____
ns
t
DH
Data Hold from Write Time
0
____
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write
4
____
4
____
4
____
4
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
1
8
1
8
1
9
1
10
ns
3101 tbl 10
6.42
IDT71V256SA
3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1)
NOTES:
1.
WE is HIGH for Read cycle.
2. Transition is measured 200mV from steady state.
ADDRESS
CS
DATA
OUT
OE
3101 drw 06
t
RC
t
AA
t
OH
t
ACS
t
CLZ
t
CHZ
(2)
t
OE
t
OLZ
(2)
(2)
t
OHZ
(2)
DATA VALID
,
Timing Waveform of Read Cycle No. 2
(1,2,4)
Timing Waveform of Read Cycle No. 3
(1,3,4)
NOTES:
1.
WE is HIGH for Read cycle.
2. Device is continuously selected,
CS is LOW.
3. Address valid prior to or coincident with
CS transition LOW.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
DATA
OUT
CS
3101 drw 08
t
ACS
(5)
t
CLZ
(5)
CHZ
t
DATA VALID
,
ADDRESS
DATA
OUT
3101 drw 07
t
RC
t
AA
t
OH
t
OH
DATA VALID
PREVIOUS DATA VALID
,
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