Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1996

1996 Integrated Device Technology, Inc.

DSC-2661/9

5.04

FEATURES:

· First-In/First-Out Dual-Port memory
· 2048 x 9 organization (IDT7203)
· 4096 x 9 organization (IDT7204)
· 8192 x 9 organization (IDT7205)
· 16384 x 9 organization (IDT7206)
· High-speed: 12ns access time
· Low power consumption

-- Active: 770mW (max.)
-- Power-down: 44mW (max.)

· Asynchronous and simultaneous read and write
· Fully expandable in both word depth and width
· Pin and functionally compatible with IDT720X family
· Status Flags: Empty, Half-Full, Full
· Retransmit capability
· High-performance CMOS technology
· Military product compliant to MIL-STD-883, Class B
· Standard Military Drawing for #5962-88669 (IDT7203),

5962-89567 (IDT7203), and 5962-89568 (IDT7204) are
listed on this function

Industrial temperature range (-40

C to +85

C) is avail-

able, tested to military electrical specifications

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

IDT7203
IDT7204
IDT7205
IDT7206

DESCRIPTION:

The IDT7203/7204/7205/7206 are dual-port memory buff-

ers with internal pointers that load and empty data on a first-
in/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.

Data is toggled in and out of the device through the use of

the Write (

) and Read (

) pins.

The devices 9-bit width provides a bit for a control or parity

at the user's option. It also features a Retransmit (

) capa-

bility that allows the read pointer to be reset to its initial position
when

is pulsed LOW. A Half-Full Flag is available in the

single device and width expansion modes.

The IDT7203/7204/7205/7206 are fabricated using IDT's

high-speed CMOS technology. They are designed for appli-
cations requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,
8192 x 9 and 16384 x 9

WRITE

CONTROL

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

WRITE

POINTER

RAM ARRAY

2048 x 9
4096 x 9
8192 x 9

16384 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-
STATE
BUFFERS

DATA OUTPUTS

(D D

)

2661 drw 01

FUNCTIONAL BLOCK DIAGRAM

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

TERM

Terminal

0.5 to + 7.0

0.5 to +7.0

Voltage with
Respect to
GND

Operating

0 to +70

55 to +125

Temperature

BIAS

Temperature

55 to +125

65 to +135

Under Bias

STG

Storage

55 to + 125

65 to +155

Temperature

OUT

DC Output

Current

NOTE:

2661 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

RECOMMENDED DC OPERATING
CONDITIONS

Symbol

Parameter

Min.

Typ.

Max.

Unit

CCM

Military Supply

4.5

5.0

5.5

Voltage

CCC

Commercial Supply

4.5

5.0

5.5

Voltage

GND

Supply Voltage

(1)

Input High Voltage

2.0

Commercial

(1)

Input High Voltage

2.2

Military

(1)

Input Low Voltage

0.8

Commercial and
Military

NOTE:

2661 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

6
7

8
9

10
11

12
13

GND

1
2
3

28
27

26
25
24
23

22
21

XO/HF

Vcc

FL/RT

20
19

18
17
16
15

P28-1
P28-2
D28-1
D28-3

SO28-3

2661 drw 02a

DIP

TOP VIEW

NOTES:
1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/

7205.

2. The small outline package SO28-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.

PLCC/LCC

TOP VIEW

6
7

8
9

10
11
12
13

J32-1

L32-1

28
27

26
25

24
23
22
21

INDEX

Vcc

GND

2661 drw 02b

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206

(Commercial: V

= 5.0V

10%, T

= 0

C to +70

C; Military: V

= 5.0V

10%, T

= 55

C to +125

IDT7205/7206

Commercial

Military

= 15, 20, 25, 35, 50 ns

= 20, 30, 50 ns

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

(1)

Input Leakage Current (Any Input)

(2)

Output Leakage Current

Output Logic "1" Voltage I

= 2mA

2.4

Output Logic "0" Voltage I

= 8mA

0.4

CC1

(3)

Active Power Supply Current

120

(4)

150

(4)

CC2

(3)

Standby Current (

)

CC3

(L)

(3)

Power Down Current (All Input = V

- 0.2V)

DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204

(Commercial: V

= 5.0V

10%, T

= 0

C to +70

C; Military: V

= 5.0V

10%, T

= 55

C to +125

IDT7203/7204

Commercial

Military

(1)

= 12, 15, 20, 25, 35, 50 ns

= 20, 30, 40, 50, 65, 80, 120 ns

Symbol

Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

(2)

Input Leakage Current (Any Input)

(3)

Output Leakage Current

Output Logic "1" Voltage I

= 2mA

2.4

Output Logic "0" Voltage I

= 8mA

0.4

CC1

(4)

Active Power Supply Current

120

(5)

150

(5)

CC2

(4)

Standby Current (

)

CC3

(L)

(4)

Power Down Current (All Input = V

- 0.2V)

CC3

(S)

(4)

Power Down Current (All Input = V

- 0.2V)

NOTES:

2661 tbl 03

1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4

3. R

, 0.4

OUT

4. I

measurements are made with outputs open (only capacitive loading).

5. Tested at f = 20MHz.

NOTES:

2661 tbl 04

1. Measurements with 0.4

2. R

, 0.4

OUT

3. I

measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Commercial

Com'l & Mil.

Com'l

Military

Com'l

7203S/L12

7203S/L15

7203S/L20

7203S/L25

7203S/L30 7203S/L35

7204S/L12

7204S/L15

7204S/L20

7204S/L25

7204S/L30 7204S/L35

7205L15

7205L20

7205L25

7205L30

7205L35

7206L15

7206L20

7206L25

7206L30

7206L35

Symbol

Parameters

Min. Max. Min. Max. Min.

Max.

Min. Max. Min. Max. Min. Max. Unit

Shift Frequency

33.3

28.5

22.2 MHz

Read Cycle Time

Access Time

Read Recovery Time

RPW

Read Pulse Width

(2)

RLZ

Read LOW to Data Bus LOW

(3)

WLZ

Write HIGH to Data Bus Low-Z

(3, 4)

Data Valid from Read HIGH

RHZ

Read HIGH to Data Bus High-Z

(3)

Write Cycle Time

WPW

Write Pulse Width

(2)

Write Recovery Time

Data Set-up Time

Data Hold Time

RSC

Reset Cycle Time

Reset Pulse Width

(2)

RSS

Reset Set-up Time

(3)

RTR

Reset Recovery Time

RTC

Retransmit Cycle Time

Retransmit Pulse Width

(2)

RTS

Retransmit Set-up Time

(3)

RSR

Retransmit Recovery Time

EFL

Reset to

LOW

HFH

, t

FFH

Reset to

and

HIGH

RTF

Retransmit LOW to Flags Valid

REF

Read LOW to

LOW

RFF

Read HIGH to

HIGH

RPE

Read Pulse Width after

HIGH

WEF

Write HIGH to

HIGH

WFF

Write LOW to

LOW

WHF

Write LOW to

Flag LOW

RHF

Read HIGH to

Flag HIGH

WPF

Write Pulse Width after

HIGH

XOL

Read/Write LOW to

LOW

XOH

Read/Write HIGH to

HIGH

Pulse Width

(2)

XIR

Recovery Time

XIS

Set-up Time

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

= 5V

10%, T

= 0

C to +70

C; Military: V

= 5V

10%, T

= 55

C to +125

NOTES:

2661 tbl 05

1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Military

Com'l & Mil.

Military

(2)

7203S/L40

7203S/L50

7203S/L65

7203S/L80

7203S/L120

7204S/L40

7204S/L50

7204S/L65

7204S/L80

7204S/L120

7205L50
7206L50

Symbol

Parameters

Min.

Max.

Min.

Max. Min.

Max.

Unit

Shift Frequency

12.5

MHz

Read Cycle Time

100

140

Access Time

120

Read Recovery Time

RPW

Read Pulse Width

(3)

120

RLZ

Read LOW to Data Bus LOW

(4)

WLZ

Write HIGH to Data Bus Low-Z

(4, 5)

Data Valid from Read HIGH

RHZ

Read HIGH to Data Bus High-Z

(4)

Write Cycle Time

100

140

WPW

Write Pulse Width

(3)

120

Write Recovery Time

Data Set-up Time

Data Hold Time

RSC

Reset Cycle Time

100

140

Reset Pulse Width

(3)

120

RSS

Reset Set-up Time

(4)

120

RSR

Reset Recovery Time

RTC

Retransmit Cycle Time

100

140

Retransmit Pulse Width

(3)

120

RTS

Retransmit Set-up Time

(4)

120

RSR

Retransmit Recovery Time

EFL

Reset to

LOW

100

140

HFH

, t

FFH

Reset to

and

HIGH

100

140

RTF

Retransmit LOW to Flags Valid

100

140

REF

Read LOW to

Flag LOW

RFF

Read HIGH to

HIGH

RPE

Read Pulse Width after

HIGH

120

WEF

Write HIGH to

HIGH

WFF

Write LOW to

LOW

WHF

Write LOW to

LOW

100

140

RHF

Read HIGH to

HIGH

100

140

WPF

Write Pulse Width after

HIGH

120

XOL

Read/Write LOW to

LOW

120

XOH

Read/Write HIGH to

HIGH

120

Pulse Width

(3)

120

XIR

Recovery Time

XIS

Set-up Time

AC ELECTRICAL CHARACTERISTICS

(1)

(Continued)

(Commercial: V

= 5V

10%, T

= 0

C to +70

C; Military: V

= 5V

10%, T

= 55

C to +125

NOTES:

2661 tbl 06

1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

2661

bl 07

CAPACITANCE

(1)

= +25

C, f = 1.0 MHz)

Symbol

Parameter

Condition

Max.

Unit

(1)

Input Capacitance

= 0V

OUT

(1,2)

Output Capacitance

OUT

= 0V

NOTES:

2661

bl 08

1. This parameter is sampled and not 100% tested.
2. With output deselected.

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

5ns

1.5V
1.5V

See Figure 1

SIGNAL DESCRIPTIONS

Inputs:

DATA IN (D

) -- Data inputs for 9-bit wide data.

Controls:

RESET (

) -- Reset is accomplished whenever the Reset

(

) input is taken to a LOW state. During reset, both internal

read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take place.
Both the Read Enable (

) and Write Enable (

) inputs must

be in the HIGH state during the window shown in Figure 2
(i.e. t

RSS

before the rising edge of

) and should not

change until t

RSR

after the rising edge of

WRITE ENABLE (

) -- A write cycle is initiated on the falling

edge of this input if the Full Flag (

) is not set. Data set-up and

hold times must be adhered-to, with respect to the rising edge
of the Write Enable (

). Data is stored in the RAM array

sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (

) will be set to LOW,

and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (

) is reset by the

rising edge of the read operation.

To prevent data overflow, the Full Flag (

) will go LOW on

the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (

) will go HIGH after t

RFF

, allowing a new valid write

to begin. When the FIFO is full, the internal write pointer is
blocked from

, so external changes in

will not affect the FIFO

when it is full.

READ ENABLE (

) -- A read cycle is initiated on the falling

edge of the Read Enable (

), provided the Empty Flag (

) is not

set. The data is accessed on a First-In/First-Out basis, inde-
pendent of any ongoing write operations. After Read Enable (

)

goes HIGH, the Data Outputs (Q

through Q

) will return to a

high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (

)

will go LOW, allowing the "final" read cycle but inhibiting further
read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accom-
plished, the Empty Flag (

) will go HIGH after t

WEF

and a valid

Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from

so external changes will not affect the

FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

) -- This is a dual-

purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Single Device Mode is initiated by
grounding the Expansion In (

The IDT7203/7204/7205/7206 can be made to retransmit

data when the Retransmit Enable Control (

) input is pulsed

LOW. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. The status
of the Flags will change depending on the relative locations of
the read and write pointers. Read Enable (

) and Write Enable

(

) must be in the HIGH state during retransmit. This feature is

useful when less than 2048/4096/8192/16384 writes are per-
formed between resets. The retransmit feature is not compat-
ible with the Depth Expansion Mode.

EXPANSION IN (

) -- This input is a dual-purpose pin.

Expansion In (

) is grounded to indicate an operation in the

single device mode. Expansion In (

) is connected to Expan-

sion Out (

) of the previous device in the Depth Expansion or

Daisy-Chain Mode.

1.1K

30pF*

680

D.U.T.

OR EQUIVALENT CIRCUIT

2661 drw 03

Figure 1. Output Load

*Includes jig and scope capacitances.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Outputs:

FULL FLAG (

) -- The Full Flag (

) will go LOW, inhibiting

further write operations, when the device is full. If the read
pointer is not moved after Reset (

), the Full Flag (

) will go

LOW after 2048/4096/8192/16384 writes.

EMPTY FLAG (

) -- The Empty Flag (

) will go LOW,

inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (

) -- This is a

dual-purpose output. In the single device mode, when Expan-
sion In (

) is grounded, this output acts as an indication of a half-

full memory.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (

) will be set to LOW

Figure 2. Reset

Figure 3. Asynchronous Write and Read Operation

NOTE:
1.

and

= V

around the rising edge of

RSC

RSS

RSR

EFL

HFH

, t

FFH

2661 drw 04

DATA

WPW

VALID

RLZ

RHZ

RPW

VALID

DATA

OUT

VALID

DATA

OUT

DATA

VALID

2661 drw 05

and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The Half-Full Flag (

) is then reset by

the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (

) is con-

nected to Expansion Out (

) of the previous device. This

output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an

pulse

when the Write pointer reaches the last location of memory, and
an additional

pulse when the Read pointer reaches the last

location of memory.

DATA OUTPUTS (Q

-Q

) -- Q

-Q

are data outputs for 9-

bit wide data. These outputs are in a high-impedance condition
whenever Read (

) is in a HIGH state.

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e.

is monitored on the device

where

is used;

is monitored on the device where

used). For additional information, refer to Tech Note 8:

Oper-

ating FIFOs on Full and Empty Boundary Conditions

and

Tech Note 6:

Designing with FIFOs.

Single Device Mode

A single IDT7203/7204/7205/7206 may be used when the

application requirements are for 2048/4096/8192/16384 words
or less. The IDT7203/7204/7205/7206 is in a Single Device
Configuration when the Expansion In (

) control input is

grounded (see Figure 12).

Depth Expansion

The IDT7203/7204/7205/7206 can easily be adapted to

applications when the requirements are for greater than 2048/
4096/8192/16384 words. Figure 14 demonstrates Depth Ex-
pansion using three IDT7203/7204/7205/7206s. Any depth
can be attained by adding additional IDT7203/7204/7205/
7206s. The IDT7203/7204/7205/7206 operates in the Depth
Expansion mode when the following conditions are met:

1. The first device must be designated by grounding the First

Load (

) control input.

2. All other devices must have

in the HIGH state.

3. The Expansion Out (

) pin of each device must be tied to

the Expansion In (

) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(

) and Empty Flag (

). This requires the ORing of all

s and ORing of all

s (i.e. all must be set to generate the

correct composite

). See Figure 14.

5. The Retransmit (

) function and Half-Full Flag (

) are

not available in the Depth Expansion Mode.

For additional information, refer to Tech Note 9:

Cascading

FIFOs or FIFO Modules.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

corresponding input control signals of multiple devices. Sta-
tus flags (

and

) can be detected from any one device.

Figure 13 demonstrates an 18-bit word width by using two
IDT7203/7204/7205/7206s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206s (Figure 13).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7203/7204/7205/7206s as
shown in Figure 16. Both Depth Expansion and Width Expan-
sion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (t

WEF

+ t

) ns after the rising

edge of

, called the first write edge, and it remains on the bus

until the

line is raised from LOW-to-HIGH, after which the

bus would go into a three-state mode after t

RHZ

ns. The

line

would have a pulse showing temporary deassertion and then
would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The

line causes

the

to be deasserted but the

line being LOW causes it to

be asserted again in anticipation of a new data word. On the
rising edge of

, the new word is loaded in the FIFO. The

line must be toggled when

is not asserted to write new data

in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).

WRITE TO

FIRST PHYSICAL

LOCATION

XIS

READ FROM

FIRST PHYSICAL

LOCATION

XIS

XIR

2661 drw 11

Figure 11. Expansion In

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode

IDT

7203/
7204/
7205/

7206

WRITE (

)

FULL FLAG (

)

RESET (

)

DATA

(D)

READ (

)

EMPTY FLAG (

)

RETRANSMIT (

)

DATA

(Q)

OUT

IDT

7203/
7204/
7205/

7206

2661 drw 15

NOTE:
1. Flag detection is accomplished by monitoring the

and

signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode

WRITE (

)

DATA IN (D)

FULL FLAG (

)

RESET (

)

READ (

)

DATA OUT (Q)

EMPTY FLAG (

)

RETRANSMIT (

)

EXPANSION IN (

)

(

)

IDT

7203/
7204/
7205/

7206

(HALFFULL FLAG)

2661 drw 14

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES
TABLE I RESET AND RETRANSMIT

SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset

Location Zero

Retransmit

Location Zero

Unchanged

Read/Write

Increment

(1)

Increment

(1)

TABLE II RESET AND FIRST LOAD

DEPTH EXPANSION/COMPOUND EXPANSION MODE

Inputs

Internal Status

Outputs

Mode

Read Pointer

Write Pointer

Reset First Device

(1)

Location Zero

Reset all Other Devices

(1)

Location Zero

Read/Write

(1)

Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)

NOTES:

2661 tbl 10

is connected to

of previous device. See Figure 14.

= Reset Input,

FL/RT

= First Load/Retransmit,

= Empty Flag Output,

= Full Flag Output,

= Expansion Input,

= Half-Full Flag Output

NOTE:

2661 tbl 09

1. Pointer will Increment if flag is HIGH.

IDT

7203/
7204/
7205/

7206

FULL

EMPTY

IDT

7203/
7204/
7205/

7206

IDT

7203/
7204/
7205/

7206

2661 drw 16

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 17. Read Data Flow-Through Mode

NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.

Figure 15. Compound FIFO Expansion

· · ·

-D

(N-8)

-D

(N-8)

-D

· · ·

(N-8)

-Q

(N-8)

-Q

IDT7203/
IDT7204/
IDT7205/

IDT7206

DEPTH

EXPANSION

BLOCK

IDT7203/
IDT7204/
IDT7205/

IDT7206

DEPTH

EXPANSION

BLOCK

IDT7203/
IDT7204/
IDT7205/

IDT7206

DEPTH

EXPANSION

BLOCK

2661 drw 17

Figure 16. Bidirectional FIFO Operation

IDT

7201A

SYSTEM A

SYSTEM B

B 0-8

A 0-8

IDT

7203/
7204/
7205/

7206

A 0-8

IDT

7203/
7204/
7205/

7206

2661 drw 18

DATA

RPE

DATA

OUT

WLZ

WEF

REF

DATA VALID

OUT

2661 drw 19

5.04

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

DATA

OUT

WFF

RFF

WPF

DATA

VALID

DATA

OUT

VALID

2661 drw 20

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0

C to +70

Military (55

C to +125

Compliant to MIL-STD-883, Class B

P
TP
D
TD
J
L
SO

Plastic DIP
Plastic THINDIP
Ceramic DIP
Ceramic THINDIP (all except 7206)
Plastic Leaded Chip Carrier
Leadless Chip Carrier (Military only)
Small Outline IC (7204 only)

12
15
20
25
30
35
40
50
65
80
120

Commercial 7203/04 Only
Commercial Only

Commercial Only
Military Only
Commercial Only
Military 7203/04 Only

Military 7203/04DB Only

XXXX

DeviceType

7203
7204
7205
7206

2048 x 9 FIFO
4096 x 9 FIFO
8192 x 9 FIFO
16384 x 9 FIFO

IDT

S
L

Standard Power (7203/7204 only)
Low Power

Access Time (tA)
Speed in ns

2661 drw 21

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IDT7204L35P