Integrated Device Technology, Inc.

FEATURES

· High-density 1M/512K CMOS Dual-Port Static RAM

module

· Fast access times:

--Commercial 35, 40ns
--Military 40, 50ns

· Fully asynchronous read/write operation from either port
· Full on-chip hardware support of semaphore signaling

between ports

· Surface mounted LCC (leadless chip carriers) compo-

nents on a 64-pin sidebraze DIP (Dual In-line Package)

· Multiple Vcc and GND pins for maximum noise immunity
· Single 5V (

10%) power supply

· Input/outputs directly TTL-compatible

DESCRIPTION:

The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 high-

speed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two IDT FCT138 decoders or depopu-
lated using only four IDT7006s and two decoders.

This module provides two independent ports with separate

control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (

SEM

) "hand-

shake" signaling. The IDT7M1001/1003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users re-
sponsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.

The IDT7M1001/1003 module is packaged on a multilayer

co-fired ceramic 64-pin DIP (Dual In-line Package) with di-
mensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 35ns over the commercial temperature range are
available.

All inputs and outputs of the IDT7M1001/1003 are TTL-

compatible and operate from a single 5V supply. Fully asyn-
chronous circuitry is used, requiring no clocks or refreshing for
operation of the module.

All IDT military module semiconductor components are

manufacured in compliance with the latest revision of MIL-
STD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.

128K x 8
64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE

IDT7M1001
IDT7M1003

Left Port

Right Port

Description

A (016)

Address Inputs

I/O (07)

Data Inputs/Outputs

Read/Write Enables

Chip Select

Output Enable

SEM

Semaphore Control

Power

GND

Ground

2804 tbl 01

PIN CONFIGURATION

(1)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MARCH 1995

1995 Integrated Device Technology, Inc.

DSC-7066/5

7.5

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

PIN NAMES

DIP

TOP VIEW

11R

10R

12R

13R

14R

I/O

GND

10L

11L

12L

I/O

GND

13L

30
31
32

58
57
56
55
54
53
52

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

60
59

SEM

14L

15L

16L

GND

SEM

GND

15R

16R

2804 drw 01

NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected

to GND for proper operation of the module.

7.5

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM

2804 drw 02

74FCT138

CS CS

7006

CS CS

7006

L_CS

L_R/W

L_A15
L_A14

L_A0-13

L_OE

L_I/O0-7

L_SEM

R_I/O0-7

R_R/W
R_OE

R_A0-13

R_CS

R_A14
R_A15

R_SEM

74FCT138

CS CS

7006

CS CS

7006

7025

L_CS

L_A16

L_R/W

CS CS

7006

L_A15

L_A14

L_A0-13

L_OE

L_I/O0-7

L_SEM

R_I/O0-7

R_R/W
R_OE

R_A0-13

R_CS

R_A14

R_A15

R_A16

R_SEM

7M1001

7M1003

2804 drw 03

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.5

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Supply Voltage

Input High Voltage

2.2

6.0

Input Low Voltage

0.5

(1)

0.8

NOTE:
1. V

(min.) = 3.0V for pulse width less than 20ns.

CAPACITANCE

(1)

= +25

C, f = 1.0MHz)

Symbol

Parameter

Test Conditions

Max.

Unit

IN1

Input Capacitance

= 0V

(

SEM

)

IN2

Input Capacitance

= 0V

100

(Data, Address,

All Other Controls)

OUT

Output Capacitance

OUT

= 0V

100

(Data)

NOTE:
1. This parameter is guaranteed by design but not tested.

2804 tbl 03

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2804 tbl 05

DC ELECTRICAL CHARACTERISTICS

= 5V

10%, T

= 55

C to +125

C or 0

C to +70

Commercial

Military

Symbol

Parameter

Test Conditions

Min. Max.

(1)

Max.

(2)

Min. Max.

(1)

Max.

(2)

Unit

CC2

Dynamic Operating

= Max.,

SEM

940

660

1130

790

Current (Both Ports Active)

Outputs Open, f = f

MAX

CC1

Standby Supply

= Max., L_

or R_

750

470

905

565

Current (One Port Active)

Outputs Open, f = f

MAX

SB1

Standby Supply

= Max., L_

and R_

565

285

685

345

Current (TTL Levels)

Outputs Open, f = f

MAX

SEM

and R_

SEM

0.2V

SB2

Full Standby Supply

and R_

0.2V

125

245

125

Current (CMOS Levels)

> V

0.2V or < 0.2V

SEM

and R_

SEM

0.2V

NOTES:
1. IDT7M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

TERM

Terminal Voltage

0.5 to +7.0

with Respect to
GND

Operating

0 to +70

55 to +125

Temperature

BIAS

Temperature

55 to +125

65 to +135

Under Bias

STG

Storage

55 to +125

65 to +150

Temperature

OUT

DC Output

Current

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade

Temperature

GND

Military

C to +125

5.0V

10%

Commercial

C to +70

5.0V

10%

2804 tbl 04

2804 tbl 06

2804 tbl 02

7.5

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

=5.0V

10%, T

= 55

C to +125

C and 0

C to +70

IDT7M1001

IDT7M1003

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Input Leakage

= Max.

(Address, Data & Other Controls)

= GND to V

Input Leakage

= Max.

(

and

SEM

)

= GND to V

Output Leakage

= Max.

(Data)

IH,

OUT

= GND to V

Output Low Voltage

= Min. I

= 4mA

0.4

Output High Voltage

= Min. I

= 4mA

2.4

2804 tbl 07

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figures 1 and 2

2804 tbl 08

*Including scope and jig.

+5 V

30 pF*

DATA

OUT

480

255

2804 drw 04

+5 V

5 pF*

DATA

OUT

480

255

2804 drw 05

Figure 2. Output Load

(for t

CLZ

, t

CHZ

, t

OLZ

. t

OHZ

, t

WHZ

, t

)

Figure 1. Output Load

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.5

AC ELECTRICAL CHARACTERISTICS

= 5.0V

10%, T

= -55

C to +125

C and 0

C to +70

35

40

50

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

Address Access Time

ACS

(2)

Chip Select Access Time

Output Enable Access Time

Output Hold From Address Change

CLZ

(1)

Chip Select to Output in Low-Z

CHZ

(1)

Chip Deselect to Output in High-Z

OLZ

(1)

Output Enable to Output in Low-Z

OHZ

(1)

Output Disable to Output in High-Z

(1)

Chip Select to Power-Up Time

(1)

Chip Disable to Power-Down Time

SOP

SEM

Flag Update Pulse (

SEM

)

Write Cycle

Write Cycle Time

(2)

Chip Select to End-of-Write

Address Valid to End-of-Write

AS1

(3)

Address Set-up to Write Pulse Time

AS2

Address Set-up to

Time

Write Pulse Width

(4)

Write Recovery Time

Data Valid to End-of-Write

(4)

Data Hold Time

OHZ

(1)

Output Disable to Output in High-Z

WHZ

(1)

Write Enable to Output in High-Z

(1, 4)

Output Active from End-of-Write

SWRD

SEM

Flag Write to Read Time

SPS

SEM

Flag Contention Window

Port-to-Port Delay Timing

WDD

(5)

Write Pulse to Data Delay

DDD

(5)

Write Data Valid to Read Data Valid

NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM

and

SEM

. To access semaphore,

and

SEM

3. t

AS1

= 0 if R/

is asserted LOW simultaneously with or after the

LOW transition.

4. For

controlled write cycles, t

= 5ns, t

= 5ns.

5. Port-to-Port delay through the RAM cells from the writing port to the reading port.

2804 tbl 09

7.5

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)

(1,2,4)

2804 drw 06

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)

(1,3,5)

ACS

CHZ

(6)

OHZ

(6)

50%

(6)

DATA

OUT

CURRENT

OLZ

(6)

DATA VALID

CLZ

(6)

NOTES:
1. R/

is HIGH for Read Cycles

2. Device is continuously enabled.

= LOW. This waveform cannot be used for semaphore reads.

3. Addresses valid prior to or coincident with

transition LOW.

= LOW.

5. To access RAM,

= LOW,

SEM

= H. To access semaphore,

= HIGH and

SEM

= LOW.

6. This parameter is guaranteed by design but not tested.

2804 drw 07

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.5

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/

CONTROLLED TIMING)

(1,3,5,8)

ADDRESS

OHZ (9)

R/W

WP(2)

WHZ(9)

DATA

OUT

DATA

(4)

OW (9)

WR (7)

DATA VALID

(6)

2804 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CONTROLLED TIMING)

(1,3,5,8)

NOTES:
1. R/

must be HIGH during all address transitions.

2. A write occurs during the overlap (t

) of a LOW

and a LOW

and a LOW R/

for memory array writing cycle.

3. t

is measured from the earlier of

or R/

(or

SEM

or R/

) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the

SEM

LOW transition occurs simultaneously with or after the R/

LOW transition, the outputs remain in the high-impedance state.

6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If

is LOW during a R/

controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off and data

to be placed on the bus for the required t

. If

is HIGH during an R/

controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified t

9. This parameter is guaranteed by design but not tested.

NOTES:
1. R/

is HIGH for Read Cycles

2. Device is continuously enabled.

= LOW.

= LOW. This waveform cannot be used for semaphore reads.

3. Addresses valid prior to or coincident with

transition low.

= LOW.

5. To access RAM,

= LOW,

SEM

= H. To access semaphore,

= HIGH and

SEM

= LOW.

6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If

is LOW during a R/

controlled write cycle, the write pulse width must be larger of t

or (t

+ t

) to allow the I/O drivers to turn off and data to

be placed on the bus for the required tDW. If

is HIGH during a R/

controlled write cycle, this requirement does not apply and the write pulse width

be as short as the specified t

9. This parameter is guaranteed by design but not tested.

ADDRESS

DATA

DATA VALID

R/W

WP (2)

WR (7)

AS (6)

2804 drw 09

7.5

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)

(1)

NOTE:
1.

= HIGH for the duration of the above timing (both write and read cycle).

2804 drw 10

2804 drw 11

NOTES:
1. D

= D

= LOW, L_

= R_

= HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.

2. "A" may be either left or right port. "B" is the opposite port from "A".
3. This parameter is measured from R/

SEM

going HIGH to R/

SEM

going HIGH.

4. If t

SPS

is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

ACS

SOP

SWRD

SOP

VALID ADDRESS

DATA

VALID

DATA

OUT

VALID

READ CYCLE

WRITE CYCLE

- A

SEM

DATA

R/W

TIMING WAVEFORM OF SEMAPHORE CONTENTION

(1,3,4)

MATCH

SPS

0A -

R/W

SEM

0B -

R/W

SEM

SIDE

(2)

"A"

SIDE

(2)

"B"

IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.5

NOTE:
1. L_

= R_

= LOW.

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY

(1)

SEMAPHORE OPERATION

For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.

ADDR

R/W

DATA

IN R

VALID

MATCH

VALID

MATCH

WDD

DDD

ADDR

DATA

OUT L

READ CYCLE

RIGHT PORT

WRITE CYCLE LEFT PORT

2804 drw 12

TRUTH TABLES

TABLE I: NON-CONTENTION READ/WRITE CONTROL

(1)

Inputs

(1)

Outputs

SEM

I/O

- I/O

Mode

High-Z

Deselected: Power Down

DATA

Write to Both Bytes

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

NOTE:
1. A

-- A

12R

2804 tbl 10

TABLE II: SEMAPHORE READ/WRITE CONTROL

(1)

Inputs Outputs

SEM

I/O

- I/O

Mode

DATA

OUT

Read Data in Semaphore Flag

DATA

Write D

IN0

into Semaphore Flag

Not Allowed

NOTE:
1. A

-- A

12R

2804 tbl 11

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