COMMERCIAL TEMPERATURE RANGE
DECEMBER 1995
1996 Integrated Device Technology, Inc.
DSC-2675/6
7.11
1
The IDT logo is a registered trademark of Integrated Device Technology Inc.
FEATURES:
High-density 4-megabit (512K x 8) Static RAM module
Fast access time: 25ns (max.)
Surface mounted plastic packages on a 32-pin, 600 mil
FR-4 DIP substrate
Single 5V (
10%) power supply
Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MB4048 is a 4-megabit (512K x 8) Static RAM
module constructed on a multilayer epoxy laminate (FR-4)
substrate using four 1 megabit SRAMs and a decoder. The
IDT7MB4048 is available with access times as fast as 25ns.
The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting
in the JEDEC footprint in a package 1.6 inches long and 0.6
inches wide.
All inputs and outputs of the IDT7MB4048 are TTL-com-
patible and operate from a single 5V supply. Fully asynchro-
nous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
512K x 8
CMOS STATIC RAM MODULE
IDT7MB4048
FUNCTIONAL BLOCK DIAGRAM
2675 drw 02
19
512K x 8
RAM
ADDRESS
CS
WE
OE
I/O
8
PIN CONFIGURATION
PIN NAMES
I/O
0-7
Data Inputs/Outputs
A
0-18
Addresses
CS
Chip Select
WE
Write Enable
OE
Output Enable
V
CC
Power
GND
Ground
2675 tbl 01
DIP
TOP VIEW
2675 drw 01
5
6
7
8
9
10
11
12
GND
A
18
A
16
A
14
1
2
3
4
32
31
30
29
28
27
26
25
Vcc
24
23
22
21
A
15
A
12
A
7
A
6
A
5
A
4
A
17
A
13
A
8
A
9
A
11
A
3
A
2
A
1
A
0
13
14
15
16
I/O
0
I/O
1
I/O
2
I/O
6
I/O
5
I/O
4
20
19
17
18
OE
A
10
CS
I/O
7
I/O
3
WE
Integrated Device Technology, Inc.
7.11
2
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
Mode
CS
CS
CS
CS
CS
OE
OE
OE
OE
OE
WE
WE
WE
WE
WE
Output
Power
Standby
H
X
X
High-Z
Standby
Read
L
L
H
D
OUT
Active
Read
L
H
H
High-Z
Active
Write
L
X
L
D
IN
Active
2675 tbl 02
CAPACITANCE
(1)
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
Conditions
Typ.
Unit
C
IN
Input Capacitance
V
IN
= 0V
35
pF
C
IN(C)
Input Capacitance (
CS
)
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
35
pF
NOTE:
2675 tbl 03
1. This parameter is guaranteed by design, but not tested.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Unit
V
TERM
Terminal Voltage
0.5 to +7.0
V
with Respect
to GND
T
A
Operating
0 to +70
C
Temperature
T
BIAS
Temperature 10 to +85
C
Under Bias
T
STG
Storage
55 to +125
C
Temperature
I
OUT
DC Output Current
50
mA
NOTE:
2675 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5
5.5
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
2.2
--
6
V
V
IL
Input Low Voltage
0.5
(1)
--
0.8
V
NOTE:
2675 tbl 04
1. V
IL
= 2.0V for pulse width less than 10ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade
Temperature
GND
V
CC
Commercial
0
C to +70
C
0V
5V
10%
2675 tbl 06
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10%, T
A
= 0
C to +70
C)
7MB4048SxxP
Symbol
Parameter
Test Conditions
Min.
Max. Unit
|I
LI
|
Input Leakage
V
CC
= Max., V
IN
= GND to V
CC
--
8
A
|I
LO
|
Output Leakage
V
CC
= Max.,
CS
= V
IH
,
--
8
A
V
OUT
= GND to V
CC
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 8mA
--
0.4
V
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 1mA
2.4
--
V
I
CC
Dynamic Operating Current
V
CC
= Max.,
CS
V
IL
; f = f
MAX
,
--
480
mA
Outputs Open
I
SB
Standby Supply Current
CS
V
IH
, V
CC
= Max., f = f
MAX
,
--
250
mA
(TTL Levels)
Outputs Open
I
SB1
Full Standby Supply Current
CS
V
CC
- 0.2V, V
IN
V
CC
- 0.2V
--
170
mA
(CMOS Levels)
or
0.2
2675 tbl 07
7.11
3
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10%, T
A
= 0
C to +70
C)
7MB4048
25
30
35
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max. Unit
Read Cycle
t
RC
Read Cycle Time
25
--
30
--
35
--
ns
t
AA
Address Access Time
--
25
--
30
--
35
ns
t
ACS
Chip Select Access Time
--
25
--
30
--
35
ns
t
OE
Output Enable to Output Valid
--
12
--
15
--
15
ns
t
OHZ
(1)
Output Disable to Output in High-Z
--
12
--
12
--
15
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
--
0
--
0
--
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
5
--
5
--
5
--
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
--
14
--
16
--
20
ns
t
OH
Output Hold from Address Change
3
--
3
--
3
--
ns
t
PU
(1)
Chip Select to Power-Up Time
0
--
0
--
0
--
ns
t
PD
(1)
Chip Deselect to Power-Down Time
--
25
--
30
--
35
ns
Write Cycle
t
WC
Write Cycle Time
25
--
30
--
35
--
ns
t
WP
Write Pulse Width
17
--
20
--
25
--
ns
t
AS
(2)
Address Set-up Time
3
--
0
--
0
--
ns
t
AW
Address Valid to End-of-Write
20
--
25
--
30
--
ns
t
CW
Chip Select to End-of-Write
20
--
25
--
30
--
ns
t
DW
Data to Write Time Overlap
15
--
17
--
20
--
ns
t
DH
(2)
Data Hold Time
0
--
0
--
0
--
ns
t
WR
(2)
Write Recovery Time
0
--
0
--
0
--
ns
t
WHZ
(1)
Write Enable to Output in High-Z
--
15
--
15
--
15
ns
t
OW
(1)
Output Active from End-of-Write
2
--
5
--
5
--
ns
NOTES
2675 tbl 10
1. This parameter is guaranteed by design, but not tested.
2. t
AS
=0ns for
CS
controlled write cycles
.
t
DH
, t
WR
= 3ns for
CS
controlled write cycles.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 & 2
2675 tbl 09
+5 V
30 pF*
DATA
OUT
480
255
2675 drw 04
Figure 1. Output Load
Figure 2. Output Load
(for t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, t
OW
and
t
CLZ
)
+5 V
5 pF*
DATA
OUT
480
255
2675 drw 05
7.11
4
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
AA
ADDRESS
2675 drw 06
t
RC
t
OE
t
OLZ
t
ACS
t
CLZ
(5)
t
CHZ
(5)
t
OHZ
(5)
t
OH
OE
CS
DATA
OUT
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
2675 drw 08
t
ACS
t
CLZ
t
CHZ
DATA
OUT
CS
(5)
(5)
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
= V
IL
.
5. Transition is measured
200mV from steady state. This parameter is guaranteed by design, but not tested.
2675 drw 07
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
7.11
5
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CS
CS
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
CS
2675 drw 09
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WHZ
t
OHZ
(6)
(6)
(4)
(4)
(7)
(6)
t
OW
OE
(6)
t
OHZ
DATA VALID
CS
2675 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
DATA VALID
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
7.11
6
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
SIDE VIEW
0.590
0.620
0.007
0.013
0.035
0.065
0.015
0.025
0.100
TYP.
0.120
0.175
0.360
MAX.
BOTTOM VIEW
0.600
0.620
1.590
1.610
TOP VIEW
Pin 1
ORDERING INFORMATION
(1)
2675 drw 11
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
Commercial (0
C to +70
C)
P
SOJs mounted on an FR-4 DIP
25
30
35
XXXX
Device
Type
IDT
Speed in Nanoseconds
S
Standard Power
7MB4048 512K x 8 Static RAM Module (FR-4 substrate)
2675 drw 12
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