1999 Integrated Device Technology, Inc.
DECEMBER 1999
DSC-2682/6
1
Features
x
x
x
x
x
High-density 2MB Static RAM module
x
x
x
x
x
Low profile 64-pin ZIP (Zig-zag In-line vertical Package) or 64-
pin SIMM (Single In-line Memory Module)
x
x
x
x
x
Ultra fast access time: 12ns (max.)
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x
x
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x
Surface mounted plastic components on an epoxy laminate
(FR-4) substrate
x
x
x
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x
Single 5V (10%) power supply
x
x
x
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x
Multiple GND pins and decoupling capacitors for maximum
noise immunity
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x
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x
Inputs/outputs directly TTL-compatible
Description
The IDT7MP4036 is a 64K x 32 Static RAM module constructed on
an epoxy laminate (FR-4) substrate using eight 64K x 4 Static RAMs in
plastic SOJ packages. Availability of four chip select lines (one for each
group of two RAMs) provides byte access. Extremely fast speeds can be
achieved due to the use of 256K Static RAMs fabricated in IDT's high-
performance, high-reliability CMOS technology. The IDT7MP4036 is
available with access time as fast as 12ns with minimal power consumption.
The IDT7MP4036 is packaged in a 64-pin FR-4 ZIP (Zig-zag In-line
vertical Package)or a 64-pin SIMM (Single In-line Memory Module). The
ZIP configuration allows 64 pins to be placed on a package 3.65 inches
long and 0.35 inches wide. At only 0.50 inches high, this low-profile
package is ideal for systems with minimum board spacing, while the SIMM
configuration allows use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4036 are TTL-compatible and
operate from a single 5V supply. Full asynchronous circuitry requires no
clocks or refresh for operation and provides equal access and cycle times
for ease of use.
Two identification pins (PD
0
and PD
1
) are provided for applications in
which different density versions of the module are used. In this way, the
target system can read the respective levels of PD
0
and PD
1
to determine
a 64K depth.
Pin Configuration
(1)
NOTE:
1. Pins 2 and 3 (PD
0
and PD
1
) are read by the user to determine the density of
the module. If PD
0
reads Open and PD
1
reads GND, then the module had a
64K depth.
ZIP, SIMM
Top View
Pin Names
2682 drw 02
PD
0
31
29
9
11
13
15
17
19
21
23
25
1
3
5
7
27
33
63
61
41
43
45
47
49
51
53
55
57
35
37
39
59
PD
1
OPEN
GND
32
30
28
8
10
12
14
16
18
20
22
24
2
4
6
26
34
64
62
42
44
46
48
50
52
54
56
58
36
38
40
60
GND
CS
3
NC
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
WE
I/O
7
CS
1
PD
0
A
14
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
PD
1
GND
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
CS
2
A
15
,
64K x 32
CMOS Static RAM Module
IDT7MP4036
I/O
0-31
Data Inputs/Outputs
A
0-15
Addresses
CS
1-4
Chip Selects
WE
Write Enable
OE
Output Enable
PD
0-1
Depth Identification
V
CC
Power
GND
Ground
NC
No Connect
2682 tbl 01
2
IDT7MP4036
64K x 32 CMOS Static RAM Module Commercial Temperature Ranges
Truth Table
Capacitance
(T
A
= +25C, f = 1.0MHz)
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings
(1)
Recommended DC Operating
Conditions
Functional Block Diagram
OE
WE
2682 drw 01
8
16
64K x 32
RAM
8
8
8
2
CS
1
CS
2
CS
3
CS
4
ADDRESS
I/O
0-31
PD
0-1
,
Mode
CS
OE
WE
Output
Power
Standby
H
X
X
High-Z
Standby
Read
L
L
H
D
OUT
Active
Read
L
H
H
High-Z
Active
Write
L
X
L
D
IN
Active
2682 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. I/O pins must not exceed V
CC
+0.5V.
Symbol
Rating
Commercial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to GND
-0.5 to +7.0
V
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature
Under Bias
-10 to +85
C
T
STG
Storage Temperature
-55 to +125
C
I
OUT
DC Output Current
50
mA
2682 tbl 06
NOTE:
1. This parameter is guaranteed by design but not tested.
Symbol
Parameter
Conditions
Typ.
Unit
C
IN(D)
Input Capacitance (Data)
V
IN
= 0V
15
pF
C
IN(A)
Input Capacitance
(Address & Control)
V
IN
= 0V
70
pF
C
OUT
Output Capacitance
V
OUT
= 0V
15
pF
2682 tbl 02
NOTES:
1. V
IL
(min) = 1.5V for pulse width less than 10ns.
2. I/O pins must not exceed V
CC
+0.5V.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
(2)
Input High Voltage
2.2
____
6.0
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2682 tbl 03
Grade
Ambient
Temperature
GND
VCC
Commercial
0C to +70C
0V
5V 10%
2682 tbl 04
6.42
IDT7MP4036
64K x 32 CMOS Static RAM Module Commercial Temperature Ranges
3
AC Test Conditions
Figure 1. Output Load
Figure 2. Output Load
(for t
OLZ
, t
OHZ
, t
CHZ
, t
CLZ
, t
WHZ
, t
OW
)
*incluces scope and jig.
DC Electrical Characteristics
(V
CC
= 5.0V 10%, T
A
= 0C to +70C)
2682 drw 03
480
30pF*
255
+5V
DATA
OUT
,
480
5pF
255
+5V
DATA
OUT
*
2682 drw 04
,
Symbol
Parameter
Test Condition
Min.
Max.
Unit
II
LI
I
Input Leakage Current
(Address and Control)
V
CC
= Max., V
IN
= GND to V
CC
____
80
A
II
LI
I
Input Leakage Current
(Data)
V
CC
= Max., V
IN
= GND to V
CC
____
10
A
II
LO
I
Output Leakage Current
V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
____
10
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
____
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
____
V
I
CC
Dynamic Operating
Current
V
CC
= Max.,
CS = V
IL
,
f = f
MAX
, Outputs Open
____
1280
mA
I
SB
Standby Supply
Current
V
CC
= Max.,
CS > V
IH
,
f = f
MAX
, Outputs Open
____
360
mA
I
SB1
Full Standby
Supply Current
CS > V
CC
- 0.2V, f = 0
V
IN
> V
CC
- 0.2V or < 0.2V
____
240
mA
2682 tbl 07
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2682 tbl 08
4
IDT7MP4036
64K x 32 CMOS Static RAM Module Commercial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5V 10%, T
A
= 0C to +70C)
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
7MP4036SxxZ, 7MP4036SxxM
-12
(2)
-13
-15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
12
____
13
____
15
____
ns
t
AA
Address Access Time
____
12
____
13
____
15
ns
t
ACS
Chip Select Access Time
____
12
____
13
____
15
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
2
____
2
____
2
____
ns
t
OE
Output Enable to Output Valid
____
7
____
8
____
9
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
7
____
7
____
8
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
7
____
7
____
8
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power-Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power-Down Time
____
12
____
13
____
15
ns
Write Cycle
t
WC
Write Cycle Time
12
____
13
____
15
____
ns
t
CW
Chip Select to End-of-Write
10
____
11
____
12
____
ns
t
AW
Address Valid to End-of-Write
11
____
12
____
13
____
ns
t
AS
Address Set-up Time
1
____
1
____
1
____
ns
t
WP
Write Pulse Width
10
____
11
____
12
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
7
____
7
____
8
ns
t
DW
Data to Write Time Overlap
7
____
7
____
8
____
ns
t
DH
Data Hold Time
1
____
1
____
1
____
ns
t
OW
(1)
Output Active from End-of-Write
2
____
2
____
1
____
ns
2682 tbl 09
6.42
IDT7MP4036
64K x 32 CMOS Static RAM Module Commercial Temperature Ranges
5
AC Electrical Characteristics
(V
CC
= 5V 10%, T
A
= 0C to +70C)
NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.
7MP4036SxxZ, 7MP4036SxxM
-20
-25
-35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
ns
t
ACS
Chip Select Access Time
____
20
____
25
____
35
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
3
____
3
____
3
____
ns
t
OE
Output Enable to Output Valid
____
10
____
12
____
25
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
10
____
15
____
22
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
10
____
15
____
22
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power-Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power-Down Time
____
20
____
25
____
35
ns
Write Cycle
t
WC
Write Cycle Time
20
____
25
____
35
____
ns
t
CW
Chip Select to End-of-Write
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write
15
____
20
____
30
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
15
____
20
____
30
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
12
____
15
____
18
ns
t
DW
Data to Write Time Overlap
12
____
15
____
20
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write
0
____
0
____
0
____
ns
2682 tbl 10
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