1999 Integrated Device Technology, Inc.
DECEMBER 1999
DSC-2703/5
1
2703 drw 01
PD
0
31
29
9
11
13
15
17
19
21
23
25
1
3
5
7
27
33
63
61
41
43
45
47
49
51
53
55
57
35
37
39
59
PD
1
- GND
- GND
32
30
28
8
10
12
14
16
18
20
22
24
2
4
6
26
34
64
62
42
44
46
48
50
52
54
56
58
36
38
40
60
GND
CS
3
A
16
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
WE
I/O
7
CS
1
PD
0
A
14
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
PD
1
GND
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
CS
2
A
15
,
Features
x
x
x
x
x
High density 1 megabyte static RAM module
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)
x
x
x
x
x
Low profile 64 pin ZIP (Zig-zag In-line vertical Package) or
64 pin SIMM (Single In-line Memory Module) for
IDT7MP4045 and 72 pin SIMM (Single In-line Memory
Module) for IDT7MP4145
x
x
x
x
x
Very fast access time: 15ns (max.)
x
x
x
x
x
Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
x
x
x
x
x
Single 5V (10%) power supply
x
x
x
x
x
Multiple GND pins and decoupling capacitors for maximum
noise immunity
x
x
x
x
x
Inputs/outputs directly TTL-compatible
NOTE:
1. Pins 2 and 3 (PD
0
and PD
1
) are read by the user to determine the density of
the module. If PD
0
reads GND and PD
1
reads GND, then the module has a 256K
depth.
Description
The IDT7MP4045/4145 is a 256K x 32 static RAM module constructed
on an epoxy laminate (FR-4) substrate using 8 256K x 4 static RAMs in
plastic SOJ packages. Availability of four chip select lines (one for each
group of two RAMs) provides byte access. The IDT7MP4045 is available
with access time as fast as 10ns with minimal power consumption.
The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig-zag In-line
vertical Package)or a 64 pin SIMM (Single In-line Memory Module) where
as the 7MP4145 is packaged in a 72 pin SIMM (Single In-line Memory
Module). The 4045 ZIP configuration allows 64 pins to be placed on a
package 3.65 inches long and 0.365 inches wide. The 7MP4045 ZIP is
only 0.585 inches high, this low profile package is ideal for systems with
minimum board spacing while the SIMM configuration allows use of edge
mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4045/4145 are TTL-compatible
and operate from a single 5V supply. Full asynchronous circuitry requires
no clocks or refresh for operation and provides equal access and cycle
times for ease of use.
Identification pins are provided for applications in which different
density versions of the module are used. In this way, the target system can
read the respective levels of PD
pins
to determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel covered
by 30 micro-inches minimum of selective gold.
Pin Configuration 7MP4045
(1)
ZIP, SIMM
Top View
Functional Block Diagram
OE
WE
2703 drw 02
8
18
256K x 32
RAM
8
8
8
2
CS
1
CS
2
CS
3
CS
4
ADDRESS
I/O
0-31
PD
,
256K x 32
CMOS Static RAM Module
IDT7MP4045
IDT7MP4145
2
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
A
17
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
NC
NC
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
PD
0
- GND
PD
1
- GND
PD
2
- OPEN
PD
3
- OPEN
2703 drw 03
,
Recommended Operating
Temperature and Supply Voltage
Capacitance
(T
A
= +25C, f = 1.0MHz)
Recommended DC Operating
Conditions
Pin Configuration 7MP4145
(1)
SIMM
Top View
NOTE:
1. Pins 3,4,6,and 7 (PD
0
-
3
) are read by the user to determine the density of the
module. If PD
0
, PD
1
read GND and PD
2,
PD
3
read OPEN, then the module has
a 256K depth.
Pin Names
I/O
0-31
Data Inputs/Outputs
A
0-17
Addresses
CS
1-4
Chip Selects
WE
Write Enable
OE
Output Enable
PD
0-1
Depth Identification
V
CC
Power
GND
Ground
NC
No Connect
2703 tbl 01
NOTE:
1. This parameter is guaranteed by design but not tested.
Symbol
Parameter
Conditions
Typ.
Unit
C
IN(C)
Input Capacitance (
CS)
V
IN
= 0V
20
pF
C
IN(A)
Input Capacitance
(Address & Control)
V
IN
= 0V
70
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
2703 tbl 02
NOTE:
1. V
IL
(min) = 1.5V for pulse width less than 10ns.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2703 tbl 03
Grade
Ambient
Temperature
GND
VCC
Commercial
0C to +70C
0V
5V 10%
2703 tbl 04
6.42
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
3
DC Electrical Characteristics
(V
CC
= 5.0V 10%, T
A
= 0C to +70C)
Truth Table
Absolute Maximum Ratings
(1)
Mode
CS
OE
WE
Output
Power
Standby
H
X
X
High-Z
Standby
Read
L
L
H
D
OUT
Active
Read
L
H
H
High-Z
Active
Write
L
X
L
D
IN
Active
2703 tbl 05
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Rating
Commercial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to GND
-0.5 to +7.0
V
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature
Under Bias
-10 to +85
C
T
STG
Storage Temperature
-55 to +125
C
I
OUT
DC Output Current
50
mA
2703 tbl 06
Symbol
Parameter
Test Condition
Min.
Max.
Unit
II
LI
I
Input Leakage Current
(Address and Control)
V
CC
= Max., V
IN
= GND to V
CC
____
80
A
II
LI
I
Input Leakage Current
(Data)
V
CC
= Max., V
IN
= GND to V
CC
____
10
A
II
LO
I
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= 0V to V
CC
____
10
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
____
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
____
V
I
CC
Dynamic Operating
Current
V
CC
= Max.,
CS = V
IL
,
f = f
MAX
, Outputs Open
____
1360
mA
I
SB
Standby Supply
Current
V
CC
= Max.,
CS > V
IH
,
f = f
MAX
, Outputs Open
____
480
mA
I
SB1
Full Standby
Supply Current
CS > V
CC
- 0.2V, f = 0
V
IN
> V
CC
- 0.2V or < 0.2V
____
120
mA
2703 tbl 07
4
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
1
2
3
4
5
6
7
8
20
40
60
80
100
120 140
160 180
200
T
AA
(Typical, ns)
CAPACITANCE (pF)
2703 drw 07
Figure 3. Alternate Output Load
Figure 4. Alternate Lumped Capacitive Load,
Typical Derating
2703 drw 06
DATA
OUT
50
1.5V
Zo = 50
,
+5 V
480
30 pF*
DATA
OUT
255
2703 drw 04
,
+5 V
480
5 pF*
DATA
OUT
255
2703 drw 05
,
Figure 1. Output Load
*Includes scope and jig.
Figure 2. Output Load
(for t
OLZ
,t
OHZ
, t
CHZ
, t
CLZ
, t
WHZ
, t
OW
)
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2703 tbl 08
6.42
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
5
AC Electrical Characteristics
(V
CC
= 5V 10%, T
A
= 0C to +70C)
NOTE:
1. This parameter is guaranteed by design but not tested.
7MP4045SxxZ, 7MP4045/4145SxxM
-15
-20
-25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25
ns
t
ACS
Chip Select Access Time
____
15
____
20
____
25
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
3
____
5
____
5
____
ns
t
OE
Output Enable to Output Valid
____
8
____
10
____
12
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
____
0
____
0
____
ns
t
CHZ
(1)
Chip Deselect to Output in High-Z
____
8
____
10
____
12
ns
t
OHZ
(1)
Output Disable to Output in High-Z
____
8
____
10
____
10
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power-Up Time
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power-Down Time
____
15
____
20
____
25
ns
Write Cycle
t
WC
Write Cycle Time
15
____
20
____
25
____
ns
t
CW
Chip Select to End-of-Write
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
12
____
15
____
20
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z
____
8
____
13
____
15
ns
t
DW
Data to Write Time Overlap
10
____
12
____
15
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write
0
____
0
____
0
____
ns
2703 tbl 09
6
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1,2,4)
Timing Waveform of Read Cycle No. 3
(1,3,4)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected.
CS = V
IL
.
3. Address valid prior to or coincident with
CS transition LOW.
4.
OE = V
IL
.
5. Transition is measured 200mV from steady state. This parameter is guaranteed by design, but not tested.
2703 drw 10
t
ACS
t
CHZ
DATA
OUT
CS
(5)
t
CLZ
(5)
,
2703 drw 09
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALID
PREVIOUS DATA VALID
,
OE
t
AA
t
OH
ADDRESS
t
RC
CS
DATAOUT
t
ACS
t
OHZ
(5)
t
CHZ
(5)
t
OLZ (5)
2703 drw 08
t
CLZ
(5)
t
OE
,
6.42
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
7
Timing Waveform of Write Cycle No. 1 (WE Controlled)
(1,2,3,7)
Timing Waveform of Wdite Cycle No. 2 (CS Controlled)
(1,2,3,5)
NOTES:
1.
WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS and a LOW WE.
3. t
WR
is measured from the earlier of
CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed
on the bus for the required t
DW
. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP
.
CS
2703 drw 12
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
DATA VALID
,
CS
2703 drw 11
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WHZ
(6)
(4)
(4)
(7)
t
OW
OE
(6)
t
OHZ
t
OHZ
(6)
DATA VALID
(6)
,
8
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
0.365
MAX.
0.050
TYP.
FRONT VIEW
BACK VIEW
SIDE VIEW
PIN 1
PIN 1
0.630
MAX.
0.240
0.260
0.390
0.410
0.250
TYP.
3.580
3.588
3.840
3.860
0.045
0.055
COMPONENT AREA
COMPONENT AREA
2703 drw 14
,
Package Dimensions
7MP4045 ZIP VERSION
7MP4045 SIMM VERSION
0.585
MAX.
3.640
3.660
FRONT VIEW
BACK VIEW
0.015
0.025
0.100
TYP.
0.125
0.190
0.250
TYP.
0.050
TYP.
0.100
TYP.
0.365
MAX.
PIN 1
SIDE VIEW
PIN 1
COMPONENT AREA
COMPONENT AREA
2703 drw 13
,
6.42
IDT7MP4046 / 7MP4145
256k x 32 CMOS Static RAM Module Commercial Temperature Ranges
9
Ordering Information
7MP4145 SIMM VERSION
X
Power
X
Speed
X
Package
X
Process/
Temperature
Range
Blank
Commercial (0C to +70C)
Z
M
FR-4 ZIP (Zig-Zag In-line vertical Package, 4045 only)
FR-4 SIMM (Single In-line Memory Module)
15
20
25
XXXXX
Device
Type
IDT
Speed in Nanoseconds
S
Standard Power
7MP4045
7MP4145
256K x 32 Static RAM Module
256K x 32 Static RAM Module
2703 drw 16
,
0.350
MAX.
0.050
TYP.
FRONT VIEW
BACK VIEW
SIDE VIEW
PIN 1
PIN 1
0.640
0.660
0.240
0.260
0.390
0.410
0.250
TYP.
3.974
3.994
4.240
4.260
0.045
0.055
0.070
0.090
2703 drw 15
,
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
sramhelp@idt.com
Santa Clara, CA 95054
fax:408-492-8674
800 544-7726, x4033
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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