COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
DSC-3147/7
7.09
1
IDT7MP4060
IDT7MP4095
128K x 32
CMOS STATIC RAM
MODULES
FEATURES:
High density 4 megabit static RAM modules
Low profile 64-pin ZIP (Zig-zag In-line vertical Package),
64-lead, 72-lead SIMMs (Single In-line Memory Modules)
Fast access time: 15ns (max.)
Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
Single 5V (
10%) power supply
Multiple GND pins and decoupling capacitors for maxi-
mum noise immunity
Inputs/outputs directly TTL compatible
Gold plated fingers on the SIMM version
DESCRIPTION:
The IDT7MP4095/7MP4060 are 128K x 32 static RAM
modules constructed on an epoxy laminate (FR-4) substrate
using four 128K x 8 static RAMs in plastic SOJ packages. The
IDT7MP4095/7MP4060 are available with access times as
fast as 15ns with minimal power consumption.
The IDT7MP4095 is packaged in a 64-pin FR-4 ZIP (Zig-
zag In-line vertical Package) or a 64-lead SIMM (Single In-line
Memory Module). The IDT7MP4060 is packaged in a 72-lead
SIMM. The ZIP configuration allows 64 pins to be placed on
a package 3.65 inches long and 0.21 inches thick. At only 0.60
inches high, this low-profile package is ideal for systems with
minimum board spacing, while the SIMM configuration allows
use of edge mounted sockets to secure the module.
All inputs and outputs of the IDT7MP4095/7MP4060 are
TTL compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clocks or refresh for opera-
tion and provides equal access and cycle times for ease of
use.
ZIP, SIMM
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Integrated Device Technology, Inc.
PIN NAMES
I/O
0
31
Data Inputs/Outputs
A
0
16
Addresses
CS
1
4
Chip Selects
WE
Write Enable
OE
Output Enable
V
CC
Power
GND
Ground
NC
No Connect
3147 tbl 01
PIN CONFIGURATION 7MP4095
FUNCTIONAL BLOCK DIAGRAM
OE
WE
3147 drw 01
8
17
8
8
ADDRESS
I/O
0-31
128K x 32
RAM
CS
4
8
CS
3
CS
2
CS
1
31
29
9
11
13
15
17
19
21
23
25
1
3
5
7
27
33
63
61
41
43
45
47
49
51
53
55
57
35
37
39
59
32
30
28
8
10
12
14
16
18
20
22
24
2
4
6
26
34
64
62
42
44
46
48
50
52
54
56
58
36
38
40
60
GND
CS
3
A
16
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
WE
I/O
7
CS
1
PD
0
A
14
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
PD
1
GND
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
CS
2
A
15
PD
0
- OPEN
PD
1
- OPEN
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
7.09
2
CAPACITANCE
(T
A
= +25
C, F = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN(D)
Input Capacitance
V
(IN)
= 0V
12
pF
(Data and
CS
)
C
IN(A)
Input Capacitance
V
(IN)
= 0V
40
pF
(Address,
WE
,
OE
)
C
OUT
Output Capacitance
V
(OUT)
= 0V
12
pF
NOTE:
3147 tbl 04
1. This parameter is guaranteed by design but not tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade
Temperature
GND
V
CC
Commercial
0
C to +70
C
0V
5.0V
10%
3147 tbl 06
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
2.2
--
5.8
V
V
IL
Input Low Voltage
0.5
(1)
--
0.8
V
NOTE:
3147 tbl 05
1. V
IL
(min) = 3.0V for pulse width less than 10ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Value
Unit
V
TERM
Terminal Voltage with
0.5 to +7.0
V
Respect to GND
T
A
Operating Temperature
0 to +70
C
T
BIAS
Temperature Under Bias
10 to +85
C
T
STG
Storage Temperature
55 to +125
C
I
OUT
DC Output Current
50
mA
NOTES:
3147 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TRUTH TABLE
Mode
CS
CS OE
OE WE
WE
Output
Power
Standby
H
X
X
High Z
Standby
Read
L
L
H
DATA
OUT
Active
Write
L
X
L
DATA
IN
Active
Read
L
H
H
High-Z
Active
3147 tbl 02
PIN CONFIGURATION 7MP4060
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
NC
PD
2
GND
PD
1
I/O
8
I/O
9
I/O
10
I/O
11
A
0
A
1
A
2
I/O
12
I/O
13
I/O
14
I/O
15
GND
A
15
CS
2
CS
4
NC
OE
I/O
24
I/O
25
I/O
26
I/O
27
A
3
A
4
A
5
V
CC
A
6
I/O
28
I/O
29
I/O
30
I/O
31
NC
NC
NC
PD
3
PD
0
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
A
7
A
8
A
9
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
14
CS
1
CS
3
A
16
GND
I/O
16
I/O
17
I/O
18
I/O
19
A
10
A
11
A
12
A
13
I/O
20
I/O
21
I/O
22
I/O
23
GND
NC
NC
PD
0
- OPEN
PD
1
- OPEN
PD
2
- OPEN
PD
3
- GND
3147 drw 13
SIMM
TOP VIEW
7.09
3
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
10%, T
A
= 0
C to +70
C)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
LI
|
Input Leakage
V
CC
= Max.; V
IN
= GND to V
CC
--
10
A
(Data and
CS
)
|I
LI
|
Input Leakage
V
CC
= Max.; V
IN
= GND to V
CC
--
40
A
(Address,
WE
, and
OE
)
|I
LO
|
Output Leakage
V
CC
= Max.;
CS
= V
IH
, V
OUT
= GND to V
CC
--
10
A
V
OL
Output Low
V
CC
= Min., I
OL
= 8mA
--
0.4
V
V
OH
Output High
V
CC
= Min., I
OH
= 4mA
2.4
--
V
Symbol
Parameter
Test Conditions
Max.
Unit
I
CC
Dymanic Operating
f = f
MAX
;
CS
= V
IL
760
mA
Current
V
CC
= Max.; Output Open
I
SB
Standby Supply
CS
V
IH,
V
CC
= Max.
160
mA
Current
Outputs Open, f = f
MAX
I
SB1
Full Standby
CS
V
CC
0.2V; f = 0
60
mA
Supply Current
V
IN
> V
CC
0.2V or < 0.2V
3147 tbl 07
5 pF*
+5 V
480
30 pF*
DATA
OUT
255
+5 V
480
DATA
255
Figure 1. Output Load
Figure 2. Output Load
(for tOLZ, tOHZ, tCHZ, tCLZ,
tWHZ, tOW)
* Includes scope and jig.
3147 drw 03
OUT
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figures 1 and 2
3147 tbl 08
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
7.09
4
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
10%, T
A
= 0
C to +70
C)
-15
-20
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
Read Cycle
t
RC
Read Cycle Time
15
--
20
--
ns
t
AA
Address Access Time
--
15
--
20
ns
t
ACS
Chip Select Access Time
--
15
--
20
ns
t
CLZ
(1)
Chip Select to Output in Low Z
3
--
3
--
ns
t
OE
Output Enable to Output Valid
--
8
--
10
ns
t
OLZ
(1)
Output Enable to Output in Low Z
0
--
0
--
ns
t
CHZ
(1)
Chip Deselect to Output in High Z
--
8
--
12
ns
t
OHZ
(1)
Output Disable to Output in High Z
--
8
--
12
ns
t
OH
Output Hold from Address Change
3
--
3
--
ns
t
PU
(1)
Chip Select to Power-Up Time
0
--
0
--
ns
t
PD
(1)
Chip Deselect to Power-Down Time
--
15
--
20
ns
Write Cycle
t
WC
Write Cycle Time
15
--
20
--
ns
t
CW
Chip Select to End of Write
12
--
18
--
ns
t
AW
Address Valid to End of Write
12
--
18
--
ns
t
AS
Address Set-up Time
0
--
0
--
ns
t
WP
Write Pulse Width
12
--
18
--
ns
t
WR
Write Recovery Time
0
--
3
--
ns
t
WHZ
(1)
Write Enable to Output in High Z
--
8
--
13
ns
t
DW
Data to Write Time Overlap
10
--
12
--
ns
t
DH
Data Hold from Write Time
0
--
0
--
ns
t
OW
(1)
Output Active from End of Write
3
--
3
--
ns
NOTE:
3147 tbl 10
1. This parameter is guaranteed by design, but not tested.
7.09
5
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
TIMING WAVEFORM OF READ CYCLE NO. 3
(1,3,4)
NOTES:
1.
WE
is High for Read Cycle.
2. Device is continuously selected.
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition low.
4.
OE
= V
IL
.
5. Transition is measured
200mV from steady state. This parameter is guaranteed by design, but not tested.
OE
t
AA
t
OH
ADDRESS
t
RC
CS
t
OE
DATA
OUT
t
ACS
t
OHZ
(5)
t
CHZ
(5)
t
OLZ
(5)
3147 drw 04
t
CLZ
(5)
3147 drw 05
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALID
PREVIOUS DATA VALID
3147 drw 06
t
ACS
t
CHZ
DATA
OUT
CS
(5)
t
CLZ
(5)
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
7.09
6
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
NOTES:
1.
WE
or
CS
must be high during all address transitions.
2. A write occurs during the overlap (t
WP
) of a low
CS
and a low
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
low transition occurs simultaneously with or after the
WE
low transition, the outputs remain in a high impedance state.
6. Transition is measured
200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE
is low during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP or (
t
WHZ +
t
DW)
.
CS
3147 drw 08
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
DATA VALID
CS
3147 drw 07
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WHZ
t
OHZ
(6)
(6)
(4)
(4)
(7)
(6)
t
OW
OE
(6)
t
OHZ
DATA VALID
7.09
7
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS IDT7MP4095
SIMM VERSION
ZIP VERSION
3147 drw 10
3147 drw 09
0.600
MAX.
3.640
3.660
FRONT VIEW
BACK VIEW
0.015
0.025
0.100
TYP.
0.125
0.175
0.250
TYP.
0.050
TYP.
PIN 1
SIDE VIEW
0.100
TYP.
0.210
MAX.
3.574
3.594
3.840
3.860
0.390
0.410
0.240
0.260
PIN 1
FRONT VIEW
BACK VIEW
SIDE VIEW
0.045
0.055
0.250
TYP.
0.050
TYP.
0.060
0.064
0.062 R
0.070
0.090
0.210
MAX.
0.620
0.640
PIN 1
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
7.09
8
ORDERING INFORMATION
PACKAGE DIMENSIONS IDT7MP4060
X
Power
X
Speed
X
Package
X
Process/
Temperature
Range
Blank
Commercial (0
C to +70
C)
M
Z
FR-4 SIMM (Single In-line Memory Module)
FR-4 ZIP (Zig-zag In-line Package)
15
20
XXXXX
Device
Type
IDT
3147 drw 12
S
Standard Power
IDT7MP4060
IDT7MP4095
128K x 32 Static RAM Module (SIMM only)
128K x 32 Static RAM Module
Speed in Nanoseconds
3147 drw 11
0.390
0.410
PIN 1
PIN 1
FRONT VIEW
BACK VIEW
SIDE VIEW
0.045
0.055
0.250 TYP
0.050 TYP
0.240
0.260
4.240
4.260
3.974
3.994
0.070
0.090
0.062 R
0.060
0.064
R
0.210 MAX
0.640
0.660
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