FEATURES

Fully integrated octal E1 short haul line interface which
supports 120

E1 twisted pair and 75

E1 coaxial appli-

cations

Selectable single rail or dual rail mode and AMI or HDB3
line encoder/decoder

Built-in transmit pre-equalization meets G.703

Selectable transmit/receive jitter attenuator meets ETSI
CTR12/13, ITU G.736, G.742 and G.823 specifications

SONET/SDH optimized jitter attenuator meets ITU G.783
mapping jitter specification

Digital/analog LOS detector meets ITU G.775 and ETS 300
233

OCTAL E1 SHORT HAUL
LINE INTERFACE UNIT

IDT82V2058

FUNCTIONAL BLOCK DIAGRAM

Jitter

Attenuator

Jitter

Attenuator

HDB3/AMI

Decoder

HDB3/AMI

Encoder

Remote

Loopback

Analog

Loopback

Slicer

Peak

Detector

CLK&Data

Recovery

(DPLL)

Line

Driver

Waveform

Shaper

LOS

Detector

Digital

Loopback

AIS

Detector

One of Eight Identical Channels

File

Clock

Generator

MODE[2:0]

/JAS

SCLK/ALE/

/R/

SDI/

/
DS

SD0/RDY/

ACK INT

LP/D/AD[7:0]

MC/A[4:0]

MCLK

TRST TCK TMS TDI TDO

JTAG TAP

RTIPn

RRINGn

TTIPn

TRINGn

VDD IO

VDDT

VDDD
VDDA

LOSn

RCLKn

RDn/RDPn

CVn/RDNn

TCLKn

BPVIn/TDNn

TDn/TDPn

G.772

Monitor

Transmit
All Ones

Control Interface

CLKE

Figure - 1. Block Diagram

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

JANUARY 2003

DSC-6038/9

�

2002 Integrated Device Technology, Inc.

ITU G.772 non-intrusive monitoring for in-service testing
for any one of channel1 to channel7

Low impedance transmit drivers with tri-state

Selectable hardware and parallel/serial host interface

Local and remote loopback test functions

Hitless Protection Switching (HPS) for 1 to 1 protection
without relays

JTAG boundary scan for board test

3.3V supply with 5V tolerant I/O

Low power consumption

Operating temperature range: -40�C to +85�C

Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA)
and 160-pin Plastic Ball Grid Array (PBGA) packages

INDUSTRIAL TEMPERATURE RANGES

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Figure - 2. TQFP144 Package Pin Assignment

DESCRIPTION:

The IDT82V2058 is a single chip, 8-channel E1 short haul PCM

transceiver with a reference clock of 2.048MHz. It contains 8 transmit-
ters and 8 receivers.

Both receivers and transmitters can be programmed to work either

in single rail mode or dual rail mode. AMI or HDB3 encoder/decoder
is selectable in single rail mode. Pre-encoded transmit data in NRZ
format can be accepted when the device is configured in dual rail
mode. The receivers perform clock and data recovery by using
integrated digital phase-locked loop. As an option, the raw sliced data
(no retiming) can be output on the receive data pins. Transmit
equalization is implemented with low-impedance output drivers that
provide shaped waveforms to the transformer, guaranteeing template
conformance.

A jitter attenuator is integrated in the IDT82V2058 and can be

switched into either the transmit path or the receive path. The jitter at-

PIN CONFIGURATIONS

tenuation performance meets ETSI CTR12/13, ITU G.736, G.742, and
G.823 specifications.

The IDT82V2058 offers hardware control mode and software con-

trol mode. Software control mode works with either serial host interface
or parallel host interface. The latter works via an Intel/Motorola com-
patible 8-bit parallel interface for both multiplexed or non-
multiplexed applications. Hardware control mode uses
multiplexed pins to select different operation mode when host in-
terface is not available to the device.

The IDT82V2058 also provides loopback testing functions and

JTAG boundary scan testing functions. As the monitoring function is
integrated, IDT82V2058 can be configured as a 7-channel transceiver
with non-intrusive protected monitoring points.

The IDT82V2058 can be used for SDH/SONET multiplexers, cen-

tral office or PBX, digital access cross connects, digital radio base sta-
tions, remote wireless modules and microwave transmission systems.

BPVI3/TDN3

RCLK3

RD3/RDP3

CV3/RDN3
LOS3

RTIP3

RRING3

VDDT3

TTIP3
TRING3

GNDT3

RRING2

RTIP2

GNDT2

TRING2
TTIP2

VDDT2

RTIP1

RRING1

VDDT1

TTIP1
TRING1

GNDT1

RRING0

RTIP0

GNDT0

TRING0
TTIP0

VDDT0

MODE1

LOS0

CV0/RDN0

RD0/RDP0
RCLK0

BPVI0/TDN0

TD0/TDP0

1 2 3 4

5 6 7 8 9 10

1
1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

68
67

63
62

57
56

51
50

45
44

39
38

108 107 106 105

104 103 102 101 100 99

98 97 96 95 94 93

92 91 90 89 88

87 86 85 84 83 82

81 80 79 78 77 76

75 74 73

109

110

111

112

113
114

115

116

117

118

119

120

121

122

123

124

125
126

127

128

129

130

131
132

133

134

135

136

137
138

139

140

141

142

143
144

TD7/TDP7

TCLK7 LOS6

CV6/RDN6

RD6/RDP6

RCLK6

BPVI6/TDN6

TD6/TDP6

TCLK6 MCLK

MODE2

MC3/A3 MC2/A2 MC1/A1 MC0/A0

VDDIO GNDIO VDDD GNDD

LP0/D0/AD0

LP1/D1/AD1 LP2/D2/AD2 LP3/D3/AD3 LP4/D4/AD4 LP5/D5/AD5 LP6/D6/AD6

LP7/D7/AD7

TCLK1

TD1/TDP1

BPVI1/TDN1

RCLK1

RD1/RDP1

CV1/RDN1

LOS1 TCLK0

TD4/TDP4 TCLK4 LOS5 CV5/RDN5

RD5/RDP5 RCLK5 BPVI5/TDN5 TD5/TDP5 TCLK5 TDI

TDO TCK TMS TRST IC IC

VDDIO GNDIO VDDA GNDA MODE0/CODE

/JAS

SCLK/ALE/

/R/

SDI/

/
DS

SDO/RDY/

ACK

INT

TCLK2 TD2/TDP2 BPVI2/TDN2 RCLK2 RD2/RDP2 CV2/RDN2

LOS2 TCLK3 TD3/TDP3

BPVI4/TDN4

RCLK4

RD4/RDP4

CV4/RDN4

LOS4

CLKE

VDDT4

TTIP4

TRING4

GNDT4

RTIP4

RRING4

GNDT5

TRING5

TTIP5

VDDT5

RRING5

RTIP5

VDDT6

TTIP6

TRING6

GNDT6

RTIP6

RRING6

GNDT7

TRING7

TTIP7

VDDT7

RRING7

RTIP7

LOS7

CV7/RDN7

RD7/RDP7

RCLK7

BPVI7/TDN7

IDT
82V2058DA

INDUSTRIAL TEMPERATURE RANGES

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

PIN CONFIGURATIONS (CONTINUED)

Figure - 2b. PBGA160 Package Pin Assignment

VDDT

TRING

GNDT

RTIP

GNDT

TRING

VDDT

RDN

RCLK

RDP

RDN

RDP

RCLK

VDDT

TRING

GNDT

RTIP

GNDT

VDDT

RDN

RCLK

RDP

RDN

RDP

RCLK

VDDT

TTIP

GNDT

RRING

GNDT

TTIP

VDDT

TDN

TCLK

TDP

TDN

TDP

TCLK

LOS

CLKE

LOS

MODE

MCLK

TMS

TCK

TDO

TDI

GNDIO

VDDIO

TRST

VDDIO

GNDA

GNDD

VDDA

MODE

VDDD

SDI

SCLK

LOS

SDO

INT

LOS

MODE

VDDT

TTIP

GNDT

RRING

GNDT

TTIP

VDDT

TDN

TCLK

TDP

TDN

TDP

TCLK

VDDT

TRING

GNDT

RTIP

GNDT

TRING

VDDT

RDN

RCLK

RDP

RDN

RDP

RCLK

VDDT

TTIP

GNDT

RRING

GNDT

TTIP

VDDT

TDN

TCLK

TDP

TDN

TDP

TCLK

VDDT

TRING

GNDT

RTIP

GNDT

TRING

VDDT

RDN

RCLK

RDP

RDN

RDP

RCLK

VDDT

TTIP

GNDT

RRING

GNDT

TTIP

VDDT

TDN

TCLK

TDP

TDN

TDP

TCLK

TRING

IDT82V2058

Bottom View

RRING

A B C D E F G H J K L M N P

INDUSTRIAL TEMPERATURE RANGES

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Pin No.

Name

Type

QFP144 BGA160

Description

Transmit and Receive Line Interface

TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7

TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7

Analog

Output

45
52
57
64

117
124
129
136

46
51
58
63

118
123
130
135

L10

N10

B10

D10

M10

P10
A10

C10

TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7
These pins are the differential line driver outputs. They will be in high impedance state if pin OE
is low or the corresponding pin TCLKn is low (pin OE is globe control, while pin TCLKn is per-
channel control). In host mode, each pin can be in high impedance state by programming a "1" to
the corresponding bit in Register OE

RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7

RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7

Analog

Input

48
55
60
67

120
127
132
139

49
54
61
66

121
126
133
138

M7
M8

P8
A8

C8
C7

L7
L8

D8
D7

RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7
These pins are the differential line receiver inputs.

PIN DESCRIPTION

INDUSTRIAL TEMPERATURE RANGES

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Pin No.

Name

Type

QFP144 BGA160

Description

TDn: Transmit Data for Channel 0~7
When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data
on TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3 line
code rules before being transmitted to the line.

BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Signal Rail mode 2 (see table-1) with AMI enabled. A low-
to-high transition on this pin will make the next logic one to be transmitted on TDn pin the same
polarity as the previous pulse, and violate the AMI rule. This is for testing.

TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail mode, the NRZ data to be transmitted for positive/negative pulse
is input on this pin. Data on TDPn/TDNn are active high and sampled into the device on falling
edges of TCLKn. The line code in Dual Rail mode is as the follows :

TDPn

TDNn

Output Pulse

Space

Negative Pulse

Positive Pulse

Space

TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7

BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7

37
30
80
73

108
101

8
1

38
31
79
72

109
102

144

L13

N13
B13
D13

L12

N12
B12
D12

Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the
corresponding channel into Single Rail mode 1 (see table-1 on Page13).
TCLKn: Transmit Clock for Channel 0~7
The clock of 2.048 MHz to be transmitted is input on this pin. The transmit data at TDn/TDPn or
TDNn is sampled into the device on falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in
Transmit All One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts
MCLK as the time reference.
If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver
output ports become high impedance.
The different operating modes of TCLKn are summarized as follows:

MCLK

TCLKn

Transmitter Mode

Clocked

Normal operation

Clocked

High (

16 MCLK) Transmit All One (TAO) signals to line side in the

corresponding transmit channel.

Clocked

Low (

64 MCLK) Corresponding transmit channel is set into power down state.

TCLKn is clocked Normal operation
TCLKn is high
(

16 TCLK1)

Transmit All One (TAO) signals to the line
side in the corresponding transmit channel.

TCLKn is low
(

64 TCLK1)

Corresponding transmit channel is set into
power down state.

High/Low

TCLK1 is clocked

The receive path is not affected by the status of TCLK1.
When MCLK is high, all receive paths just slice the incoming
data stream. When MCLK is low, all the receive paths are
powered down.

TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7

36
29
81
74

107
100

9
2

L14

N14
B14
D14

High/Low

TCLK1 is not

available

(High/Low)

All eight transmitters (TTIPn & TRINGn) will be in high
impedance state.

PIN DESCRIPTION (CONTINUED)

Электронный компонент: IDT82V2058