1
2003 Integrated Device Technology, Inc. All rights reserved.
DSC-6221/5
QUAD CHANNEL T1/E1/J1 LONG HAUL/
SHORT HAUL LINE INTERFACE UNIT
IDT82V2084
FEATURES:
Four channel T1/E1/J1 long haul/short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
Per channel software selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line Build
Out)
- Line terminating impedance (T1:100
, J1:110 , E1:75 /120 )
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 2
20
-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Per channel cable attenuation indication
Adaptive receive sensitivity
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
IDT82V2084: 128-pin TQFP
DESCRIPTION:
The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1
Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to
remove the distortion introduced by the cable attenuation. The IDT82V2084
also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and
detects and reports the LOS conditions. In transmit path, there is an AMI/
B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2084 supports both Single Rail and Dual Rail system interfaces and
both serial and parallel control interfaces. To facilitate the network mainte-
nance, a PRBS/QRSS generation/detection circuit is integrated in each
channel, and different types of loopbacks can be set on a per channel basis.
Four different kinds of line terminating impedance, 75
, 100 , 110 and
120
are selectable on a per channel basis. The chip also provides driver
short-circuit protection and supports JTAG boundary scanning.
The IDT82V2084 can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
INDUSTRIAL TEMPERATURE RANGES July 2004
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
Figure-1 Block Diagram
Ana
l
og
Loop
bac
k
One
of th
e
Four I
d
e
n
ti
c
a
l
C
h
a
n
n
e
l
s
M
i
c
r
opr
oc
es
sor
Inter
f
ace
Cl
oc
k
Gene
r
a
tor
CS
SCLK
DS/RD
SDI/R/W/WR
SDO
INT
D[7:0]
A[7:0]
MCLK
TRST
TCK
TMS
TDI
TDO
JTAG TAP
B8ZS/
HDB3/
AMI
Encoder
J
i
tte
r
At
t
enuat
or
Li
ne
Dr
i
v
er
Wa
v
e
fo
rm
S
haper
/
L
BO
B8ZS/
HDB3/
AMI
Decoder
J
i
tte
r
At
t
enuat
or
Dat
a
S
lic
e
r
Ada
p
t
i
ve
E
q
ua
liz
e
r
LOS/
AI
S
Det
e
ct
or
Cl
ock a
n
d
Dat
a
Recove
r
y
VD
DD
VD
DIO
VD
DA
VD
DT
Di
gi
tal
Lo
opbac
k
Re
mote
Loop
bac
k
G.77
2
Moni
t
o
r
Tr
ansmi
t
t
e
r
In
te
rn
a
l
Ter
m
i
nat
i
o
n
Recei
v
er
In
te
rn
a
l
Ter
m
i
nat
i
o
n
TCLKn
TDNn
TD
n/
TDPn
RCLKn
CVn
/
RDNn
LOSn
RD
n/
RDPn
RRI
N
G
n
TTI
Pn
TRI
N
Gn
RTI
P
n
PRBS
Det
e
ct
or
IB
L
C
D
e
te
c
t
o
r
PRBS G
ener
at
or
I
B
LC G
ener
at
or
TA
OS
MCLKS
VD
DR
Basic
Contr
o
l
P/S
INT/MOT
THZ
REF
RST
SCLKE
3
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
1
IDT82V2084 PIN CONFIGURATIONS .......................................................................................... 8
2
PIN DESCRIPTION ....................................................................................................................... 9
3
FUNCTIONAL DESCRIPTION .................................................................................................... 14
3.1
T1/E1/J1 MODE SELECTION .......................................................................................... 14
3.2
TRANSMIT PATH ............................................................................................................. 14
3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 14
3.2.2 ENCODER .............................................................................................................. 14
3.2.3 PULSE SHAPER .................................................................................................... 14
3.2.3.1 Preset Pulse Templates .......................................................................... 14
3.2.3.2 LBO (Line Build Out) ............................................................................... 15
3.2.3.3 User-Programmable Arbitrary Waveform ................................................ 15
3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 19
3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 19
3.3
RECEIVE PATH ............................................................................................................... 20
3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 20
3.3.2 LINE MONITOR ...................................................................................................... 21
3.3.3 ADAPTIVE EQUALIZER......................................................................................... 21
3.3.4 RECEIVE SENSITIVITY ......................................................................................... 21
3.3.5 DATA SLICER ........................................................................................................ 21
3.3.6 CDR (Clock & Data Recovery)................................................................................ 21
3.3.7 DECODER .............................................................................................................. 21
3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 21
3.3.9 RECEIVE PATH POWER DOWN........................................................................... 21
3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 22
3.4
JITTER ATTENUATOR .................................................................................................... 23
3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 23
3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 23
3.5
LOS AND AIS DETECTION ............................................................................................. 24
3.5.1 LOS DETECTION ................................................................................................... 24
3.5.2 AIS DETECTION .................................................................................................... 25
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 26
3.6.1 TRANSMIT ALL ONES ........................................................................................... 26
3.6.2 TRANSMIT ALL ZEROS......................................................................................... 26
3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 26
3.7
LOOPBACK ...................................................................................................................... 26
3.7.1 ANALOG LOOPBACK ............................................................................................ 26
3.7.2 DIGITAL LOOPBACK ............................................................................................. 26
3.7.3 REMOTE LOOPBACK............................................................................................ 26
3.7.4 INBAND LOOPBACK.............................................................................................. 28
3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 28
3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 28
3.7.4.3 Automatic Remote Loopback .................................................................. 28
TABLE OF CONTENTS
4
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.8
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 29
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 29
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30
3.9
LINE DRIVER FAILURE MONITORING ........................................................................... 30
3.10 MCLK AND TCLK ............................................................................................................. 31
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 31
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 31
3.11 MICROCONTROLLER INTERFACES ............................................................................. 32
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32
3.12 INTERRUPT HANDLING .................................................................................................. 33
3.13 5V TOLERANT I/O PINS .................................................................................................. 33
3.14 RESET OPERATION ........................................................................................................ 33
3.15 POWER SUPPLY ............................................................................................................. 33
4
PROGRAMMING INFORMATION .............................................................................................. 34
4.1
REGISTER LIST AND MAP ............................................................................................. 34
4.2
REGISTER DESCRIPTION .............................................................................................. 36
4.2.1 GLOBAL REGISTERS............................................................................................ 36
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.2.7 LINE STATUS REGISTERS ................................................................................... 48
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 51
4.2.9 COUNTER REGISTERS ........................................................................................ 52
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 53
5
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 54
5.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 55
5.2
JTAG DATA REGISTER ................................................................................................... 55
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 55
5.2.2 BYPASS REGISTER (BR)...................................................................................... 55
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 55
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 56
6
TEST SPECIFICATIONS ............................................................................................................ 58
7
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 70
7.1
SERIAL INTERFACE TIMING .......................................................................................... 70
7.2
PARALLEL INTERFACE TIMING ..................................................................................... 71
5
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
Table-1
Pin Description ................................................................................................................ 9
Table-2
Transmit Waveform Value For E1 75
........................................................................ 16
Table-3
Transmit Waveform Value For E1 120
...................................................................... 16
Table-4
Transmit Waveform Value For T1 0~133 ft................................................................... 16
Table-5
Transmit Waveform Value For T1 133~266 ft............................................................... 16
Table-6
Transmit Waveform Value For T1 266~399 ft............................................................... 17
Table-7
Transmit Waveform Value For T1 399~533 ft............................................................... 17
Table-8
Transmit Waveform Value For T1 533~655 ft............................................................... 17
Table-9
Transmit Waveform Value For J1 0~655 ft ................................................................... 17
Table-10
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 18
Table-11
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 18
Table-12
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 18
Table-13
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 18
Table-14
Impedance Matching for Transmitter ............................................................................ 19
Table-15
Impedance Matching for Receiver ................................................................................ 20
Table-16
Criteria of Starting Speed Adjustment........................................................................... 23
Table-17
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24
Table-18
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25
Table-19
AIS Condition ................................................................................................................ 25
Table-20
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26
Table-21
EXZ Definition ............................................................................................................... 29
Table-22
Interrupt Event............................................................................................................... 33
Table-23
Global Register List and Map........................................................................................ 34
Table-24
Per Channel Register List and Map .............................................................................. 35
Table-25
ID: Chip Revision Register ............................................................................................ 36
Table-26
RST: Reset Register ..................................................................................................... 36
Table-27
GCF0: Global Configuration Register 0 ........................................................................ 36
Table-28
GCF1: Global Configuration Register 1 ........................................................................ 37
Table-29
INTCH: Interrupt Channel Indication Register............................................................... 37
Table-30
JACF: Jitter Attenuator Configuration Register ............................................................. 37
Table-31
TCF0: Transmitter Configuration Register 0 ................................................................. 38
Table-32
TCF1: Transmitter Configuration Register 1 ................................................................. 38
Table-33
TCF2: Transmitter Configuration Register 2 ................................................................. 39
Table-34
TCF3: Transmitter Configuration Register 3 ................................................................. 39
Table-35
TCF4: Transmitter Configuration Register 4 ................................................................. 39
Table-36
RCF0: Receiver Configuration Register 0..................................................................... 40
Table-37
RCF1: Receiver Configuration Register 1..................................................................... 41
Table-38
RCF2: Receiver Configuration Register 2..................................................................... 42
Table-39
MAINT0: Maintenance Function Control Register 0...................................................... 42
Table-40
MAINT1: Maintenance Function Control Register 1...................................................... 43
PDF 
ZIP