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Электронный компонент: Q532805SO

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QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
JULY 2000
1999 Integrated Device Technology, Inc.
DSC-5785/-
c
QS532805/A/B
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
3.3V CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
O EA
INA
INB
O A5
O A1
5
5
MO N
O B5
O B1
O EB
DESCRIPTION
The QS532805 clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of 5 non-inverting outputs. The QS532805 incorporates 25
series
termination resistors. This clock buffer product is designed for use in high
performance workstations, embedded and personal computing systems
using 3V to 3.6V supply voltages. Several can be used in parallel or
scattered throughout a system for guaranteed low skew, system-wide clock
distribution networks. The QS532805 can accept 5V input and control
signals.
The QS532805 is characterized for operation at -40C to +85C.
FEATURES:
-
JEDEC compatible LVTTL level inputs and outputs
-
10 output, low skew clock signal buffer
-
Monitor output
-
Clock inputs are 5V tolerant
-
Pinout and function compatible with QS5805T
-
25
on-chip resistors for low noise
-
Input hysteresis for better noise margin
-
Guaranteed low skew:
0.7ns output skew
0.7ns pulse skew
1ns part-to-part skew
-
Std., A, and B speed grades (B speed in QSOP package only)
-
Available in QSOP and SOIC packages
NOTE: QS532805 has a 25
series termination resistor on each clock output, including monitor.
2
INDUSTRIAL TEMPERATURE RANGE
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
PIN CONFIGURATION
QSOP/ SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
O A
1
O A
2
O A
3
G ND
A
O A
4
O A
5
G NDQ
O E
A
IN
A
O B
1
O B
2
O B
3
G ND
B
O B
4
O B
5
M O N
O E
B
IN
B
V
C CA
V
C CB
SO 20-2
SO 20-8
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +7
V
DC Output Voltage V
OUT
0.5 to Vcc+0.5
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
-3
V
I
OUT
DC Output Current V
IN
< 0
-20
mA
DC Output Current Max. Sink Current/Pin
120
mA
T
STG
Storage Temperature
65 to +150
C
T
J
Junction Temperature
150
C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz, V
IN
= 0V, V
OUT
= 0V)
Pins
Typ.
Max.
(1)
Unit
C
IN
4
6
pF
C
OUT
8
10
pF
NOTE:
1. This parameter is guaranteed but not production tested.
RECOMMENDED OPERATING
CONDITIONS
Symbol
Description
Min.
Max
Unit
V
CC
Power Supply Voltage
3
3.6
V
V
IN
Input Voltage
0
5.5
V
V
OUT
Voltage Applied to Outputs
0
V
CC
V
T
A
Ambient Operating Temperature
40
85
C
PIN DESCRIPTION
Pin Names
I/O
Description
OEA, OEB
I
Output Enable
INA, INB
I
Clock Inputs
OAn, OBn
O
Clock Outputs
MON
O
Monitor Outputs (does not 3-state)
3
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40C to +85C, V
CC
= 3.3V 0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for Inputs
2
--
5.5
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for Inputs
0.5
--
0.8
V
V
IC
Clamp Diode Voltage
(3)
Vcc = Min., I
IN
= -18mA
--
0.7
1.2
V
V
OH
Output HIGH Voltage
Vcc = Min., I
OH
= -100
A
Vcc 0.2
--
--
V
Vcc = Min., I
OH
= -8mA
2.4
--
--
V
V
OL
Output LOW Voltage
Vcc = Min., I
OL
= 100
A
--
--
0.2
V
Vcc = Min., I
OL
= 6mA
--
--
0.4
V
Vcc = Min., I
OL
= 8mA
--
--
0.5
V
I
IN
Input Leakage Current
Vcc = Max., V
IN
= Vcc or GND
--
--
1
A
I
OZ
Output Leakage Current
Vcc = Max., V
OUT
= Vcc or GND
--
--
1
A
I
OFF
Input Power Off Leakage
Vcc = 0V, V
IN
= Vcc or GND
--
--
1
A
I
ODH
Output HIGH Current
(2)
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
30
100
200
mA
I
ODL
Output LOW Current
(2)
Vcc = 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
30
100
200
mA
I
OS
Short Circuit Current
(2,3)
Vcc = Max., V
OUT
= GND
60
--
--
mA
R
OUT
Output Resistance
(4)
Vcc = Min
--
28
--
NOTES:
1. Typical values are at V
CC
= 3.3V, T
A
= 25C.
2. Not more than one output should be used to test this high power condition. Duration is less than one second.
3. Guaranteed by design but not tested.
4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(3)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or Vcc
0.01
100
A
I
CC
Supply Current per Input HIGH
V
CC
= Max., V
IN
= Vcc 0.6V, f = 0MHz
0.1
30
A
I
CCD
Dynamic Power Supply Current per Output
(2)
V
CC
= Max.,
OEA = OEB = GND
Outputs Toggling at 50% duty cycle
65
100
A/MHz
I
C
Total Power Supply Current Examples
(2,4)
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
3.3
5.2
mA
50% duty cycle, f
I
= 10MHz
five outputs toggling
V
IN
= GND or 3V
3.3
5.2
mA
V
CC
= Max.,
OEA = OEB = GND
V
IN
= GND or Vcc
1.8
2.9
mA
50% duty cycle, f
I
= 2.5MHz
All outputs toggling
V
IN
= GND or 3V
1.8
2.9
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Guaranteed by design but not tested. C
L
= 0pF.
3. Typical values are for reference only. Conditions are V
CC
= 3.3V, T
A
= 25C.
4. I
C
= I
CC
+ (
I
CC
)(D
H
)(N
I
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input Duty Cycle
N
I
= Number of TTL HIGH inputs at D
H
f
O
= Output Frequency
N
O
= Number of outputs at f
O
4
INDUSTRIAL TEMPERATURE RANGE
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40C to +85C, V
CC
= 3.3V 0.3V
C
LOAD
= 50pF (no resistor)
QS532805
QS532805A
QS532805B
(3)
Symbol
Parameter
(1)
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
SK(01)
Skew between all outputs, same transition, same bank
--
0.7
--
0.7
--
0.7
ns
t
SK(02)
Skew between two outputs, same transition, different banks
--
0.9
--
0.9
--
0.9
ns
t
SK(P)
Pulse Skew; skew between opposite transitions of the same output (t
PHL
- t
PLH
)
--
1
--
0.7
--
0.5
ns
t
SK(T)
Part-to-part skew
(2)
--
1.5
--
1
--
1
ns
NOTES:
1. This parameter is guaranteed but not production tested. Skew parameters apply to propagation delays only.
2. t
SK(T)
only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade.
3. The B speed grade is only available in the QSOP package.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40C to +85C, V
CC
= 3.3V 0.3V
C
LOAD
= 50pF (no resistor)
QS532805
QS532805A
QS532805B
(4)
Symbol
Parameter
(1,2)
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PLH
t
PHL
Propagation Delay
1.5
6.5
1.5
5.8
1.5
5.2
ns
t
R
Output Rise Time, 0.8V to 2V
(3)
--
2
--
2
--
2
ns
t
F
Output Fall Time, 2V to 0.8V
(3)
--
2
--
2
--
2
ns
t
PZL
t
PZH
Output Enable Time
1.5
8
1.5
8
1.5
6.5
ns
t
PLZ
t
PZH
Output Disable Time
1.5
7
1.5
7
1.5
6
ns
NOTES:
1. Minimums guaranteed but not production tested.
2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delays do not imply limit skew.
3. This parameter is guaranteed but not production tested.
4. The B speed grade is only available in the QSOP package.
5
QS532805/A/B
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
Pulse
Generator
500
500
V
CC
V
O UT
V
IN
DUT
50
50pF
6.0 V
Parameter
Tested
Switch
Position
All Others
Closed
Open
t
PLZ
, t
PZL
CONTROL
INPUT
ENABLE
DISABLE
3V
1.5V
0V
3V
0V
1.5V
1.5V
OUTPUT
NORM ALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
IN PUT
OUPUT 1
3V
1.5V
0V
1.5V
1.5V
OUPUT 2
INPUT
OUPUT
3V
1.5V
0V
1.5V
2.0V
0.8V
INPUT
PART 1 O UTPUT
3V
1.5V
0V
1.5V
1.5V
PART 2 O UTPUT
INPUT
OUPUT A
t
PLHA
3V
1.5V
0V
1.5V
1.5V
OUPUT B
INPUT
OUPUT
t
PLH
t
PHL
3V
1.5V
0V
V
O H
1.5V
V
OL
t
SK(p)
= t
PHL
- t
PLH
t
SK(02)
= t
PLHB
- t
PLHA
or t
PHLB
- t
PHLA
Pulse generator for all pulses: f
1.0MHz; t
F
2.5ns; t
R
2.5ns
V
O H
V
OL
V
O H
V
OL
t
PHLA
t
SK(02)
t
SK(02)
t
PLHB
t
PHLB
V
O H
V
OL
V
O H
V
OL
t
SK(01)
t
SK(01)
t
SK(01)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
t
PLH1
t
PHL1
t
PLH2
t
PHL2
V
O H
V
OL
V
OH
V
OL
t
PLH
t
PHL
t
R
t
F
OUTPUT
NORMALLY
HIG H
t
PZL
t
PLZ
t
PHZ
t
PZH
SWITCH
OPEN
t
PLH1
t
PHL1
t
SK(t)
t
SK(t)
t
PLH2
t
PHL2
t
SK(t)
= t
PLH2
- t
PLH1
or t
PHL2
- t
PHL1
V
O H
V
OL
V
OL
V
O H
PROPAGATION DELAY
PULSE SKEW -- t
SK(P)
OUTPUT SKEW (SAME BANK) -- t
SK(O1)
TEST CIRCUITS AND WAVEFORMS
OUPUT SKEW (DIFFERENT BANKS) -- t
SK(O2)
ENABLE AND DISABLE TIMES
PART-TO-PART SKEW -- t
SK(T)