FEATURES/BENEFITS
Enhanced N channel FET with no inherent diode to V
CC
5
bidirectional switches connect inputs to outputs
Pin compatible with the 74F253, 74FCT253, and 74FCT253T
Zero propagation delay, zero ground bounce
Undershoot clamp diodes on all switch and control pins
TTL-compatible control inputs
QS32253 is 25
version for low noise
Available in SOIC (S1), QSOP
APPLICATIONS
Logic replacement
Video, audio, graphics switching, muxing
Hot-swapping, hot-docking
(Application Note AN-13)
Voltage translation
(5V to 3.3V; Application Note AN-11)
Bus funneling
DESCRIPTION
The QS3253 is a high-speed CMOS TTL-compatible dual 4:1
multiplexer/demultiplexer with 3-state outputs. The QS3253 is
function and pinout compatible version of the 74F253, 74FCT253,
and the 74ALS/AS/LS253 dual 4:1 multiplexers. The low ON
resistance of the QS3253 allows inputs to be connected to
outputs without adding propagation delay and without generat-
ing additional ground bounce noise.
The QS32253 has 25
series resitors to reduce ground
bounce noise.
Mux/Demux devices provide an order of magnitude faster
speed than equivalent logic devices.
QS3253
QS32253
QUICKSWITCH
PRODUCTS
HIGH-SPEED CMOS
QUICKSWITCH
DUAL 4:1 MUX/DEMUX
FUNCTIONAL BLOCK DIAGRAM
OCTOBER 1999
1
1999 Integrated Device Technology, Inc
DSC-XXXXXX
S 0
Y
A
I0
A
I1
A
I2
A
I3
A
I0
B
I1
B
I2
B
I3
B
Y
B
S 1
E A
E B
2
1999 Integrated Device Technology, Inc
IDT
QS3253 AND QS32253
DSC-XXXXXX
Name
I/O
Description
I
XX
I
Data Inputs
S0, S1
I
Select Inputs
EA, EB
I
Enable Inputs
Y
A
, Y
B
O
Data Outputs
PIN CONFIGURATION
(ALL PINS TOP VIEW)
SOIC (S1), QSOP
FUNCTION TABLE
Enable
Select
Outputs
EA
EB
S1
S0
Y
A
Y
B
Function
H
X
X
X
Hi-Z
X
Disable A
X
H
X
X
X
Hi-Z
Disable B
L
L
L
L
I0
A
I0
B
S1-0 = 0
L
L
L
H
I1
A
I1
B
S1-0 = 1
L
L
H
L
I2
A
I2
B
S1-0 = 2
L
L
H
H
I3
A
I3
B
S1-0 = 3
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground ...................................................................... 0.5V to +7.0V
DC Switch Voltage V
S
............................................................................ 0.5V to +7.0V
DC Input Voltage V
IN
.............................................................................. 0.5V to +7.0V
AC Input Voltage (for a pulse width
20ns) .......................................................... 3.0V
DC Output Current Max. Sink Current/Pin ........................................................... 120mA
Maximum Power Dissipation ............................................................................ 0.5 watts
T
STG
Storage Temperature .................................................................... 65 to +150C
Note: ABSOLUTE MAXIMUM CONTINU-
OUS RATINGS are those values beyond
which damage to the device may occur.
Exposure to these conditions or conditions
beyond those indicated may adversely affect
device reliability. Functional operation under
absolute-maximum conditions is not implied.
Note: Capacitance is guaranteed, but not production tested and are typical values. For total
capacitance while the switch is ON, please see Section 1 under "Input and Switch
Capacitance."
CAPACITANCE
T
A
= 25C, f = 1MHz, V
IN
= 0V, V
OUT
= 0V
SOIC, QSOP
Pins
Typ
Max
Unit
Control Inputs
4
5
pF
QuickSwitch Channels
Demux
5
7
pF
(Switch OFF)
Mux
14
16
pF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EA
S1
I3
A
I2
A
I1
A
I0
A
Y
A
G ND
V
C C
EB
S0
I3
B
I2
B
I1
B
I0
B
Y
B
1999 Integrated Device Technology, Inc
IDT
QS3253 AND QS32253
DSC-XXXXXX
3
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH
2.0
--
--
V
for Control Pins
V
IL
Input LOW Voltage
Guaranteed Logic LOW
--
--
0.8
V
for Control Pins
| I
IN
|
Input Leakage Current
0V
V
IN
V
CC
--
--
1
A
(Control Inputs)
| I
OZ
|
Off-State Current (Hi-Z)
0V
V
OUT
V
CC
--
--
1
A
R
ON
Switch On Resistance
(2)
V
CC
= Min., V
IN
= 0.0V
QS3253
--
5
7
I
ON
= 30mA
QS32253
20
28
40
R
ON
Switch On Resistance
(2)
V
CC
= Min., V
IN
= 2.4V
QS3253
--
10
15
I
ON
= 15mA
QS32253
20
35
48
V
P
Pass Voltage
(3)
V
IN
= V
CC
= 5V, I
OUT
= 5 A
3.7
4.0
4.2
V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
T
A
= 40C to +85C, V
CC
= 5.0V 5%
TYPICAL ON RESISTANCE VS. V
IN
AT V
CC
= 5.0V (QS3253)
Notes:
1. Typical values indicate V
CC
= 5.0V and T
A
= 25C.
2. For a diagram explaining the procedure for R
ON
measurement, please see Section 1 under "DC Electrical Characteristics." R
ON
guaranteed, but not production tested.
3. Pass voltage is guaranteed, but not production tested.
16
14
12
10
8
6
4
2
0
R
ON
(ohms)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
IN
(Volts)
Note: For QS32253, add 23
to R
ON
shown.
4
1999 Integrated Device Technology, Inc
IDT
QS3253 AND QS32253
DSC-XXXXXX
QS3253
QS32253
Symbol
Description
(1)
(
Min
Typ
Max
Min
Typ
Max
Unit
t
PLH
Data Propagation Delay
(2,3)
--
--
0.25
(3)
--
--
1.25
(3)
ns
t
PHL
In to Y
t
PZL
Switch Turn-on Delay
0.5
--
6.6
0.5
--
7.0
ns
t
PZH
Sn to Y
t
PZL
Switch Turn-on Delay
0.5
--
6.0
0.5
--
7.0
ns
t
PZH
En to Y
t
PLZ
Switch Turn-off Delay
(2)
0.5
--
6.0
0.5
--
6.0
ns
t
PHZ
En to Y, Sn to Y
POWER SUPPLY CHARACTERISTICS OVER OPERATING RANGE
T
A
= 40C to +85C, V
CC
= 5.0V 5%
Symbol
Parameter
Test Conditions
(1)
Max
Unit
I
CCQ
Quiescent Power
V
CC
= Max., V
IN
= GND or V
CC
, f = 0
3
A
Supply Current
I
CC
Power Supply Current
(2)
V
CC
= Max., V
IN
= 3.4V, f = 0
1.5
mA
per Input HIGH
per control input
Q
CCD
Dynamic Power Supply
V
CC
= Max., I and Y Pins Open,
0.25
mA/
Current per MHz
(3)
Control Inputs Toggling @ 50% Duty Cycle
MHz
Switching Characteristics Over Operating Range
T
A
= 40C to +85C, V
CC
= 5.0V 5%
C
LOAD
= 50pF, R
LOAD
= 500
unless otherwise noted.
Notes:
1. See Test Circuit and Waveforms. Minimums guaranteed, but not production tested.
2. This parameter is guaranteed, but not production tested.
3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone is
of the order of 0.25ns for QS3253 and 1.25ns for QS32253 for C
L
= 50pF. Since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very
little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its
interaction with the load on the driven side.
Notes:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications.
2. Per TTL driven input (V
IN
= 3.4V, control inputs only). I and Y pins do not contribute to
I
CC
.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The I and Y inputs generate no
significant AC or DC currents as they transition. This parameter is guaranteed by characterization, but not production tested.
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