FEATURES/BENEFITS
Enhanced N channel FET with no inherent diode to V
CC
5
bidirectional switches connect inputs to outputs
Zero propagation delay and zero ground bounce
Undershoot clamp diodes on all control and switch pins
Available in 48-pin QVSOP (Q1)
Four enables control five bits each
TTL-compatible input and output levels
QS32XL2384 is 25
version for low noise
FEATURES/BENEFITS
Hot-docking, hot-swapping (Application Note AN-13)
Voltage translation (5V to 3.3V; Application Note AN-11)
Logic replacement (data processing)
Power conservation
Capacitance reduction and isolation
Low power for hand held and mobil applications
Bus isolation
Clock gating
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The QS32XL384 provides a set of twenty high-speed CMOS TTL-
compatible bus switches. The low ON resistance of the QS32XL384 allows
inputs to be connected to outputs without adding propagation delay and
without generating additional ground bounce noise. The Bus Enable (
BE)
signals turn the switches on. Four Bus Enable signals are provided, one for
each of five bits of the 20-bit bus. The `384 family of QuickSwitch products
is ideal for switching wide digital buses, as well as hot-docking, 5V to 3V
conversion and capacitance isolation for power conservation.
The QS32XL2384 adds an internal 25
series termination resistor to each
switch to reduce reflection noise in high speed applications.
QS32XL384
QS32XL2384
QUICKSWITCH
PRODUCTS
HIGH-SPEED CMOS
20-BIT BUS SWITCHES
OCTOBER 1999
1
1999 Integrated Device Technology, Inc
DSC-XXXXXX
B 4
BEC
BEA
B 0
A 4
A 0
B 9
B 5
A 9
A 5
B 14
BEB
BED
B 10
A 14
A 10
B 19
B 15
A 19
A 15
2
1999 Integrated Device Technology, Inc
IDT
QS32XL384 AND QS32XL2384
DSC-XXXXXX
QVSOP
Pins
Typ
Max
Unit
Control Inputs
3
5
pF
QuickSwitch Channels
5
7
pF
(Switch OFF)
BEA
BEB
B0-B4
B15-B19
Function
H
H
Hi-Z
Hi-Z
Disconnect
L
H
A0-A4
Hi-Z
Connect
H
L
Hi-Z
A15-A19
Connect
L
L
A0-A4
A15-A19
Connect
BEC
BED
B5-B9
B10-B14
Function
H
H
Hi-Z
Hi-Z
Disconnect
L
H
A5-A9
Hi-Z
Connect
H
L
Hi-Z
A10-A14
Connect
L
L
A5-A9
A10-A14
Connect
PIN DESCRIPTION
FUNCTION TABLE
PIN CONFIGURATION
(ALL PINS TOP VIEW)
QVSOP (Q1)
Name
I/O
Function
A0-A19
I/O
Bus A
B0-B19
I/O
Bus B
BEA
I
Enable, 0-4
BEB
I
Enable, 15-19
BEC
I
Enable, 5-9
BED
I
Enable, 10-14
ABSOLUTE MAXIMUM RATINGS
Supply Voltage to Ground ...................................................................... 0.5V to +7.0V
DC Switch Voltage V
S
............................................................................ 0.5V to +7.0V
DC Input Voltage V
IN
.............................................................................. 0.5V to +7.0V
AC Input Voltage (for a pulse width
20ns) .......................................................... 3.0V
DC Output Current Max. Sink Current/Pin ........................................................... 120mA
Maximum Power Dissipation ............................................................................ 0.5 watts
T
STG
Storage Temperature .................................................................... 65 to +150C
Note: ABSOLUTE MAXIMUM CONTINUOUS
RATINGS are those values beyond which
damage to the device may occur. Exposure to
these conditions or conditions beyond those
indicated may adversely affect device reliability.
Functional operation under absolute-maximum
conditions is not implied.
CAPACITANCE
T
A
= 25C, f = 1MHz, V
IN
= 0V, V
OUT
= 0V
Note: Capacitance is characterized but not
production tested. For total capacitance while the
switch is ON, please see section 1 under "Input
and Switch Capacitance."
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BEA
B0
A0
A1
B1
B2
A2
A3
B3
B4
A4
G ND
BEC
B5
A5
A6
B6
B7
A7
A8
B8
B9
A9
G ND
V
C C
B19
A19
A18
B18
B17
A17
A16
B16
B15
A15
BEB
V
C C
A14
B14
A13
B13
B12
A12
A11
B11
B10
A10
BED
1999 Integrated Device Technology, Inc
IDT
QS32XL384 AND QS32XL2384
DSC-XXXXXX
3
Symbol
Parameter
Test Conditions
Min
Typ
(1)
Max
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH
2.0
--
--
V
for Control Inputs
V
IL
Input LOW Voltage
Guaranteed Logic LOW
--
--
0.8
V
for Control Inputs
| I
IN
|
Input Leakage Current
0
V
IN
V
CC
--
0.01
1
A
(Control Inputs)
| I
OZ
|
Off-State Current (Hi-Z)
0
V
OUT
V
CC
, Switches Off
--
0.01
1
A
R
ON
Switch ON Resistance
(2)
V
CC
= Min., V
IN
= 0.0V
32XL384
--
5
7
I
ON
= 30mA
32XL2384
20
28
40
R
ON
Switch ON Resistance
(2)
V
CC
= Min., V
IN
= 2.4V
32XL384
--
10
15
I
ON
= 15mA
32XL2384
20
35
48
V
P
Pass Voltage
(3)
V
IN
= V
CC
= 5V, I
OUT
= 5A
3.7
4
4.2
V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
T
A
= 40C to 85C, V
CC
= 5.0V 5%
TYPICAL ON RESISTANCE VS V
IN
AT V
CC
5.0V (QS32XL384)
Notes:
1. Typical values indicate V
CC
= 5.0V and T
A
= 25C.
2. For a diagram explaining the procedure for R
ON
measurement, please see Section 1 under "DC Electrical Characteristics."
Max. value of R
ON
guaranteed, but not production tested.
3. Pass Voltage is guaranteed but not production tested.
Note: For 32XL2384, add 23
to R
ON
shown.
16
14
12
10
8
6
4
2
0
R
O N
(ohm s)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
IN
(Volts)
4
1999 Integrated Device Technology, Inc
IDT
QS32XL384 AND QS32XL2384
DSC-XXXXXX
POWER SUPPLY CHARACTERISTICS OVER OPERATING RANGE
T
A
= 40C to 85C, V
CC
= 5.0V 5%
Symbol
Parameter
Test Conditions
(1)
Max
Unit
I
CCQ
Quiescent Power
V
CC
= Max., V
IN
= GND or V
CC
, f = 0
6.0
A
Supply Current
I
CC
Power Supply Current
V
CC
= Max., V
IN
= 3.4V, f = 0
2.5
mA
per Input HIGH
(2)
per Control Input
Q
CCD
Dynamic Power Supply
V
CC
= Max., A and B Pins Open, Control
0.25
mA/
Current per MHz
(3)
Inputs Toggling @ 50% Duty Cycle
MHz
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= 40C to 85C, V
CC
= 5.0V 5%
C
LOAD
= 50pF, R
LOAD
= 500
unless otherwise noted.
Notes:
1. See Test Circuit and Waveforms. Minimums guaranteed but not production tested.
2. This parameter is guaranteed but not production tested.
3. The time constant for the switch alone is of the order of 0.25ns for QS32XL384 and 1.25ns for QS32XL2384 for C
L
= 50pF.
4. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. Since this time
constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus
switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5. Measured at switch turn off, A to B, load = 50pF in parallel with 10 Meg scope probe, V
IN
at A = 0.0V.
6. Guaranteed parameter. Not production tested.
QS32XL384 QS32XL2384
Symbol
Description
(1)
Min
Typ
Max
Min
Typ
Max
Unit
t
PLH
Data Propagation Delay
(2,4)
--
--
0.25
(3)
--
--
1.25
(3)
ns
t
PHL
Ai to Bi, Bi to Ai
t
PZL
Switch Turn-on Delay
1.5
--
6.5
1.5
--
7.5
ns
t
PZH
BE to Ai, Bi
t
PLZ
Switch Turn-off Delay
(2)
1.5
--
5.5
1.5
--
5.5
ns
t
PHZ
BE to Ai, Bi
Notes:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications.
2. Per TTL driven input (V
IN
= 3.4V, control inputs only). A and B pins do not contribute to
I
CC
.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency.
The A and B inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed, but not production tested.
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