1
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
IN A
OE A
5
OA
1
-O A
5
IN B
OE B
5
OB
1
-O B
5
M O N B
INC
OEC
5
OC
1
-OC
5
IND
OED
5
OD
1
-OD
5
M O ND
DECEMBER 2000
2000 Integrated Device Technology, Inc.
DSC-5822/-
c
QS5820T
COMMERCIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS 20 OUTPUT
CLOCK DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
20 output, low skew clock signal buffer
High drive FCT-type outputs
Reduced swing TTL outputs for low noise
Input hysteresis for better noise margin
Monitor output
Guaranteed low skew
0.5ns output skew
0.7ns pulse skew
1ns part-to-part skew
Available in 40-pin QVSOP
DESCRIPTION:
The QS5820T clock driver/buffer circuits can be used for clock distri-
bution schemes where low skew, high speed, and small footprint are
primary concerns. The QS5820T offers four banks of five non-inverting
outputs. Designed in IDT's proprietary QCMOS process, this device
provides low propagation delay buffering with on-chip skew of 0.5ns for
same-transition, same-bank signals. The QS5820T provides major skew
advantages over octal type devices where total part-to-part skew (t
SK(t)
)
of >1ns is unacceptable. Furthermore, board area consumed by the
QVSOP package is almost one-third that of the typical SOIC package
offered for octal devices. This clock buffer product is designed for use in
high performance workstation, multi-board computing and telecommuni-
cations systems. The QS5820T is available in the 40-pin QVSOP pack-
age which offers the world's smallest logic footprint.
2
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OA
1
OA
2
OA
3
GN D
OA
4
OA
5
GN D
OEA
IN A
V
D D
OC
1
OC
2
OC
3
GN D
OC
4
OC
5
GN D
OE C
INC
OB
1
OB
2
OB
3
GN D
OB
4
OB
5
MO N B
OEB
IN B
OD
1
OD
2
OD
3
GN D
OD
4
OD
5
MO ND
OED
IND
V
D D
V
D D
V
D D
SO 40-1
QVSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max.
Unit
V
TERM(2)
Supply Voltage to Ground
0.5 to +7
V
V
TERM(3)
DC Switch Voltage V
S
0.5 to +7
V
V
TERM(3)
DC Input Voltage V
IN
0.5 to +7
V
V
AC
AC Input Voltage (pulse width
20ns)
3
V
DC Input Diode Current with V
IN
< 0
20
mA
I
OUT
DC Output Current Max Sink Current/Pin
120
mA
P
MAX
Maximum Power Dissipation
1.2
W
T
STG
Storage Temperature Range
65 to +150
C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
DD
Terminals.
3. All terminals except V
DD
.
CAPACITANCE
(T
A
= 25
C, f = 1MHz, V
IN
= 0V, V
OUT
= 0V)
Pins
Typ.
Max.
Unit
All Pins
5
8
pF
NOTE:
1. Capacitance is characterized but not tested.
PIN DESCRIPTION
Pin Name
Type
Description
OEA, OEB, OEC, OED
I
Output Enable Inputs
INA, INB, INC, IND
I
Clock Inputs
OAn, OBn, OCn, ODn
O
Clock Outputs
MONB, MOND
O
Non-disable Monitor Outputs
RECOMMENDED OPERATING
CONDITIONS
Symbol
Description
Min.
Max.
Unit
V
DD
Power Supply Voltage
4.75
5.25
V
V
IN
Input Voltage
0
5.5
V
V
OUT
Voltage Applied to Outputs
0
5.5
V
T
A
Ambient Operating Temperature
0
+70
C
3
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH for Inputs
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW for Inputs
--
--
0.8
V
V
IC
Clamp Diode Voltage
(3)
V
DD
= Min., I
IN
=
-
18mA
--
-
0.7
-
1.2
V
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
=
-
24mA
2.4
--
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 64mA
--
--
0.55
V
I
IN
Input Leakage Current
V
DD
= Max., V
IN
= V
DD
or
GND
--
--
1
A
I
OZ
Output Leakage Current
V
DD
= Max., Outputs High-Z
--
--
1
A
I
OS
Short Circuit Current
(2,3)
V
DD
= Max., V
OUT
= GND
-
60
--
--
mA
NOTES:
1. Typical values are at V
DD
= 5.0V, T
A
= 25C.
2. Not more than one output should be used to test this high power condition. Duration is
1 second.
3. Guaranteed by design but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(3)
Max.
Unit
I
CC
Quiescent Power Supply Current
V
DD
= Max., V
IN
= GND or V
DD
0.4
3
mA
I
CC
Supply Current per Input HIGH
V
DD
= Max., V
IN
= 3.4V, f
I
= 0MHz
0.5
2.5
mA
I
CCD
Dynamic Power Supply Current per Output
(2)
V
DD
= Max., V
IN
= GND or V
DD
Outputs Enabled, 50% duty cycle
0.1
0.2
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications.
2. Guaranteed but not tested.
3. Typical values are for reference only. Conditions are V
DD
= 5.0V and T
A
= 25C.
4. I
C
= I
CC
+ (
I
CC
)(D
H
)(N
T
) + I
CCD
(f
O
)(N
O
)
where:
D
H
= Input duty cycle
N
T
= Number of TTL HIGH inputs at D
H
f
O
= Output frequency
N
O
= Number of outputs at f
O
4
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
QS5820AT
QS5820BT
Symbol
Description
(1)
Min.
Max.
Min.
Max.
Unit
t
SK(01)
Skew between two outputs, same transition, same bank
--
0.5
--
0.5
ns
t
SK(02)
Skew between two outputs, same transition, different bank
--
0.6
--
0.6
ns
t
SK(p)
Duty cycle distortion (pulse skew) on a single output opposite transitions (t
PHL
- t
PLH
)
--
1
--
0.7
ns
t
SK(t)
Part-to-part skew, same transition
(2)
--
1.5
--
1
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
C
LOAD
= 50pF, R
LOAD
= 500
unless otherwise noted.
QS5820AT
QS5820BT
Symbol
Description
(1)
Min.
Max.
Min.
Max.
Unit
t
PLH
t
PHL
Propagation Delay
(1,2)
1.5
5.8
1.5
5
ns
t
R
Output Rise Time, 0.8V to 2V
--
1.5
--
1.5
ns
t
F
Output Fall Time, 2V to 0.8V
--
1.5
--
1.5
ns
t
PZL
t
PZH
Output Enable Time
1.5
8
1.5
7
ns
t
PLZ
t
PHZ
Output Disable Time
1.5
7
1.5
6
ns
NOTES:
1. Skew parameters are guaranteed across temperature range, but not production tested. Skew parameters apply to propagation delays only.
2. t
SK(t)
only applies to devices of the same transition, same V
DD
, same temperature, same speed grade, and same loading.
NOTES:
1. Minimums guaranteed but not tested.
2. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation
delay limits do not imply skew.
5
COMMERCIAL TEMPERATURE RANGE
QS5820T
GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER
CORPORATE HEADQUARTERS
for SALES:
2975 Stender Way
800-345-7015 or 408-727-6116
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Turboclock is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
Q S
XXX
XX
Package
Device Type
5820AT
5820BT
Q uarter Size Very Sm all Outline Package (SO 40-1)
Q 2
G uaranteed Low S kew CM OS 20 Output Clock
Driver/B uffer
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