1
INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
JANUARY 2002
2002 Integrated Device Technology, Inc.
DSC-5817/2
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
QS5931
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
DESCRIPTION:
The QS5931 Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to a reference clock input. Six outputs are
available: Q
0
Q
4
, Q/2. Careful layout and design ensure < 500ps
skew between the Q
0
Q
4
, and Q/2 outputs. The QS5931 includes an
internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5931 is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
tem for guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5931 clock driver represents the best
value in small form factor, high-performance clock management prod-
ucts.
For more information on PLL clock driver products, see Application
Note AN-227.
FEATURES:
5V operation
Six low noise CMOS level outputs
Q outputs, Q/2 output
<500ps output skew, Q
0
Q
4
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Internal VCO/2 option
Balanced drive outputs 36mA
ESD >2000V
80MHz maximum frequency
Available in QSOP package
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q /2
0
1
1
0
/2
VCO
LOO P
FILTER
PH AS E
D ETE CTO R
FREQ _SEL
FEED BACK
SYNC
PLL_EN
O E/RST
Q
2
INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
AV
DD
/V
DD
Supply Voltage to Ground
0.5 to +7
V
DC Input Voltage V
IN
0.5 to +5.5
V
Maximum Power Dissipation (T
A
= 85C)
0.5
W
T
STG
Storage Temperature Range
65 to +150
C
QSOP
TOP VIEW
CAPACITANCE
(T
A
= +25C, f = 1MHz, V
IN
= 0V)
Pins
Typ.
Max.
Unit
C
IN
3
4
pF
C
OUT
4
5
pF
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC
I
Reference clock input
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies,
LOW is for lower frequencies.
FEEDBACK
I
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Q
0
-Q
4
O
Clock outputs
Q/
2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
OE/RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are
enabled.
PLL_EN
I
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
V
DD
--
Power supply for output buffers
AV
DD
--
Power supply for phase lock loop and other internal circuitries
GND
--
Ground supply for output buffers
AGND
--
Ground supply for phase lock loop and other internal circuitries
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= 40C to +85C, AV
DD
/V
DD
= 5.0V 10%
Symbol
Description
50
66
80
Units
F
MAX_Q
Max Frequency, Q
0
- Q
4
,
50
66
80
MHz
F
MAX_Q/2
Max Frequency, Q/2
25
33
40
MHz
F
MIN_Q
Min Frequency, Q
0
- Q
4
10
10
10
MHz
F
MIN_Q/2
Min Frequency, Q/2
5
5
5
MHz
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
G ND
O E /RST
FE ED BA CK
A V
DD
AG ND
SY NC
FREQ _S EL
G ND
Q
0
Q
4
Q /2
G ND
Q
3
Q
2
G ND
P LL_E N
G ND
Q
1
V
D D
V
D D
SO 20-8
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INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DD
= Max., OE/RST = LOW,
--
1
mA
SYNC = LOW, All outputs unloaded
I
DD
Power Supply Current per Input HIGH
V
DD
= Max., V
IN
= 3V
1
30
A
I
DDD
Dynamic Power Supply Current per Output
V
DD
= Max., C
L
= 0pF
0.2
0.3
A/MHz
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
(allowable range)
(1)
Output Frequency Relationships
FREQ_SEL
Feedback
Min.
Max
Q/2
Q
0
- Q
4
HIGH
Q/2
F
MIN_Q/2
F
MAX _Q/2
SYNC
SYNC X 2
HIGH
Q
0
-Q
4
F
MIN_Q
F
MAX _Q
SYNC / 2
SYNC
LOW
Q/2
F
MIN_Q/2
/2
F
MAX _Q/2
/2
SYNC
SYNC X 2
LOW
Q
0
-Q
4
F
MIN_Q
/2
F
MAX _Q
/2
SYNC / 2
SYNC
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_Q
x2. Operation with Sync inputs outside specified
frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, AV
DD
/V
DD
= 5.0V 10%
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
--
--
0.8
V
V
OH
Output HIGH Voltage
I
OH
=
-
24mA
V
DD
-- 0.6
--
--
V
I
OH
=
-
100
A
V
DD
-- 0.2
--
--
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 24mA
--
--
0.45
V
V
DD
= Min., I
OL
= 100
A
--
--
0.2
V
H
Input Hysteresis
--
--
100
--
mV
I
OZ
Output Leakage Current
V
OUT
= V
DD
or GND,
--
--
5
A
V
DD
= Max., Outputs Disabled
I
IN
Input Leakage Current
AV
DD
= Max., V
IN
= AV
DD
or GND
--
--
5
A
INPUT TIMING REQUIREMENTS
Symbol
Description
(1)
Min.
Max.
Unit
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
--
3
ns
F
I
Input Clock Frequency, SYNC
(1)
2.5
F
MAX _Q
MHz
t
PWC
Input clock pulse, HIGH or LOW
(2)
2
--
ns
D
H
Duty Cycle, SYNC
(2)
25
75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and FREQ_SEL
combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
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INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
(1)
Min.
Max.
Unit
t
SKR
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(2)
--
500
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/2
(2)
--
500
ps
t
PW
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
T
CY
/2
-
0.4
T
CY
/2 + 0.4
ns
t
J
Cycle-to-Cycle Jitter
(4)
-- 0.15
0.15
ns
t
PD
SYNC Input to Feedback Delay
(5)
-
500
500
ps
t
LOCK
SYNC to Phase Lock
--
10
ms
t
PZH
Output Enable Time, OE/RST LOW to HIGH
(3)
0
14
ns
t
PZL
t
PHZ
Output Disable Time, OE/RST HIGH to LOW
(3)
0
14
ns
t
PLZ
t
R,
t
F
Output Rise/Fall Times, 0.2V
DD
to 0.8V
DD
0.3
2.5
ns
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. t
PD
measured at device inputs at 1.5V, Q output at 80MHz.
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INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30pF
300
7.0V
O UTPU T
V
D D
O UTP UT
1.0ns
1.0ns
2.0V
0.8V
3.0V
0V
V
th
= 1.5V
t
R
t
F
0V
0.5V
D D
0.8V
D D
0.2V
D D
V
D D
t
P W
CO NTROL
IN PU T
EN ABLE
DISABLE
3V
1.5V
0V
3.5V
0V
0.5V
D D
O UTP UT
NOR M ALLY
LOW
O UTP UT
NO R MALLY
HIG H
SW ITCH
O PEN
SW ITC H
CLO SED
t
P Z H
0.3V
0.3V
t
P Z L
t
PLZ
t
P H Z
0.5V
D D
V
O H
V
O L
100
100
AC TEST LOADS AND WAVEFORMS
Test Circuit 1
CMOS Input Test Waveform
CMOS Output Waveform
Test Circuit 2
TEST CIRCUIT 1 is used for output enable/disable parameters.
TEST CIRCUIT 2 is used for all other timing parameters.
Enable and Disable Times
6
INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
AC TIMING DIAGRAM
t
P D
SYNC
FEEDBACK
Q
Q
0
-Q
4
Q /2
t
J
t
SK F
t
SK ALL
t
S KR
NOTES:
1. AC Timing Diagram applies to Q output connected to FEEDBACK and PE = GND. For PE = V
DD
, the negative edge of FEEDBACK aligns with the negative edge of SYNC
input, and the negative edges of the multiplied and divided outputs align with the negative edge of SYNC.
2. All parameters are measured at 0.5V
DD
.
7
INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SIMPLIFIED DIAGRAM OF QS5931 FEEDBACK
Q /2
Q
VCO /2
/2
PHAS E
DETECTO R
INPU T
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5931 pro-
vides for replication of incoming SYNC clock signals. Any manipulation
of that signal, such as frequency multiplying, is performed by digital
logic following the PLL (see the block diagram). The key advantage of
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back, it
will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5931 typically provides within 150ps of
phase shift between input and output.
the PLL circuit is to provide an effective zero propagation delay be-
tween the output and input signals. In fact, adding delay circuits in the
feedback path, `propagation delay' can even be negative! A simplified
schematic of the QS5931 PLL circuit is shown below:
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for feed-
back will be advanced by the amount of delay in the feedback path. All
other outputs will retain their proper relationships to that output.
8
INDUSTRIAL TEMPERATURE RANGE
QS5931
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
Q S
X
Speed
5931
Low Skew C M O S PLL C lock D river with Integrated
Loop Filter
Q
Q uarter S ize Outline Package
XXXX
D evice Type
X
Package
-50
-66
-80
50 M H z. m ax. frequency
66 M H z. m ax. frequency
80 M H z. m ax. frequency
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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