TECHNICAL DATA
421
Octal 3-State Noninverting
Transparent Latch
High-Speed Silicon-Gate CMOS
The IN74ACT373 is identical in pinout to the LS/ALS373,
HC/HCT373. The IN74ACT373 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
A; 0.1
A @ 25
C
Outputs Source/Sink 24 mA
IN74ACT373
ORDERING INFORMATION
IN74ACT373N Plastic
IN74ACT373DW SOIC
T
A
= -40
to 85
C for all
packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
Output
Enable
Latch
Enable
D
Q
L
H
H
H
L
H
L
L
L
L
X
No Change
H
X
X
Z
X = Don't Care
Z = High Impedance
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
IN74ACT373
422
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Sink/Source Current, per Pin
50
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
J
Junction Temperature (PDIP)
140
C
T
A
Operating Temperature, All Package Types
-40
+85
C
I
OH
Output Current - High
-24
mA
I
OL
Output Current - Low
24
mA
t
r
, t
f
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=4.5 V
V
CC
=5.5 V
0
0
10
8.0
ns/V
*
V
IN
from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74ACT373
423
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limits
Symbol
Parameter
Test Conditions
V
25
C
-40
C to
85
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low -
Level Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
V
OH
Minimum High-Level
Output Voltage
I
OUT
-50
A
4.5
5.5
4.4
5.4
4.4
5.4
V
*
V
IN
= V
IL
or V
IH
I
OH
=-24 mA
I
OH
=-24 mA
4.5
5.5
3.86
4.86
3.76
4.76
V
OL
Maximum Low-Level
Output Voltage
I
OUT
50
A
4.5
5.5
0.1
0.1
0.1
0.1
V
*
V
IN
= V
IL
or V
IH
I
OL
=24 mA
I
OL
=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
5.5
0.1
1.0
A
I
OZ
Maximum Three-
State Leakage
Current
V
IN
(OE)=V
IL
or V
IH
V
IN
=V
CC
or GND
V
OUT
=V
CC
or GND
5.5
0.5
5.0
A
I
CCT
Additional Max
I
CC
/Input
V
IN
=V
CC
- 2.1 V
5.5
1.5
mA
I
OLD
+Minimum Dynamic
Output Current
V
OLD
=1.65 V Max
5.5
75
mA
I
OHD
+Minimum Dynamic
Output Current
V
OHD
=3.85 V Min
5.5
-75
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
5.5
8.0
80
A
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
IN74ACT373
424
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
C
-40
C to 85
C
Unit
Min
Max
Min
Max
t
PLH
Propagation Delay, Input D to Q (Figure 1)
2.5
10
1.5
11.5
ns
t
PHL
Propagation Delay, Input D to Q (Figure 1)
2.0
10
1.5
11.5
ns
t
PLH
Propagation Delay, Latch Enable to Q (Figure 2)
2.5
11
2.0
11.5
ns
t
PHL
Propagation Delay, Latch Enable to Q (Figure 2)
2.0
10
1.5
11.5
ns
t
PZH
Propagation Delay, Output Enable to Q
(Figure 3)
2.0
9.5
1.5
10.5
ns
t
PZL
Propagation Delay, Output Enable to Q
(Figure 3)
2.0
9.0
1.5
10.5
ns
t
PHZ
Propagation Delay, Output Enable to Q
(Figure 3)
2.5
11
2.5
12.5
ns
t
PLZ
Propagation Delay, Output Enable to Q
(Figure 3)
1.5
8.5
1.0
10
ns
C
IN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25
C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
40
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
10%, C
L
=50pF, Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
C
-40
C to 85
C
Unit
t
su
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
7.0
8.0
ns
t
h
Minimum Hold Time, Latch Enable to
Input D (Figure 4)
0
1.0
ns
t
w
Minimum Pulse Width, Latch Enable
(Figure 2)
2.0
8.0
ns
IN74ACT373
425
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
PDF 
ZIP