ChipFind - документация

Электронный компонент: C1004

Скачать:  PDF   ZIP
IMP, Inc.
ISO 9001 Registered
17
Process C1004
CMOS 1.0
m
5 Volt Digital
N-Channel Transistor
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
N
0.55
0.75
0.95
V
100x1.0
m
Body Factor
N
0.60
V
1/2
100x1.0
m
Conduction Factor
N
74
87
100
A/V
2
100x100
m
Effective Channel Length
Leff
N
0.60
0.75
0.90
m
100x1.0
m
Width Encroachment
W
N
0.8
m
Per side
Punch Through Voltage
BVDSS
N
7
V
Poly Field Threshold
VTF
P(N)
10
V
P-Channel Transistor
Symbol
Minimum
Typical
Maximum
Unit
Comments
Threshold Voltage
VT
P
0.85
1.0
1.15
V
100x1.0
m
Body Factor
P
0.4
V
1/2
100x1.0
m
Conduction Factor
P
24
28
32
A/V
2
100x100
m
Effective Channel Length
Leff
P
0.83
0.98
1.13
m
100x1.0
m
Width Encroachment
W
P
0.85
m
Per side
Punch Through Voltage
BVDSS
P
7
V
Poly Field Threshold Voltage
VTF
P(P)
10
V
Diffusion & Thin Films
Symbol
Minimum
Typical
Maximum
Unit
Comments
Well (field) Sheet Resistance
N-well(f)
0.8
1.0
1.22
K
/
n-well
N+ Sheet Resistance
N+
20
35
50
/
N+ Junction Depth
x
jN+
0.45
m
P+ Sheet Resistance
P+
60
80
100
/
P+ Junction Depth
x
jP+
0.5
m
Gate Oxide Thickness
T
GOX
20
nm
Field Oxide Thickness
T
FIELD
700
nm
Poly Sheet Resistance
POLY
15
22
30
/
Metal-1 Sheet Resistance
M1
50
m
/
Metal-2 Sheet Resistance
M2
30
m
/
Passivation Thickness
T
PASS
200+900
nm
oxide+nit.
Capacitance
Symbol
Minimum
Typical
Maximum
Unit
Comments
Gate Oxide
C
ox
1.52
1.64
1.82
fF/
m
2
Metal-1 to Poly1
C
M1P
0.046
fF/
m
2
Metal-1 to SIlicon
C
MIS
0.028
fF/
m
2
Metal-2 to Metal-1
C
MM
0.038
fF/
m
2
Electrical Characteristics
T=25
o
C Unless otherwise noted
18
C1004-4-98
Physical Characteristics
VGS = 5.0V
VGS = 4.0V
VGS = 3.0V
VGS = 2.0V
VGS = 1.0V
0
5.0
35.0
28.0
21.0
14.0
1.0
2.0
3.0
4.0
ID vs VD, W/L = 20/1.2
N-ch Transistor IV Characteristics of a 20/1.2 device
7.0
0
Drain Current (mA) I
DS
Drain Voltage (V) V
DS
VGS = 5.0V
VGS = 4.0V
VGS = 3.0V
VGS = 2.0V
0
5.0
15.0
12.0
9.0
6.0
1.0
2.0
3.0
4.0
ID vs VD, W/L = 20/1.2
P-ch Transistor IV Characteristics of a 20/1.2 device
3.0
0
Drain Current (mA) I
DS
Drain Voltage (V) V
DS
Starting Material
P <100>
N+/P+ Width/Space
2.0 / 1.2
m
Starting Mat. Resistivity
7-8.5
-cm
N+ To P+ Space
7.0
m
Typ. Operating Voltage
5V
Contact To Poly Space
0.8
m
Well Type
N-well
Contact Overlap Of Diffusion
0.7
m
Metal Layers
2
Contact Overlap Of Poly
0.7
m
Poly Layers
1
Metal-1 Overlap Of Contact
0.7
m
Contact Size
1.2x1.2
m
Metal-1 Overlap Of Via
0.7
m
Via Size
1.2x1.2
m
Metal-2 Overlap Of Via
0.7
m
Metal-1 Width/Space
1.4 / 1.2
m
Minimum Pad Opening
65x65
m
Metal-2 Width/Space
2.0 / 1.4
m
Minimum Pad-to-Pad Spacing
5.0
m
Gate Poly Width/Space
1.0 / 1.4
m
Minimum Pad Pitch
80.0
m
Metal 2
Metal 1
SIO
2
LTO
n
+
n
+
p
n
+
p
+
p
Field Oxide
N-well contact
Source
Poly gate
N-well
Drain
Contact
Drain
LDD
Poly gate
Sidewall spacer
Source
p
substrate contact
Channel stop
p
+
substrate
p
epi
p
+
p
+
LTO
Process C1004