1999 IMP, Inc.
408-432-9100/www.impweb.com
1
Key Features
x
Pin compatible with the Dallas Semiconductor
DS1232LP/1232LPS
-- 40% lower supply current
x
5V supply monitor
x
Selectable watchdog period
x
Debounce manual push-button reset input
x
Precision temperature-compensated voltage
reference and comparator
x
Power-up, power-down and brownout detection
x
250ms reset time
x
Active LOW open-drain reset and active HIGH
push-pull output
x
Selectable trip point tolerance: 5% or 10%
x
Low-cost, surface mount packages: 8/16-pin
SO, 8-pin DIP and 8-pin MicroSO
x
Wide operating temperature 40
C to +85
C
(N/EPA suffixed devices)
Block Diagram
RESET
PBRST
1 (2)
1232_03.eps
40k
TOL
IMP1232LP/LPS
(16-Pin Package)
3 (6)
V
CC
+
5%/10% Tolerance
Selection
Reference
V
CC
8 (15)
RESET
5 (9)
TD
Push Button
Debounce
2 (4)
Watchdog
Timebase Selection
GND
4 (8)
Reset &
Watchdog Timer
6 (11)
ST
7 (13)
Watchdog
Transition Detector
IMP1
IMP1
232LP/LPS
232LP/LPS
P
OWER
M
ANAGEMENT
5V
5V
P P
P P
o
o
w
w
er Suppl
er Suppl
y Monit
y Monit
or and
or and
R
R
eset Cir
eset Cir
cuit
cuit
Select
Select
able T
able T
r
r
i
i
p
p
-P
-P
oint T
oint T
oler
oler
ance
ance
and W
and W
atc
atc
hdog P
hdog P
er
er
iod
iod
Push-Butt
Push-Butt
on R
on R
eset
eset
The IMP1232LP/LPS microprocessor supervisor can halt and restart a
"hung-up" or "stalled" microprocessor, restart a microprocessor after a
power failure, and debounce and interface a manual push-button micro-
processor reset switch. The low-power supervisors feature 40% lower
supply current than the pin compatible Dallas Semiconductor
DS1232LP/LPS.
Precision temperature compensated reference and comparator circuits
monitor the 5V, V
CC
input voltage. During power-up or when the V
CC
power supply falls outside selectable tolerance limits, both the RESET
and RESET become active. When V
CC
rises above the threshold voltage,
the reset signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to stabilize. The
trip point tolerance signal, TOL, selects the trip level tolerance to be
either 5- or 10-percent.
Each device has both a push-pull, active HIGH reset output and an open
drain, active LOW reset output.
A debounced manual reset input activates the reset outputs for a mini-
mum period of 250ms.
Also included is a watchdog timer to stop and restart a microprocessor
that is "hung-up". Three watchdog time-out periods are selectable:
150ms, 610ms and 1,200ms. If the ST input is not strobed
LOW before the time-out period expires, a reset is issued.
Devices are available in 8-pin DIP, 8/16-pin SO and com-
pact 8-pin MicroSO packages.
2
408-432-9100/www.impweb.com
1999 IMP, Inc.
Pin Configuration
IMP1
IMP1
232LP/LPS
232LP/LPS
Pin Descriptions
IMP1232LP
IMP1232LPS-2
IMP1232LPCMA
IMP1232LPEMA
5
1232_01.eps
RESET
6 RESET
7 ST
8
4
3
2
1
V
CC
GND
TOL
TD
PBRST
Ordering Information
1232_02.eps
IMP1232LPSN
13 ST
14 NC
15 V
CC
16
4
3
2
1
NC
TD
12 NC
5
NC
11 RESET
6
TOL
10 NC
7
NC
9 RESET
8
GND
NC
PBRST
NC
DIP/SO/MicroSO
SO
r
e
b
m
u
N
t
r
a
P
e
g
a
k
c
a
P
e
r
u
t
a
r
e
p
m
e
T
g
n
i
t
a
r
e
p
O
e
g
n
a
R
y
l
p
p
u
S
m
u
m
i
x
a
M
(
t
n
e
r
r
u
C
)
A
g
n
i
r
o
t
i
n
o
M
e
g
a
t
l
o
V
n
o
i
t
a
c
i
l
p
p
A
P
L
2
3
2
1
P
M
I
P
I
D
-
8
0 C
0
7
o
t
C
0
3
V
5
S
P
L
2
3
2
1
P
M
I
O
S
-
6
1
0 C
0
7
o
t
C
0
3
V
5
2
-
S
P
L
2
3
2
1
P
M
I
O
S
-
8
0 C
0
7
o
t
C
0
3
V
5
A
M
C
P
L
2
3
2
1
P
M
I
O
S
o
r
c
i
M
-
8
0 C
0
7
o
t
C
0
3
V
5
A
M
E
P
L
2
3
2
1
P
M
I
O
S
o
r
c
i
M
-
8
0
4
C
5
8
o
t
C
0
3
V
5
N
P
L
2
3
2
1
P
M
I
P
I
D
-
8
0
4
C
5
8
o
t
C
0
3
V
5
2
-
N
S
P
L
2
3
2
1
P
M
I
O
S
-
8
0
4
C
5
8
o
t
C
0
3
V
5
N
S
P
L
2
3
2
1
P
M
I
O
S
-
6
1
0
4
C
5
8
o
t
C
0
3
V
5
s
p
e
.
1
0
t
_
2
3
2
1
Pin Number
Pin Number
8-Pin P
8-Pin P
ac
ac
k
k
ag
ag
e
e
1
1
6-Pin P
6-Pin P
ac
ac
k
k
ag
ag
e
e
N
N
ame
ame
F
F
unction
unction
1
2
PBRST
Debounced manual pushbutton RESET input
2
4
TD
Watchdog time delay selection. (t
TD
= 150ms for TD = GND, t
TD
= 610ms
for TD = Open, and t
TD
=1200ms for TD = V
CC
)
3
6
TOL
Selects 5% (TOL connected to GND) or 10% (TOL connected to V
CC
) trip
point tolerance
4
8
GND
Ground
5
9
RESET
Active HIGH reset output. RESET is active:
1. If V
CC
falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power-up.
6
11
RESET
Active LOW reset output. (See RESET)
7
13 ST
Strobe
Input
8
15
V
CC
5V power
--
1, 3, 5, 7, 10,
NC
No internal connection
12, 14, 16
1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP1
IMP1
232LP/LPS
232LP/LPS
Absolute Maximum Ratings
Electrical Characteristics
Voltage on V
CC
. . . . . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . 0.5V to V
CC
+ 0.5V
Voltage on PBRST, RESET, RESET . . . . . . . . 0.5V to V
CC
+ 0.5V
Operating Temperature Range . . . . . . . . . . . 40
C to 85
C
(N/EMA version)
0
C to 70
C
Soldering Temperature . . . . . . . . . . . . . . . . . . 260
C for 10 seconds
Storage Temperature . . . . . . . . . . . . . . . . . . . 55
C to 125
C
Voltages measured with respect to ground.
These are stress ratings only and functional operation is not implied.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage (V
CC
)
V
CC
4.5
5.5
V
ST and PBRST Input High Level
V
IH
2
V
CC
+ 0.3V
V
ST and PBRST Input Low Level
V
IL
0.3
0.8
V
V
CC
Trip Point (TOL = GND)
V
CCTP
4.50
4.62
4.74
V
V
CC
Trip Point (TOL = V
CC
)
V
CCTP
4.25
4.37
4.49
V
Watchdog Time-Out Period
t
TD
TD = GND
62.5
150
250
ms
Watchdog Time-Out Period
t
TD
TD = V
CC
500
1200
2000
ms
Watchdog Time-Out Period
t
TD
TD floating
250
610
1000
ms
Output Voltage
V
OH
I = 500
A, Note 3
V
CC
- 0.5V
V
CC
- 0.1V
V
Output Current
I
OH
Output = 2.4V , Note 2
8
10
mA
Output Current
I
OL
Output = 0.4V,
10
mA
Input Leakage
I
IL
Note 1
1.0
1.0
A
RESET Low Level
V
OL
0.4
V
Internal Pull-Up Resistor
Note 1
40
k
Operating Current (CMOS)
I
CC1
30
A
Input Capacitance
C
IN
5
pF
Output Capacitance
C
OUT
10
pF
PBRST Manual Reset
t
PB
PBRST = V
IL
20
ms
Minimum Low Time
Reset Active Time
t
RST
250
610
1000
ms
ST Pulse Width
t
ST
Note 4
20
ns
V
CC
Fail Detect to
t
RPD
5
8
s
RESET or RESET
V
CC
Slew Rate
t
F
4.75V to 4.25V
300
s
PBRST Stable LOW to
t
PDLY
20
ms
RESET and RESET Active
V
CC
Detect to RESET or
t
RPU
t
RISE
= 5
s
250
610
1000
ms
RESET Inactive
V
CC
Slew Rate
t
R
4.25V to 4.75V
0
ns
Unless otherwise stated, 4.5V
V
CC
5.5V and over the operating temperature range of 0
C to +70
C (40
C to +85
C for N/EMA
devices). All voltages are referenced to ground.
Notes: 1. PBRST is internally pulled HIGH to V
CC
through a nominal 40k
resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of V
CC
on power-down until V
CC
falls below 2V. RESET remains within 0.5V of ground on power-down
until V
CC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
TD
). The watchdog circuit cannot be disabled. To avoid a reset, ST must be
strobed.
4
408-432-9100/www.impweb.com
1999 IMP, Inc.
IMP1
IMP1
232LP/LPS
232LP/LPS
Application Information
Supply Voltage Monitor
Reset Signal Polarity and Output Stage Structure
RESET is an active LOW signal. It is developed with an open
drain driver. If a pullup resistor is required, typical values are
10k
to 50k
.
RESET is an active High signal developed by a CMOS push-pull
output stage and is the logical opposite to RESET.
Trip Point Tolerance Selection
With TOL connected to V
CC
, RESET and RESET become active
whenever V
CC
falls below 4.5V. RESET and RESET become active
when V
CC
falls below 4.75V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET and
RESET remain active for a minimum time period of 250ms.
On power-down, once V
CC
falls below the reset threshold RESET
stays LOW and is guaranteed to be 0.4V or less until V
CC
drops
below 1.2V. The active HIGH reset signal is valid down to a V
CC
level of 1.2V also.
Figure 1. Timing Diagram: Power Up
Figure 2. Timing Diagram: Power Down
1232_05.eps
4.75V
V
CCTP
4.25V
V
CC
RESET
RESET
t
R
t
RPU
V
OH
V
OL
Figure 3. Timing Diagram: Pushbutton Reset
V
IH
V
IL
V
OH
V
OL
RESET
RESET
PBRST
t
PDLY
t
PB
t
RST
1232_08.eps
Figure 4. Application Circuit: Pushbutton Reset
1232_06.eps
PBRST
5V
1
V
CC
TD
2
ST
TOL
IMP1232LP/LPS
P
3
4
RESET
GND
8
7
6
5
RESET
RESET
4.75V
V
CCTP
4.25V
V
CC
RESET
RESET
t
F
V
OH
V
OL
t
RPD
1232_04.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is normally pulled HIGH
through an internal 40k
resistor.
When PBRST is held LOW for the minimum time t
PB
, both resets
become active and remain active for approximately a minimum
time period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40k
resistor.
The PBRST can be driven from a TTL or CMOS logic line or short-
ed to ground with a mechanical switch.
e
c
n
a
r
e
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o
T
t
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e
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r
e
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o
T
)
V
(
e
g
a
t
l
o
V
t
n
i
o
P
P
I
R
T
n
i
M
l
a
n
i
m
o
N
x
a
M
V
=
L
O
T
C
C
%
0
1
5
2
.
4
7
3
.
4
9
4
.
4
D
N
G
=
L
O
T
%
5
5
.
4
2
6
.
4
4
7
.
4
s
p
e
.
2
0
t
_
2
3
2
1
1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP1
IMP1
232LP/LPS
232LP/LPS
Application Information
Figure 6. Application Circuit: Watchdog Timer
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
"hung-up". Through the time delay input, TD, three watchdog
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the
strobe input, ST, is not strobed LOW prior to timeout, reset signals
become active. On power-up or after the supply voltage returns to
an in-tolerance condition, the reset signal remains active for
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
ST Pulses as short as 20ns can be detected.
Figure 5. Timing Diagram: Strobe Input
RESET
ST
Valid
Strobe
Valid
Strobe
Invalid
Strobe
t
RST
t
ST
Note: ST is ignored whenever a reset is active.
t
TD
(Min)
t
TD
(Max)
1232_09.eps
A HIGH-to-LOW ST signal transition must be regularly issued
no later than the minimum time-out period defined by the state of
the TD signal. This guarantees the watchdog timer does not
time-out.
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
selected through the TD pin.
1232_07.eps
PBRST
5V
1
10k
V
CC
TD
2
ST
TOL
IMP1232LP/LPS
P
Decoder
3
4
RESET
GND
8
7
6
5
RESET
MREQ
Address
Bus
RESET
l
e
v
e
L
e
g
a
t
l
o
V
D
T
)
s
m
(
d
o
i
r
e
P
t
u
O
-
e
m
i
T
g
o
d
h
c
t
a
W
n
i
M
l
a
n
i
m
o
N
x
a
M
D
N
G
5
.
2
6
0
5
1
0
5
2
g
n
i
t
a
o
l
F
0
5
2
0
1
6
0
0
0
1
V
C
C
0
0
5
0
0
2
1
0
0
0
2
s
p
e
.
3
0
t
_
2
3
2
1
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
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