2002 IMP, Inc. 408-432-9100/www.impweb.com
1
Key Features
N 2.5pF typical disabled output capacitance
N Fast response
N No external V
REF
capacitors required
N 5A supply current in disconnect mode
N 20mA supply current during normal operation
N Logic command disconnects all termination lines
N Diffsense line driver
N Current limit and thermal protection
N Compatible with the pending SPI-2 LVD
specification
N Pin compatible to the UCC5640
Block Diagram
IMP52
IMP52
45/46
45/46
L
L
VD SCSI T
VD SCSI T
er
er
minat
minat
or
or
Ultr
Ultr
a2/3 SCSI
a2/3 SCSI
9 Channels
9 Channels
Eliminat
Eliminat
es Ext
es Ext
er
er
nal V
nal V
REF
REF
Capacit
Capacit
or
or
The IMP5245/5246 ICs are Low Voltage Differential (LVD) terminators
designed to comply with the LVD termination specification in the SPI-2
document. The IMP5245/5246 are designed specifically for LVD appli-
cations. Because the IMP5245/5246 support only LVD, they have lower
output capacitance than multimode terminators.
The IMP5245/5246 deliver the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external
capacitors also mitigates the need for a lengthy capacitor selection
process. The individual high bandwidth drivers also maximize channel
separation and reduces channel-to-channel noise and cross talk. The
high-bandwidth architecture insures ULTRA-2 performance, while pro-
viding a clear migration path to ULTRA-3 and beyond.
When the IMP5245/5246 are enabled, the differential sense (DIFF-
SENSE) pin supplies a voltage between 1.2V and 1.4V. The terminator
DIFFSENSE output is connected to the system DIFFSENSE line. If there
are no single ended or HVD devices attached to the system the LVD
output will be enabled. If the DIFFSENSE line is LOW, indicating a
single ended device, the IMP5245/5246 output will be in a high-
impedance state. If the DIFFSENSE line is HIGH, indicating a high
5245/46_01.eps
DISC
DISC (IMP5246)
1.25V
1.3V
V
CM
V
OS
/2
V
OS
/2
R+
R
DIFFB
DIFFSENSE
OUT
(+)
()
voltage differential device, the IMP5245/5246 output will
also be in a high-impedance state.
The IMP5245/5246 ICs have a TTL compatible disconnect
pin. The IMP5245 is active LOW and the IMP5246 is active
HIGH. During sleep mode, power supply current is
reduced to just 5
A. During sleep mode all outputs are in
a high-impedance state. Also during sleep mode, the
DIFFSENSE function is disabled and is placed in a high-
impedance state.
D
ATA
C
OMMUNICATIONS
2
408-432-9100/www.impweb.com
2002 IMP, Inc.
Ordering Information
Absolute Maximum Ratings
1
Thermal Data
Pin Configuration
IMP52
IMP52
45/46
45/46
IMP5245/46
1
NC
2
1+
3
1
4
2+
V
TERM
9
9+
8
24
23
22
21
5
2
8+
20
6
3+
7
19
7
3
7+
18
8
4+
6
17
9
4
6+
16
10
DIFFB
5
15
11
DIFFSENSE
5+
14
12
GND
DISC
13
5245/46_05.eps
Part Number
Temperature Range
Package
IMP5245CPW
0
C to 70C
24-Pin Plastic TSSOP
IMP5246CPW
0
C to 70C
24-Pin Plastic TSSOP
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to 6.5V
Differential Voltage . . . . . . . . . . . . . . . . . . . . . 0V to 6.5V
Operating Junction Temperature
Plastic (PW Package) . . . . . . . . . . . . . . . . . 150
C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Storage Temperature Range . . . . . . . . . . . . . . 65
C to 150C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300
C
PW Package:
Thermal Resistance Junction-to-Ambient,
JA
. . . . . . 100
C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
JA
).
The
JA
numbers are guidelines for the thermal performance of
the device/pc-board system. No ambient airflow is assumed.
TSSOP Package
2002 IMP, Inc. 408-432-9100/www.impweb.com
3
IMP52
IMP52
45/46
45/46
Electrical Characteristics
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Termpwr Voltage
V
TERM
3.0
5.25
V
Signal Line Voltage
0
5.0
V
Disconnect Input Voltage
0
V
TERM
V
Operating Junction Temperature Range -- IMP5245/5246
0
70
C
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0
C T
A
70C. TermPwr = 3.3V,
DISCONNECT: IMP5245 = LOW, IMP5246 = HIGH. Low duty cycle pulse testing techniques are used which maintains junction and case
temperatures equal to the ambient temperature.
Note:
3. Open circuit failsafe voltage.
Note:
2. Range over which the device is functional.
Parameter
Symbol Conditions
Min
Typ
Max
Units
LVD Terminator Section
TermPwr Supply Current
All term lines = Open
20
25
mA
Power Down Mode
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW
5
10
A
Common Mode Voltage
V
OM
1.125
1.25
1.375
V
Offset Voltage
V
OS
Open circuit between and + (see Note 3)
100
112
125
mV
Differential Terminator
V
OD
= 1V to 1V
100
105
110
Impedance
Common Mode Impedance
0V to 2.5V
100
200
300
Output Capacitance
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW
2.5
pF
Output Leakage
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
V
LINE
= 0 to 4V, T
A
= 25
C
0
2
A
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
V
TERM
= 0V, V
LINE
= 2.7V
1
A
Mode Change Delay
DIFFSENSE = 1.4V to 0V
100
150
ms
DIFFSENSE Section
DIFFSENSE Output Voltage
1.2
1.3
1.4
V
DIFFSENSE Output Source
DIFFSENSE = 0V
5.0
15.0
mA
Current
DIFFSENSE Sink Current
V
IN
= 2.75V
200
A
DIFFSENSE Output Leakage
DISCONNECT: IMP5245 = HIGH, IMP5246 = LOW,
10
A
T
A
= 25
C
DISCONNECT Section
DISCONNECT Threshold
0.8
2.0
V
Input Current
DISCONNECT: IMP5245 = 0V
10
A
DISCONNECT: IMP5246 = 3.3V
10
A
4
408-432-9100/www.impweb.com
2002 IMP, Inc.
IMP52
IMP52
45/46
45/46
Application Information
IMP5245/46
IMP5245/46
Figure 1. Bus Voltage
Figure 2. V
OD
V
(+)
V
(-)
V
CM
V
OD
= V
(-)
- V
(+)
, Logic = 0
NEGATED
0V
100mV
-100mV
Figure 3.
IMP5245
IMP5246
Outputs
DISCONNECT
DISCONNECT
DIFFSENS
Status
Type
Current
L
H
L < 0.5V
Disable
HiZ
2mA
L
H
0.7V to 1.9V
Enable
LVD
21mA
L
H
H > 2.4V
Disable
HiZ
2mA
H
L
X
Disable
HiZ
10
A
Open
Open
X
Disable
HiZ
10
A
Note:
IMP5245 Disconnect logic is compatible with the Unitrode UCC5640.
Table 1. DIFFSENSE/Power Up/Power Down Function Table
IMP52
IMP52
45/46
45/46
Application Information
SCSI
CABLE
HOST
PERIPHERAL
DIFFSENSE
DIFFB
DISC
V
T
IMP5245
DIFFB
DISC
V
T
IMP5245
DIFFB
DISC
V
T
IMP5245
Disconnect
5V
2.2
F
DIFFSENSE
DIFFB
DISC
V
T
IMP5245
DIFFB
DISC
V
T
IMP5245
DIFFB
DISC
V
T
IMP5245
ATN-
ATN+
REQ-
REQ+
DB(0)-
DB(0)+
DB(8)-
DB(8)+
DB(9)-
DB(9)+
DB(15)-
DB(15)+
ATN-
ATN+
REQ-
REQ+
DB(0)-
DB(0)+
DB(8)-
DB(8)+
DB(9)-
DB(9)+
DB(15)-
DB(15)+
Disconnect
2.2
F
Figure 4. Application Schematic
2002
IMP, Inc.
Printed in USA
Publication #: 7003
Revision:
B
Issue Date:
08/12/02
Type:
Preliminary
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Fax: 408-43
2-1085
e-mail: info@impinc.com
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
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