Edition 1999-07
Published by Infineon Technologies AG i. Gr.,
St.-Martin-Strasse 53
D-81541 München

Infineon Technologies AG 1999.

All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech-
nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to
support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other
persons may be endangered.

The C161PI is the successor of the C161RI. Therefore this data sheet also replaces the C161RI
data sheet (see also revision history).

C161PI
Revision History:

1999-07 Preliminary

Previous Versions:

1998-05

(C161RI / Preliminary)

1998-01

(C161RI / Advance Information)

1997-12

(C161RI / Advance Information)

Page

Subjects

---

3 V specification introduced

4, 5, 7

Signal FOUT added

XRAM description added

Unlatched CS description added

Block Diagram corrected

Description of divider chain improved

25, 51, 52

ADC description updated to 10-bit

36, 37

Revised description of Absolute Max. Ratings and Operating Conditions

39, 44

Power supply values improved

45 - 50

Revised description for clock generation including PLL

54 ff.

Standard 25-MHz timing

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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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· High Performance 16-bit CPU with 4-Stage Pipeline

80 ns Instruction Cycle Time at 25 MHz CPU Clock
400 ns Multiplication (16

16 bit), 800 ns Division (32 / 16 bit)

Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area

· 16-Priority-Level Interrupt System with 27 Sources, Sample-Rate down to 40 ns
· 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

· Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp.
· On-Chip Memory Modules

1 KByte On-Chip Internal RAM (IRAM)
2 KBytes On-Chip Extension RAM (XRAM)

· On-Chip Peripheral Modules

4-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8

Two Multi-Functional General Purpose Timer Units with 5 Timers
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
I

C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)

· Up to 8 MBytes External Address Space for Code and Data

Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

Five Programmable Chip-Select Signals

· Idle and Power Down Modes with Flexible Power Management
· Programmable Watchdog Timer and Oscillator Watchdog
· On-Chip Real Time Clock
· Up to 76 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

· Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

· On-Chip Bootstrap Loader
· 100-Pin MQFP / TQFP Package

Data Sheet

1999-07

C166 Family of

C161PI

High-Performance CMOS 16-Bit Microcontrollers

Preliminary
C161PI 16-Bit Microcontroller

&3,

Data Sheet

1999-07

This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PI-
LM and the SAF-C161PI-LF.
For simplicity all versions are referred to by the term C161PI throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

· the derivative itself, i.e. its function set
· the specified temperature range
· the package
· the type of delivery.

For the available ordering codes for the C161PI please refer to the
,,Product Catalog Microcontrollers", which summarizes all available microcontroller
variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

&3,

Data Sheet

1999-07

Introduction

The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS
microcontrollers. It combines high CPU performance (up to 8 million instructions per
second) with high peripheral functionality and enhanced IO-capabilities. The C161PI
derivative is especially suited for cost sensitive applications.

Figure 1

Logic Symbol

C161PI

XTAL2

XTAL1

RSTIN

NMI

RSTOUT

ALE
RD
WR/WRL

PORT0

16 bit

PORT1

16 bit

Port 2

8 bit

Port 3

15 bit

Port 4

7 bit

Port 6

8 bit

Port 5

6 bit

AREF

AGND

&3,

Data Sheet

1999-07

Pin Configuration MQFP Package
(top view)

Figure 2

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

C161PI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

NMI
RSTOUT
RSTIN
V

P1H.7/A15
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
V

P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9

P5.2/AN2
P5.3/AN3

P5.14/T4EUD
P5.15/T2EUD

XTAL1
XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT
P3.4/T3EUD

P3.5/T4IN
P3.6/T3IN
P3.7/T2IN

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/

FOUT

P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
P4.4/A20

P5.

P2.15/

P2.14/

P2.13/

P2.12/

P2.11/

P2.10/

P2.

X1IN

P2.

X0IN

P6.

DA2

P6.6/

CL1

P6.

DA1

P6.

/CS

P6.

/CS

P6.

/CS

P6.

/CS

P6.

/CS

.
5

.
6

READY

ALE

0L.

0H.

&3,

Data Sheet

1999-07

Pin Configuration TQFP Package
(top view)

Figure 3

P5.

P2.15/

P2.14/

P2.13/

P2.12/

P2.11/

P2.10/

P2.

X1IN

P2.

X0IN

P6.

DA2

P6.6/

CL1

P6.

DA1

P6.

/CS

P6.

/CS

P6.

/CS

P6.

/CS

P6.

/CS

NMI

TOUT

TIN

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

C161PI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

P1H.7/A15
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
P1H.1/A9
P1H.0/A8
V

P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11

P5.14/T4EUD
P5.15/T2EUD

XTAL1
XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT
P3.4/T3EUD

P3.5/T4IN
P3.6/T3IN
P3.7/T2IN

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT/

FOUT

P4.0/A16
P4.1/A17

P4.

/A18

P4.

/A19

P4.

/A20

P4.

/A21

P4.

/A22

ADY

ALE

P0L.0/

AD0

P0L.1/

AD1

P0L.2/

AD2

P0L.3/

AD3

P0L.4/

AD4

P0L.5/

AD5

P0L.6/

AD6

P0L.7/

AD7

P0H.0/

AD8

P0H.1/

AD9

P0H.2/

AD10

&3,

Data Sheet

1999-07

Table 1

Pin Definitions and Functions

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

P5.0
P5.1
P5.2
P5.3
P5.14
P5.15

97
98
99
100
1
2

99
100
1
2
3
4

I
I
I
I
I
I

Port 5 is a 6-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as (up to
4) analog input channels for the A/D converter, or they
serve as timer inputs:
AN0
AN1
AN2
AN3
T4EUD

GPT1 Timer T4 Ext. Up/Down Ctrl. Input

T2EUD

GPT1 Timer T5 Ext. Up/Down Ctrl. Input

XTAL1

XTAL2

XTAL1:

Input to the oscillator amplifier and input to
the internal clock generator

XTAL2:

Output of the oscillator amplifier circuit.

To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected. Minimum
and maximum high/low and rise/fall times specified in
the AC Characteristics must be observed.

&3,

Data Sheet

1999-07

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5

P3.6
P3.7

P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

7
8
9
10
11
12

13
14

15
16
17
18
19

20
21

9
10
11
12
13
14

15
16

17
18
19
20
21

22
23

I/O
I/O
I
O
I
I

I
I

I/O
I/O
O
I/O
O
O
I/O
O
O

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into
high-impedance state. Port 3 outputs can be
configured as push/pull or open drain drivers. The input
threshold of Port 3 is selectable (TTL or special). The
following Port 3 pins also serve for alternate functions:
SCL0

I2C Bus Clock Line 0

SDA0

I2C Bus Data Line 0

CAPIN

GPT2 Register CAPREL Capture Input

T3OUT

GPT1 Timer T3 Toggle Latch Output

T3EUD

GPT1 Timer T3 External Up/Down Ctrl.Inp

T4IN

GPT1 Timer T4 Count/Gate/Reload/
Capture Input

T3IN

GPT1 Timer T3 Count/Gate Input

T2IN

GPT1 Timer T2 Count/Gate/Reload/
Capture Input

MRST

SSC Master-Rec. / Slave-Trans. Inp/Outp.

MTSR

SSC Master-Trans. / Slave-Rec. Outp/Inp.

ASC0 Clock/Data Output (Async./Sync.)

ASC0 Data Input (Async.) or I/O (Sync.)

BHE

External Memory High Byte Enable Signal,

WRH

External Memory High Byte Write Strobe

SCLK

SSC Master Clock Outp. / Slave Clock Inp.

CLKOUT

System Clock Output (=CPU Clock)

FOUT

Programmable Frequency Output

Note: Pins P3.0 and P3.1 are open drain outputs only.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6

24
25
26
27
28
29
30

26
27
28
29
30
31
32

O
O
O
O
O
O
O

Port 4 is a 7-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into
high-impedance state. Port 4 outputs can be
configured as push/pull or open drain drivers. The input
threshold of Port 4 is selectable (TTL or special). Port 4
can be used to output the segment address lines:
A16

Least Significant Segment Address Line

A17

Segment Address Line

A18

Segment Address Line

A19

Segment Address Line

A20

Segment Address Line

A21

Segment Address Line

A22

Most Significant Segment Address Line

External Memory Read Strobe. RD is activated for
every external instruction or data read access.

WR/
WRL

External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-
mode this pin is activated for low byte data write
accesses on a 16-bit bus, and for every data write
access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.

READY 33

Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory access
will force the insertion of memory cycle time waitstates
until the pin returns to a low level.
An internal pullup device will hold this pin high when
nothing is driving it.

ALE

Address Latch Enable Output. Can be used for latching
the address into external memory or an address latch
in the multiplexed bus modes.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

External Access Enable pin. A low level at this pin
during and after Reset forces the C161PI to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
"ROMless" versions must have this pin tied to `0'.

PORT0
P0L.0-7

P0H.0-7

38-
45
48-
55

40-
47
50-
57

PORT0 consists of the two 8-bit bidirectional I/O ports
P0L and P0H. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
In case of external bus configurations, PORT0 serves
as the address (A) and address/data (AD) bus in
multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

D0 D7

D0 - D7

P0H.0 P0H.7:

I/O

D8 - D15

Multiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

AD0 AD7

AD0 - AD7

P0H.0 P0H.7:

A8 - A15

AD8 - AD15

PORT1
P1L.0-7

P1H.0-7

56-
63
66-
73

58-
65
68-
75

PORT1 consists of the two 8-bit bidirectional I/O ports
P1L and P1H. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from
a demultiplexed bus mode to a multiplexed bus mode.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

RSTIN

I/O

Reset Input with Schmitt-Trigger characteristics. A low
level at this pin while the oscillator is running resets the
C161PI. An internal pullup resistor permits power-on
reset using only a capacitor connected to

A spike filter suppresses input pulses <10 ns. Input
pulses >100 ns safely pass the filter.
The minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit
BDRSTEN in register SYSCON) the RSTIN line is
internally pulled low for the duration of the internal
reset sequence upon any reset (HW, SW, WDT).
See note below this table.

Note: To let the reset configuration of PORT0 settle

and to let the PLL lock a reset duration of ca.
1 ms is recommended.

RST
OUT

Internal Reset Indication Output. This pin is set to a low
level when the part is executing either a hardware-, a
software- or a watchdog timer reset. RSTOUT remains
low until the EINIT (end of initialization) instruction is
executed.

NMI

Non-Maskable Interrupt Input. A high to low transition
at this pin causes the CPU to vector to the NMI trap
routine. When the PWRDN (power down) instruction is
executed, the NMI pin must be low in order to force the
C161PI to go into power down mode. If NMI is high,
when PWRDN is executed, the part will continue to run
in normal mode.
If not used, pin NMI should be pulled high externally.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7

79
80
81
82
83
84
85
86

81
82
83
84
85
86
87
88

O
O
O
O
O
I/O
I/O
I/O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into
high-impedance state. Port 6 outputs can be
configured as push/pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
CS0

Chip Select 0 Output

CS1

Chip Select 1 Output

CS2

Chip Select 2 Output

CS3

Chip Select 3 Output

CS4

Chip Select 4 Output

SDA1

C Bus Data Line 1

SCL1

C Bus Clock Line 1

SDA2

C Bus Data Line 2

Note: Pins P6.7-5 are open drain outputs only.

P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15

87
88
89
90
91
92
93
94

89
90
91
92
93
94
95
96

I
I
I
I
I
I
I
I

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into
high-impedance state. Port 2 outputs can be
configured as push/pull or open drain drivers. The input
threshold of Port 2 is selectable (TTL or special).
The Port 2 pins also serve for alternate functions:
EX0IN

Fast External Interrupt 0 Input

EX1IN

Fast External Interrupt 1 Input

EX2IN

Fast External Interrupt 2 Input

EX3IN

Fast External Interrupt 3 Input

EX4IN

Fast External Interrupt 4 Input

EX5IN

Fast External Interrupt 5 Input

EX6IN

Fast External Interrupt 6 Input

EX7IN

Fast External Interrupt 7 Input

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

Note: The following behaviour differences must be observed when the bidirectional reset

is active:

· Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

· The reset indication flags always indicate a long hardware reset.
· The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap

loader may be activated when P0L.4 is low.

· Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

· A short hardware reset is extended to the duration of the internal reset sequence.

6, 23,
37,
47,
65, 75

8, 25,
39,
49,
67, 77

Digital Supply Voltage:
+ 5 V or + 3 V during normal operation and idle mode.

2.5 V during power down mode

3, 22,
36,
46,
64, 74

5, 24,
38,
48,
66, 76

Digital Ground.

Table 1

Pin Definitions and Functions (continued)

Symbol Pin

Num.
TQFP

Pin
Num.
MQFP

Input
Outp.

Function

&3,

Data Sheet

1999-07

Functional Description

The architecture of the C161PI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. The
following block diagram gives an overview of the different on-chip components and of the
advanced, high bandwidth internal bus structure of the C161PI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

Figure 4

Block Diagram

(no

internal

ROM)

Instr./Data

3(&

&38 &RUH

Interrupt Bus

Internal

RAM

ÃF7r

ual

Port

Port 2

Port 3

Port 4

Port 1

Data

Watchdog

Port 5

C161RI V0.1

&38

&&RUH

XBUS

(

-
b

i
t

t
a

/ A

r
e

sse

External Instr./Data

USART

ASC

Sync.

Channel

(SPI)

SSC

XTAL

BRG

Peripheral Data

GPT 1

T 3

T 4

T 2

XRAM

2 KByte

GPT 2

T 6

T 5

I²C-Bus

Interface

Interrupt Controller

11 ext. IR

OSC

(input: 16MHz;

prescaler

or direct drive)

External

Bus

(MUX

only) &

XBUS

Control,

CS Logic

(4 CS)

Port

r
t
6

Channel

8-bit

ADC

RTC

Oscillator

(16MHz)

PLL

10-bit

&3,

Data Sheet

1999-07

Memory Organization

The memory space of the C161PI is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.

1 KByte of on-chip Internal RAM (IRAM) is provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
..., RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like external memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the
microcontroller.

&3,

Data Sheet

1999-07

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:

16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which allow to access different resources with different bus
characteristics. These address windows are arranged hierarchically where BUSCON4
overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not
covered by these 4 address windows are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. The C161PI offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).

Access to very slow memories is supported via a particular `Ready' function.

For applications which require less than 8 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4
outputs four, two or no address lines at all. It outputs all 7 address lines, if an address
space of 8 MBytes is used.

&3,

Data Sheet

1999-07

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161PI's instructions can be executed
in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and
rotate instructions are always processed during one machine cycle independent of the
number of bits to be shifted. All multiple-cycle instructions have been optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16

16 bit multiplication

in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-
called `Jump Cache', reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.

Figure 5

CPU Block Diagram

&3,

Data Sheet

1999-07

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C161PI instruction set which includes
the following instruction classes:

Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

&3,

Data Sheet

1999-07

Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C161PI is capable of reacting very fast to the
occurrence of non-deterministic events.

The architecture of the C161PI supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
`stolen' from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C161PI has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the `TRAP' instruction in combination with
an individual trap (interrupt) number.

The following table shows all of the possible C161PI interrupt sources and the
corresponding hardware-related interrupt flags, vectors, vector locations and trap
(interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).

&3,

Data Sheet

1999-07

Table 2

C161PI Interrupt Nodes

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Trap
Number

External Interrupt 0

CC8IR

CC8IE

CC8INT

00'0060

External Interrupt 1

CC9IR

CC9IE

CC9INT

00'0064

External Interrupt 2

CC10IR

CC10IE

CC10INT

00'0068

External Interrupt 3

CC11IR

CC11IE

CC11INT

00'006C

External Interrupt 4

CC12IR

CC12IE

CC12INT

00'0070

External Interrupt 5

CC13IR

CC13IE

CC13INT

00'0074

External Interrupt 6

CC14IR

CC14IE

CC14INT

00'0078

External Interrupt 7

CC15IR

CC15IE

CC15INT

00'007C

GPT1 Timer 2

T2IR

T2IE

T2INT

00'0088

GPT1 Timer 3

T3IR

T3IE

T3INT

00'008C

GPT1 Timer 4

T4IR

T4IE

T4INT

00'0090

GPT2 Timer 5

T5IR

T5IE

T5INT

00'0094

GPT2 Timer 6

T6IR

T6IE

T6INT

00'0098

GPT2 CAPREL
Register

CRIR

CRIE

CRINT

00'009C

A/D Conversion
Complete

ADCIR

ADCIE

ADCINT

00'00A0

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00'00A4

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00'00A8

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00'011C

ASC0 Receive

S0RIR

S0RIE

S0RINT

00'00AC

ASC0 Error

S0EIR

S0EIE

S0EINT

00'00B0

SSC Transmit

SCTIR

SCTIE

SCTINT

00'00B4

SSC Receive

SCRIR

SCRIE

SCRINT

00'00B8

SSC Error

SCEIR

SCEIE

SCEINT

00'00BC

C Data Transfer

Event

XP0IR

XP0IE

XP0INT

00'0100

C Protocol Event

XP1IR

XP1IE

XP1INT

00'0104

X-Peripheral Node 2

XP2IR

XP2IE

XP2INT

00'0108

PLL Unlock / RTC

XP3IR

XP3IE

XP3INT

00'010C

&3,

Data Sheet

1999-07

The C161PI also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise
during run-time:

Table 3

Hardware Trap Summary

Exception Condition

Trap
Flag

Trap
Vector

Vector
Location

Trap
Number

Trap
Prio

Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow

RESET
RESET
RESET

00'0000

III
III
III

Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00'0008

00'0010

00'0018

II
II
II

Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access

UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS

BTRAP
BTRAP
BTRAP
BTRAP
BTRAP

00'0028

I
I
I
I
I

Reserved

[2C

] [0B

]

Software Traps:
TRAP Instruction

Any
[00'0000

00'01FC

]

in steps
of 4

Any
[00

]

Current
CPU
Priority

&3,

Data Sheet

1999-07

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the `gate' level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate eg. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on a port pin (T3OUT) eg. for time
out monitoring of external hardware components, or may be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to
a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of
T2 or T4 triggered either by an external signal or by a selectable state transition of its
toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on
opposite state transitions of T3OTL with the low and high times of a PWM signal, this
signal can be constantly generated without software intervention.

&3,

Data Sheet

1999-07

Figure 6

Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock via a programmable prescaler. The count direction (up/down) for each timer is
programmable by software. Concatenation of the timers is supported via the output
toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/
underflow.

Mode

Control

: 1

CPU

: 1

CPU

Mode

Control

GPT1 Timer T2

Reload

Capture

: 1

CPU

Mode

Control

GPT1 Timer T4

Reload

Capture

GPT1 Timer T3

T3OTL

U/D

T2EUD

T2IN

T3IN

T3EUD

T4IN

T4EUD

T3OUT

Toggle FF

U/D

Interrupt
Request

Other
Timers

MCT02141

&3,

Data Sheet

1999-07

The state of this latch may be used to clock timer T5. The overflows/underflows of timer
T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL
register may capture the contents of timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the
capture procedure. This allows absolute time differences to be measured or pulse
multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.

Figure 7

Block Diagram of GPT2

MUX

: 1

CPU

Mode

Control

GPT2 Timer T5

: 1

CPU

Mode

Control

GPT2 Timer T6

GPT2 CAPREL

T6OTL

CAPIN

T6OUT

U/D

Interrupt
Request

Other
Timers

Clear

Capture

CT3

Mcb03999C.vsd

&3,

Data Sheet

1999-07

Real Time Clock

The Real Time Clock (RTC) module of the C161PI consists of a chain of 3 divider blocks,
a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible
via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip
oscillator frequency divided by 32 via a separate clock driver (

RTC

OSC

/ 32) and is

therefore independent from the selected clock generation mode of the C161PI. All timers
count up.

The RTC module can be used for different purposes:

· System clock to determine the current time and date
· Cyclic time based interrupt
· 48-bit timer for long term measurements

Figure 8

RTC Block Diagram

Note: The registers associated with the RTC are not effected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

RTCL

T14

T14REL

8:1

RTC

Reload

Interrupt
Request

&3,

Data Sheet

1999-07

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 4 multiplexed input channels
and a sample and hold circuit has been integrated on-chip. It uses the method of
successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.

For applications which require less than 4 analog input channels, the remaining channel
inputs can be used as digital input port pins.

The A/D converter of the C161PI supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into
a running sequence without disturbing this sequence. This is called Channel Injection
Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via registers
P5DIDIS (Port 5 Digital Input Disable).

&3,

Data Sheet

1999-07

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 780 KBaud and
half-duplex synchronous communication at up to 3.1 MBaud @ 25 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 Mbaud @
25 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral
components. A dedicated baud rate generator allows to set up all standard baud rates
without oscillator tuning. For transmission, reception and error handling 3 separate
interrupt vectors are provided.
The SSC transmits or receives characters of 2...16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.

&3,

Data Sheet

1999-07

C Module

The integrated I

C Bus Module handles the transmission and reception of frames over

the two-line I

C bus in accordance with the I

C Bus specification. The on-chip I

C Module

can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave
mode, in master mode or in multi-master mode.

Several physical interfaces (port pins) can be established under software control. Data
can be transferred at speeds up to 400 Kbit/sec.

Two interrupt nodes dedicated to the I

C module allow efficient interrupt service and also

support operation via PEC transfers.

Note: The port pins associated with the I

C interfaces feature open drain drivers only, as

required by the I

C specification.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip's start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2
or by 128. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

&3,

Data Sheet

1999-07

Parallel Ports

The C161PI provides up to 76 IO lines which are organized into six input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three IO ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. The other IO ports
operate in push/pull mode, except for the I²C interface pins which are open drain pins
only. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE and the system clock output CLKOUT (or the programmable frequency
output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

Port 6 provides the optional chip select signals and interface lines for the I²C module.

The edge characteristics (transition time) of the C161PI's port drivers can be selected
via the Port Driver Control Register (PDCR).

&3,

Data Sheet

1999-07

Instruction Set Summary

The table below lists the instructions of the C161PI in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the "C166 Family Instruction Set Manual".

This document also provides a detailled description of each instruction.

Table 4

Instruction Set Summary

Mnemonic

Description

Bytes

ADD(B)

Add word (byte) operands

2 / 4

ADDC(B)

Add word (byte) operands with Carry

2 / 4

SUB(B)

Subtract word (byte) operands

2 / 4

SUBC(B)

Subtract word (byte) operands with Carry

2 / 4

MUL(U)

(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

DIV(U)

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

DIVL(U)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

CPL(B)

Complement direct word (byte) GPR

NEG(B)

Negate direct word (byte) GPR

AND(B)

Bitwise AND, (word/byte operands)

2 / 4

OR(B)

Bitwise OR, (word/byte operands)

2 / 4

XOR(B)

Bitwise XOR, (word/byte operands)

2 / 4

BCLR

Clear direct bit

BSET

Set direct bit

BMOV(N)

Move (negated) direct bit to direct bit

BAND, BOR,
BXOR

AND/OR/XOR direct bit with direct bit

BCMP

Compare direct bit to direct bit

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data

CMP(B)

Compare word (byte) operands

2 / 4

CMPD1/2

Compare word data to GPR and decrement GPR by 1/2

2 / 4

CMPI1/2

Compare word data to GPR and increment GPR by 1/2

2 / 4

PRIOR

Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR

SHL / SHR

Shift left/right direct word GPR

ROL / ROR

Rotate left/right direct word GPR

ASHR

Arithmetic (sign bit) shift right direct word GPR

&3,

Data Sheet

1999-07

MOV(B)

Move word (byte) data

2 / 4

MOVBS

Move byte operand to word operand with sign extension

2 / 4

MOVBZ

Move byte operand to word operand. with zero extension 2 / 4

JMPA, JMPI,
JMPR

Jump absolute/indirect/relative if condition is met

JMPS

Jump absolute to a code segment

J(N)B

Jump relative if direct bit is (not) set

JBC

Jump relative and clear bit if direct bit is set

JNBS

Jump relative and set bit if direct bit is not set

CALLA, CALLI,
CALLR

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

Call absolute subroutine in any code segment

PCALL

Push direct word register onto system stack and call
absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

PUSH, POP

Push/pop direct word register onto/from system stack

SCXT

Push direct word register onto system stack und update
register with word operand

RET

Return from intra-segment subroutine

RETS

Return from inter-segment subroutine

RETP

Return from intra-segment subroutine and pop direct
word register from system stack

RETI

Return from interrupt service subroutine

SRST

Software Reset

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode (supposes NMI-pin being low)

SRVWDT

Service Watchdog Timer

DISWDT

Disable Watchdog Timer

EINIT

Signify End-of-Initialization on RSTOUT-pin

ATOMIC

Begin ATOMIC sequence

EXTR

Begin EXTended Register sequence

EXTP(R)

Begin EXTended Page (and Register) sequence

2 / 4

EXTS(R)

Begin EXTended Segment (and Register) sequence

2 / 4

NOP

Null operation

Table 4

Instruction Set Summary (continued)

Mnemonic

Description

Bytes

&3,

Data Sheet

1999-07

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161PI in alphabetical
order.
Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical
Address". Registers within on-chip X-Peripherals (I²C) are marked with the letter "X" in
column "Physical Address".

An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 5

C161PI Registers, Ordered by Name

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

ADCIC

b FF98

A/D Converter End of Conversion
Interrupt Control Register

0000

ADCON

b FFA0

A/D Converter Control Register

0000

ADDAT

FEA0

A/D Converter Result Register

0000

ADDAT2

F0A0

E 50

A/D Converter 2 Result Register

0000

ADDRSEL1

FE18

Address Select Register 1

0000

ADDRSEL2

FE1A

Address Select Register 2

0000

ADDRSEL3

FE1C

Address Select Register 3

0000

ADDRSEL4

FE1E

Address Select Register 4

0000

ADEIC

b FF9A

A/D Converter Overrun Error Interrupt
Control Register

0000

BUSCON0 b FF0C

Bus Configuration Register 0

0000

BUSCON1 b FF14

Bus Configuration Register 1

0000

BUSCON2 b FF16

Bus Configuration Register 2

0000

BUSCON3 b FF18

Bus Configuration Register 3

0000

BUSCON4 b FF1A

Bus Configuration Register 4

0000

CAPREL

FE4A

GPT2 Capture/Reload Register

0000

CC8IC

b FF88

External Interrupt 0 Control Register

0000

CC9IC

b FF8A

External Interrupt 1 Control Register

0000

CC10IC

b FF8C

External Interrupt 2 Control Register

0000

CC11IC

b FF8E

External Interrupt 3 Control Register

0000

&3,

Data Sheet

1999-07

CC12IC

b FF90

External Interrupt 4 Control Register

0000

CC13IC

b FF92

External Interrupt 5 Control Register

0000

CC14IC

b FF94

External Interrupt 6 Control Register

0000

CC15IC

b FF96

External Interrupt 7 Control Register

0000

FE10

CPU Context Pointer Register

FC00

CRIC

b FF6A

GPT2 CAPREL Interrupt Ctrl. Register

0000

CSP

FE08

CPU Code Segment Pointer Register
(8 bits, not directly writeable)

0000

DP0L

b F100

E 80

P0L Direction Control Register

DP0H

b F102

E 81

P0H Direction Control Register

DP1L

b F104

E 82

P1L Direction Control Register

DP1H

b F106

E 83

P1H Direction Control Register

DP2

b FFC2

Port 2 Direction Control Register

0000

DP3

b FFC6

Port 3 Direction Control Register

0000

DP4

b FFCA

Port 4 Direction Control Register

DP6

b FFCE

Port 6 Direction Control Register

DPP0

FE00

CPU Data Page Pointer 0 Register (10
bits)

0000

DPP1

FE02

CPU Data Page Pointer 1 Reg. (10 bits)

0001

DPP2

FE04

CPU Data Page Pointer 2 Reg. (10 bits)

0002

DPP3

FE06

CPU Data Page Pointer 3 Reg. (10 bits)

0003

EXICON

b F1C0

E E0

External Interrupt Control Register

0000

ICADR

ED06

X ---

I²C Address Register

0XXX

ICCFG

ED00

X ---

I²C Configuration Register

XX00

ICCON

ED02

X ---

I²C Control Register

0000

ICRTB

ED08

X ---

I²C Receive/Transmit Buffer

ICST

ED04

X ---

I²C Status Register

0000

IDCHIP

F07C

E 3E

Identifier

09XX

IDMANUF

F07E

E 3F

Identifier

1820

IDMEM

F07A

E 3D

Identifier

0000

Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

&3,

Data Sheet

1999-07

IDPROG

F078

E 3C

Identifier

0000

ISNC

b F1DE

E EF

Interrupt Subnode Control Register

0000

MDC

b FF0E

CPU Multiply Divide Control Register

0000

MDH

FE0C

CPU Multiply Divide Reg. High Word

0000

MDL

FE0E

CPU Multiply Divide Reg. Low Word

0000

ODP2

b F1C2

E E1

Port 2 Open Drain Control Register

0000

ODP3

b F1C6

E E3

Port 3 Open Drain Control Register

0000

ODP6

b F1CE

E E7

Port 6 Open Drain Control Register

ONES

b FF1E

Constant Value 1's Register (read only)

FFFF

P0L

b FF00

Port 0 Low Reg. (Lower half of PORT0)

P0H

b FF02

Port 0 High Reg. (Upper half of PORT0)

P1L

b FF04

Port 1 Low Reg. (Lower half of PORT1)

P1H

b FF06

Port 1 High Reg. (Upper half of PORT1)

b FFC0

Port 2 Register

0000

b FFC4

Port 3 Register

0000

b FFC8

Port 4 Register (7 bits)

b FFA2

Port 5 Register (read only)

XXXX

P5DIDIS

b FFA4

Port 5 Digital Input Disable Register

0000

b FFCC

Port 6 Register (8 bits)

PECC0

FEC0

PEC Channel 0 Control Register

0000

PECC1

FEC2

PEC Channel 1 Control Register

0000

PECC2

FEC4

PEC Channel 2 Control Register

0000

PECC3

FEC6

PEC Channel 3 Control Register

0000

PECC4

FEC8

PEC Channel 4 Control Register

0000

PECC5

FECA

PEC Channel 5 Control Register

0000

PECC6

FECC

PEC Channel 6 Control Register

0000

PECC7

FECE

PEC Channel 7 Control Register

0000

PSW

b FF10

CPU Program Status Word

0000

PDCR

F0AA

E 55

Pin Driver Control Register

0000

RP0H

b F108

E 84

System Startup Config. Reg. (Rd. only)

Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

&3,

Data Sheet

1999-07

RTCH

F0D6

E 6B

RTC High Register

RTCL

F0D4

E 6A

RTC Low Register

S0BG

FEB4

Serial Channel 0 Baud Rate Generator
Reload Register

0000

S0CON

b FFB0

Serial Channel 0 Control Register

0000

S0EIC

b FF70

Serial Channel 0 Error Interrupt Control
Register

0000

S0RBUF

FEB2

Serial Channel 0 Receive Buffer Reg.
(read only)

XXXX

S0RIC

b FF6E

Serial Channel 0 Receive Interrupt
Control Register

0000

S0TBIC

b F19C

E CE

Serial Channel 0 Transmit Buffer
Interrupt Control Register

0000

S0TBUF

FEB0

Serial Channel 0 Transmit Buffer Reg.
(write only)

0000

S0TIC

b FF6C

Serial Channel 0 Transmit Interrupt
Control Register

0000

FE12

CPU System Stack Pointer Register

FC00

SSCBR

F0B4

E 5A

SSC Baudrate Register

0000

SSCCON

b FFB2

SSC Control Register

0000

SSCEIC

b FF76

SSC Error Interrupt Control Register

0000

SSCRB

F0B2

E 59

SSC Receive Buffer

XXXX

SSCRIC

b FF74

SSC Receive Interrupt Control Register

0000

SSCTB

F0B0

E 58

SSC Transmit Buffer

0000

SSCTIC

b FF72

SSC Transmit Interrupt Control Register

0000

STKOV

FE14

CPU Stack Overflow Pointer Register

FA00

STKUN

FE16

CPU Stack Underflow Pointer Register

FC00

SYSCON

FF12

CPU System Configuration Register

0xx0

SYSCON2 b F1D0

E E8

CPU System Configuration Register 2

0000

SYSCON3 b F1D4

E EA

CPU System Configuration Register 3

0000

T14

F0D2

E 69

RTC Timer 14 Register

Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

&3,

Data Sheet

1999-07

T14REL

F0D0

E 68

RTC Timer 14 Reload Register

FE40

GPT1 Timer 2 Register

0000

T2CON

b FF40

GPT1 Timer 2 Control Register

0000

T2IC

b FF60

GPT1 Timer 2 Interrupt Control Register

0000

FE42

GPT1 Timer 3 Register

0000

T3CON

b FF42

GPT1 Timer 3 Control Register

0000

T3IC

b FF62

GPT1 Timer 3 Interrupt Control Register

0000

FE44

GPT1 Timer 4 Register

0000

T4CON

b FF44

GPT1 Timer 4 Control Register

0000

T4IC

b FF64

GPT1 Timer 4 Interrupt Control Register

0000

FE46

GPT2 Timer 5 Register

0000

T5CON

b FF46

GPT2 Timer 5 Control Register

0000

T5IC

b FF66

GPT2 Timer 5 Interrupt Control Register

0000

FE48

GPT2 Timer 6 Register

0000

T6CON

b FF48

GPT2 Timer 6 Control Register

0000

T6IC

b FF68

GPT2 Timer 6 Interrupt Control Register

0000

TFR

b FFAC

Trap Flag Register

0000

WDT

FEAE

Watchdog Timer Register (read only)

0000

WDTCON

FFAE

Watchdog Timer Control Register

00xx

XP0IC

b F186

E C3

I²C Data Interrupt Control Register

0000

XP1IC

b F18E

E C7

I²C Protocol Interrupt Control Register

0000

XP2IC

b F196

E CB

X-Peripheral 2 Interrupt Control Register

0000

XP3IC

b F19E

E CF

RTC Interrupt Control Register

0000

ZEROS

b FF1C

Constant Value 0's Register (read only)

0000

1) The system configuration is selected during reset.

2) The reset value depends on the indicated reset source.

Table 5

C161PI Registers, Ordered by Name (continued)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

&3,

Data Sheet

1999-07

Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (

) the

voltage on

pins with respect to ground (

) must not exceed the values

defined by the absolute maximum ratings.

Table 6

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Storage temperature

-65

150

°C

Voltage on

pins with

respect to ground (

)

-0.5

6.5

Voltage on any pin with
respect to ground (

)

-0.5

+0.5

Input current on any pin
during overload condition

-10

Absolute sum of all input
currents during overload
condition

|100|

Power dissipation

DISS

1.5

&3,

Data Sheet

1999-07

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation of the C161PI. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.

Table 7

Operating Condition Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Standard
digital supply voltage

4.5

5.5

Active mode,

CPUmax

= 25 MHz

2.5

1) Output voltages and output currents will be reduced when

leaves the range defined for active mode.

5.5

PowerDown mode

Reduced
digital supply voltage

3.0

3.6

Active mode,

CPUmax

= 20 MHz

2.5

3.6

PowerDown mode

Digital ground voltage

Reference voltage

Overload current

Per pin

2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e.

+0.5V or

-0.5V). The absolute sum of input overload

currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.

3) Not 100% tested, guaranteed by design characterization.

Absolute sum of overload
currents

External Load
Capacitance

100

Pin drivers in
fast edge mode
(PDCR.BIPEC =
'0')

Pin drivers in
reduced edge
mode
(PDCR.BIPEC =
'1')

Ambient temperature

°C

SAB-C161PI...

-40

°C

SAF-C161PI...

-40

125

°C

SAK-C161PI...

&3,

Data Sheet

1999-07

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161PI
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column "Symbol":

CC (Controller Characteristics):
The logic of the C161PI will provide signals with the respective timing characteristics.

SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C161PI.

DC Characteristics (Standard Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7

IL1

0.5

0.3

Input low voltage
(TTL)

0.5

0.2

0.1

Input low voltage
(Special Threshold)

ILS

0.5

2.0

Input high voltage RSTIN

IH1

0.6

0.5

Input high voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7

IH2

0.7

0.5

Input high voltage
(TTL)

0.2

+ 0.9

0.5

Input high voltage
(Special Threshold)

IHS

0.8

- 0.2

0.5

Input Hysteresis
(Special Threshold)

HYS

400

Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)

0.45

= 2.4 mA

Output low voltage
(P3.0, P3.1, P6.5, P6.6, P6.7)

OL2

0.4

OL2

= 3 mA

&3,

Data Sheet

1999-07

Output low voltage
(all other outputs)

OL1

0.45

= 1.6 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)

2.4

= -2.4 mA

0.9

= -0.5 mA

Output high voltage

(all other outputs)

OH1

2.4

= -1.6 mA

0.9

= -0.5 mA

Input leakage current (Port 5)

OZ1

200

0.45V <

Input leakage current (all other)

OZ2

500

0.45V <

RSTIN inactive current

RSTH

-10

IH1

RSTIN active current

RSTL

-100

Read/Write inactive current

RWH

-40

OUT

= 2.4 V

Read/Write active current

RWL

-500

OUT

OLmax

ALE inactive current

ALEL

OUT

OLmax

ALE active current

ALEH

500

OUT

= 2.4 V

Port 6 inactive current

P6H

-40

OUT

= 2.4 V

Port 6 active current

P6L

-500

OUT

OL1max

PORT0 configuration current

P0H

-10

IHmin

P0L

-100

ILmax

XTAL1 input current

0 V <

Pin capacitance

(digital inputs/outputs)

= 1 MHz

= 25 °C

Power supply current (5V active)
with all peripherals active

DD5

1 +
2*

CPU

RSTIN =

IL2

CPU

in [MHz]

Idle mode supply current (5V)
with all peripherals active

IDX5

1 +
0.8*

CPU

RSTIN =

IH1

CPU

in [MHz]

Idle mode supply current (5V)
with all peripherals deactivated,
PLL off, SDD factor = 32

IDO5

500 +
50*

OSC

RSTIN =

IH1

OSC

in [MHz]

DC Characteristics (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

&3,

Data Sheet

1999-07

Power-down mode supply
current (5V) with RTC running

PDR5

200 +
25*

OSC

DDmax

OSC

in [MHz]

Power-down mode supply
current (5V) with RTC disabled

PDO5

DDmax

1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 K

3) The maximum current may be drawn while the respective signal line remains inactive.

4) The minimum current must be drawn in order to drive the respective signal line active.

5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are

only affected, if they are used (configured) for CS output and the open drain function is not enabled.

6) Not 100% tested, guaranteed by design characterization.

7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at

DDmax

and maximum CPU clock with all outputs disconnected and all inputs

The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. I

PDRmax

For lower oscillator frequencies the respective supply current can be reduced accordingly.

8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is

influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry
and may change in case of a not optimized external oscillator circuitry.

9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

DC Characteristics (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

&3,

Data Sheet

1999-07

DC Characteristics (Reduced Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7

IL1

0.5

0.3

Input low voltage
(TTL)

0.5

0.8

Input low voltage
(Special Threshold)

ILS

0.5

1.3

Input high voltage RSTIN

IH1

0.6

0.5

Input high voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7

IH2

0.7

0.5

Input high voltage
(TTL)

1.8

0.5

Input high voltage
(Special Threshold)

IHS

0.8

- 0.2

0.5

Input Hysteresis
(Special Threshold)

HYS

250

Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)

0.45

= 1.6 mA

Output low voltage
P3.0, P3.1, P6.5, P6.6, P6.7

OL2

0.4

OL2

= 1.6 mA

Output low voltage
(all other outputs)

OL1

0.45

= 1.0 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)

CC 0.9

= -0.5 mA

Output high voltage

(all other outputs)

OH1

CC 0.9

= -0.25 mA

Input leakage current (Port 5)

OZ1

200

0.45V <

Input leakage current (all other)

OZ2

500

0.45V <

RSTIN inactive current

RSTH

-10

IH1

&3,

Data Sheet

1999-07

RSTIN active current

RSTL

-100

Read/Write inactive current

RWH

-10

OUT

= 2.4 V

Read/Write active current

RWL

-500

OUT

OLmax

ALE inactive current

ALEL

OUT

OLmax

ALE active current

ALEH

500

OUT

= 2.4 V

Port 6 inactive current

P6H

-10

OUT

= 2.4 V

Port 6 active current

P6L

-500

OUT

OL1max

PORT0 configuration current

P0H

-5

IHmin

P0L

-100

ILmax

XTAL1 input current

0 V <

Pin capacitance

(digital inputs/outputs)

= 1 MHz

= 25 °C

Power supply current (3V active)
with all peripherals active

DD3

1 +
1.1*

CPU

RSTIN =

IL2

CPU

in [MHz]

Idle mode supply current (3V)
with all peripherals active

IDX3

1 +
0.5*

CPU

RSTIN =

IH1

CPU

in [MHz]

Idle mode supply current (3V)
with all peripherals deactivated,
PLL off, SDD factor = 32

IDO3

300 +
30*

OSC

RSTIN =

IH1

OSC

in [MHz]

Power-down mode supply
current (3V) with RTC running

PDR3

100 +
10*

OSC

DDmax

OSC

in [MHz]

Power-down mode supply
current (3V) with RTC disabled

PDO3

DDmax

1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 K

3) The maximum current may be drawn while the respective signal line remains inactive.

4) The minimum current must be drawn in order to drive the respective signal line active.

5) This specification is only valid during Reset, or during Hold- or Adapt-mode. During Hold mode Port 6 pins are

only affected, if they are used (configured) for CS output and the open drain function is not enabled.

6) Not 100% tested, guaranteed by design characterization.

DC Characteristics (continued) (Reduced Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

&3,

Data Sheet

1999-07

Figure 9

Idle and Power Down Supply Current as a Function of Oscillator

Frequency

7) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at

DDmax

and maximum CPU clock with all outputs disconnected and all inputs

The oscillator also contributes to the total supply current. The given values refer to the worst case, ie. I

PDRmax

For lower oscillator frequencies the respective supply current can be reduced accordingly.

8) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is

influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry
and may change in case of a not optimized external oscillator circuitry.

9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

I [

µA

]

OSC

[MHz]

3'5PD[

3'2PD[

1500

1250

1000

750

500

250

,'2PD[

3'5PD[

&3,

Data Sheet

1999-07

AC Characteristics
Definition of Internal Timing

The internal operation of the C161PI is controlled by the internal CPU clock f

CPU

. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.

The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called "TCL" (see figure below).

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock signal

CPU

can be generated from the oscillator clock signal

OSC

via

different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate

CPU

. This influence must

be regarded when calculating the timings for the C161PI.

Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.

The used mechanism to generate the CPU clock is selected during reset via the logic
levels on pins P0.15-13 (P0H.7-5).

The table below associates the combinations of these three bits with the respective clock
generation mode.

TCL TCL

&38

26&

&38

26&

3KDVH /RFNHG /RRS 2SHUDWLRQ

'LUHFW &ORFN 'ULYH

TCL

&38

26&

3UHVFDOHU 2SHUDWLRQ

&3,

Data Sheet

1999-07

Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal 001

during reset the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of

CPU

is half the frequency of

OSC

and the high and low time of

CPU

(i.e.

the duration of an individual TCL) is defined by the period of the input clock

OSC

The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of

OSC

for any TCL.

Phase Locked Loop

For all combinations of pins P0.15-13 (P0H.7-5) except for 001

and 011

the on-chip

phase locked loop is enabled and provides the CPU clock (see table above). The PLL
multiplies the input frequency by the factor F which is selected via the combination of
pins P0.15-13 (i.e.

CPU

OSC

* F). With every F'th transition of

OSC

the PLL circuit

synchronizes the CPU clock to the input clock. This synchronization is done smoothly,
i.e. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of

CPU

is constantly adjusted so

it is locked to

OSC

. The slight variation causes a jitter of

CPU

which also effects the

duration of individual TCLs.

Table 8

C161PI Clock Generation Modes

P0.15-13
(P0H.7-5)

CPU Frequency

CPU

OSC

* F

External Clock
Input Range

Notes

1 1 1

OSC

* 4

2.5 to 6.25 MHz

Default configuration

1 1 0

OSC

* 3

3.33 to 8.33 MHz

1 0 1

OSC

* 2

5 to 12.5 MHz

1 0 0

OSC

* 5

2 to 5 MHz

0 1 1

OSC

* 1

1 to 25 MHz

Direct drive

0 1 0

OSC

* 1.5

6.66 to 16.6 MHz

0 0 1

OSC

/ 2

2 to 50 MHz

CPU clock via prescaler

0 0 0

OSC

* 2.5

4 to 10 MHz

1) The external clock input range refers to a CPU clock range of 10...25 MHz.

2) The maximum frequency depends on the duty cycle of the external clock signal.

&3,

Data Sheet

1999-07

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and figure below).
For a period of

* TCL the minimum value is computed using the corresponding

deviation D

(

* TCL)

min

* TCL

NOM

- D

[ns] =

(13.3 +

*6.3) /

CPU

[MHz],

where

= number of consecutive TCLs

and 1

40.

So for a period of 3 TCLs @ 25 MHz (i.e.

= 3): D

= (13.3 +

* 6.3) / 25 = 1.288 ns,

and (3TCL)

min

= 3TCL

NOM

- 1.288 ns = 58.7 ns (@

CPU

= 25 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.

Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).

Figure 12

Approximated Maximum Accumulated PLL Jitter

This approximated formula is valid for
1

40 and 10MHz

CPU

25MHz.

26.5

Max.jitter D

[ns]

20 MHz

25 MHz

16 MHz

10 MHz

&3,

Data Sheet

1999-07

Direct Drive

When pins P0.15-13 (P0H.7-5) equal 011

during reset the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of

CPU

directly follows the frequency of

OSC

so the high and low time of

CPU

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

OSC

The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:

TCL

min

= 1/

OSC

* DC

min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of

OSC

is compensated

so the duration of 2TCL is always 1/

OSC

. The minimum value TCL

min

therefore has to be

used only once for timings that require an odd number of TCLs (1,3,...). Timings that
require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/

OSC

Note: The address float timings in Multiplexed bus mode (

and

) use the maximum

duration of TCL (TCL

max

= 1/

OSC

* DC

max

) instead of TCL

min

&3,

Data Sheet

1999-07

AC Characteristics

External Clock Drive XTAL1 (Standard Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

max.

min.

max.

min.

max.

Oscillator period

OSC

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

500

High time

2) The clock input signal must reach the defined levels

and

IH2

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (

CPU

) in

direct drive mode depends on the duty cycle of the clock input signal.

Low time

Rise time

Fall time

External Clock Drive XTAL1 (Reduced Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

max.

min.

max.

min.

max.

Oscillator period

OSC

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation

mode. Please see respective table above.

500

High time

2) The clock input signal must reach the defined levels

and

IH2

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (

CPU

) in

direct drive mode depends on the duty cycle of the clock input signal.

Low time

Rise time

Fall time

&3,

Data Sheet

1999-07

A/D Converter Characteristics
(Operating Conditions apply)
4.0V (2.6V)

AREF

+ 0.1V (Note the influence on TUE.)

- 0.1V

AGND

+ 0.2V

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Analog input voltage range

AIN

AGND

AREF

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in these

cases will be X000

or X3FF

, respectively.

Basic clock frequency

0.5

6.25

MHz

2) The limit values for

must not be exceeded when selecting the CPU frequency and the ADCTC setting.

Conversion time

CPU

= 1 /

CPU

3) This parameter includes the sample time

, the time for determining the digital result and the time to load the

result register with the conversion result.
Values for the basic clock

depend on the conversion time programming.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

Total unadjusted error

TUE CC

4) TUE is tested at

AREF

=5.0V (3.3V),

AGND

=0V,

=4.9V (3.2V). It is guaranteed by design for all other

voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see

specification) occurs on maximum 2 not

selected analog input pins and the absolute sum of input overload currents on all analog input pins does not
exceed 10 mA.
During the reset calibration sequence the maximum TUE may be

4 LSB (

8 LSB @ 3V).

LSB

AREF

4.0 V

5) This case is not applicable for the reduced supply voltage range.

LSB

AREF

2.6 V

Internal resistance of
reference voltage source

AREF

/ 60

- 0.25

in [ns]

6) 7)

6) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion timing.

7) Not 100% tested, guaranteed by design.

Internal resistance of analog
source

ASRC

/ 450

- 0.25

in [ns]

7) 8)

8) During the sample time the input capacitance

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time

depend on programming and can be taken from the table below.

ADC input capacitance

AIN

&3,

Data Sheet

1999-07

Sample time and conversion time of the C161PI's A/D Converter are programmable. The
table below should be used to calculate the above timings.
The limit values for

must not be exceeded when selecting ADCTC.

Converter Timing Example:

Assumptions:

CPU

= 25 MHz (i.e.

CPU

= 40 ns), ADCTC = '00', ADSTC = '00'.

Basic clock

CPU

/ 4 = 6.25 MHz, i.e.

= 160 ns.

Sample time

* 8 = 1280 ns.

Conversion time

+ 40

+ 2

CPU

= (1280 + 6400 + 80) ns = 7.8

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.

Table 9

A/D Converter Computation Table

ADCON.15|14
(ADCTC)

A/D Converter
Basic clock

ADCON.13|12
(ADSTC)

Sample time

CPU

/ 4

* 8

CPU

/ 2

* 16

CPU

/ 16

* 32

CPU

/ 8

* 64

Table 10

Memory Cycle Variables

Description

Symbol

Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time Waitstates

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

&3,

Data Sheet

1999-07

Testing Waveforms

Figure 14

Input Output Waveforms

Figure 15

Float Waveforms

AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'.
Timing measurements are made at

min for a logic '1' and

max for a logic '0'.

2.4 V

0.45 V

Test Points

1.8 V

0.8 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded

level occurs (

= 20 mA).

&3,

Data Sheet

1999-07

AC Characteristics

Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

TCL - 10
+

Address setup to ALE

4 +

TCL - 16
+

Address hold after ALE

10 +

TCL - 10
+

ALE falling edge to RD,
WR (with RW-delay)

10 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

Address float after RD,
WR (with RW-delay)

Address float after RD,
WR (no RW-delay)

TCL + 6

RD, WR low time
(with RW-delay)

30 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

50 +

3TCL-
10+

RD to valid data in
(with RW-delay)

20 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

40 +

3TCL - 20
+

ALE low to valid data in

40 +

3TCL - 20
+

Address to valid data in

50 + 2

4TCL - 30
+ 2

Data hold after RD
rising edge

Data float after RD

26 +

2TCL - 14
+

&3,

Data Sheet

1999-07

Data valid to WR

20 +

2TCL - 20
+

Data hold after WR

26 +

2TCL - 14
+

ALE rising edge after RD,
WR

26 +

2TCL - 14
+

Address hold after RD,
WR

26 +

2TCL - 14
+

ALE falling edge to CS

-4 -

10 -

-4 -

10 -

CS low to Valid Data In

40
+

+ 2

3TCL - 20
+

+ 2

CS hold after RD, WR

46 +

3TCL - 14
+

ALE fall. edge to RdCS,
WrCS (with RW delay)

16 +

TCL - 4
+

ALE fall. edge to RdCS,
WrCS (no RW delay)

-4 +

-4
+

Address float after RdCS,
WrCS (with RW delay)

Address float after RdCS,
WrCS (no RW delay)

TCL

RdCS to Valid Data In
(with RW delay)

16 +

2TCL - 24
+

RdCS to Valid Data In
(no RW delay)

36 +

3TCL - 24
+

RdCS, WrCS Low Time
(with RW delay)

30 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW delay)

50 +

3TCL - 10
+

Multiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

Data valid to WrCS

26 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS

20 +

2TCL - 20
+

Address hold after
RdCS, WrCS

20 +

2TCL - 20
+

Data hold after WrCS

20 +

2TCL - 20
+

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Multiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

AC Characteristics

Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

11 +

TCL - 14
+

Address setup to ALE

5 +

TCL - 20
+

Address hold after ALE

15 +

TCL - 10
+

ALE falling edge to RD,
WR (with RW-delay)

15 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

Address float after RD,
WR (with RW-delay)

Address float after RD,
WR (no RW-delay)

TCL + 6

RD, WR low time
(with RW-delay)

34 +

2TCL - 16
+

RD, WR low time
(no RW-delay)

59 +

3TCL - 16
+

RD to valid data in
(with RW-delay)

22 +

2TCL - 28
+

RD to valid data in
(no RW-delay)

47 +

3TCL - 28
+

ALE low to valid data in

49 +

3TCL - 30
+

Address to valid data in

57 + 2

4TCL - 43
+ 2

Data hold after RD
rising edge

Data float after RD

36 +

2TCL - 14
+

&3,

Data Sheet

1999-07

Data valid to WR

24 +

2TCL - 26
+

Data hold after WR

36 +

2TCL - 14
+

ALE rising edge after RD,
WR

36 +

2TCL - 14
+

Address hold after RD,
WR

36 +

2TCL - 14
+

ALE falling edge to CS

-8 -

10 -

-8 -

10 -

CS low to Valid Data In

47
+

+ 2

3TCL - 28
+

+ 2

CS hold after RD, WR

57 +

3TCL - 18
+

ALE fall. edge to RdCS,
WrCS (with RW delay)

19 +

TCL - 6
+

ALE fall. edge to RdCS,
WrCS (no RW delay)

-6 +

-6
+

Address float after RdCS,
WrCS (with RW delay)

Address float after RdCS,
WrCS (no RW delay)

TCL

RdCS to Valid Data In
(with RW delay)

20 +

2TCL - 30
+

RdCS to Valid Data In
(no RW delay)

45 +

3TCL - 30
+

RdCS, WrCS Low Time
(with RW delay)

38 +

2TCL - 12
+

RdCS, WrCS Low Time
(no RW delay)

63 +

3TCL - 12
+

Data valid to WrCS

28 +

2TCL - 22
+

Multiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

Data hold after RdCS

Data float after RdCS

30 +

2TCL - 20
+

Address hold after
RdCS, WrCS

30 +

2TCL - 20
+

Data hold after WrCS

30 +

2TCL - 20
+

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Multiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(150 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

AC Characteristics

Demultiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

TCL - 10
+

Address setup to ALE

4 +

TCL - 16
+

ALE falling edge to RD,
WR (with RW-delay)

10 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

-10
+

RD, WR low time
(with RW-delay)

30 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

50 +

3TCL - 10
+

RD to valid data in
(with RW-delay)

20 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

40 +

3TCL - 20
+

ALE low to valid data in

40 +

3TCL - 20
+

Address to valid data in

50 +
2

4TCL - 30
+ 2

Data hold after RD
rising edge

Data float after RD rising
edge (with RW-delay

)

26 +
2

2TCL - 14
+ 22

Data float after RD rising
edge (no RW-delay

)

10 +
2

TCL - 10
+ 22

Data valid to WR

20 +

2TCL - 20
+

&3,

Data Sheet

1999-07

Data hold after WR

10 +

TCL - 10
+

ALE rising edge after RD,
WR

-10 +

Address hold after WR

0 +

ALE falling edge to CS

-4 -

10 -

-4 -

10 -

CS low to Valid Data In

40 +

+ 2

3TCL - 20
+

+ 2

CS hold after RD, WR

6 +

TCL - 14
+

ALE falling edge to
RdCS, WrCS (with RW-
delay)

16 +

TCL - 4
+

ALE falling edge to
RdCS, WrCS (no RW-
delay)

-4 +

-4
+

RdCS to Valid Data In
(with RW-delay)

16 +

2TCL - 24
+

RdCS to Valid Data In
(no RW-delay)

36 +

3TCL

- 24

RdCS, WrCS Low Time
(with RW-delay)

30 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW-delay)

50 +

3TCL - 10
+

Data valid to WrCS

26 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS
(with RW-delay)

20 +

2TCL - 20
+ 2

Data float after RdCS
(no RW-delay)

0 +

TCL - 20
+ 2

Demultiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

Address hold after
RdCS, WrCS

-6 +

Data hold after WrCS

6 +

TCL - 14 +

1) RW-delay and

refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Demultiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

AC Characteristics

Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

ALE high time

11 +

TCL - 14
+

Address setup to ALE

5 +

TCL - 20
+

ALE falling edge to RD,
WR (with RW-delay)

15 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

-10
+

RD, WR low time
(with RW-delay)

34 +

2TCL - 16
+

RD, WR low time
(no RW-delay)

59 +

3TCL - 16
+

RD to valid data in
(with RW-delay)

22 +

2TCL - 28
+

RD to valid data in
(no RW-delay)

47 +

3TCL - 28
+

ALE low to valid data in

49 +

3TCL - 30
+

Address to valid data in

57 +
2

4TCL - 43
+ 2

Data hold after RD
rising edge

Data float after RD rising
edge (with RW-delay

)

36 +
2

2TCL - 14
+ 2

Data float after RD rising
edge (no RW-delay

)

15 +
2

TCL - 10
+ 2

Data valid to WR

24 +

2TCL - 26
+

&3,

Data Sheet

1999-07

Data hold after WR

15 +

TCL - 10
+

ALE rising edge after RD,
WR

-12 +

Address hold after WR

0 +

ALE falling edge to CS

-8 -

10 -

-8 -

10 -

CS low to Valid Data In

47 +

+ 2

3TCL - 28
+

+ 2

CS hold after RD, WR

9 +

TCL - 16
+

ALE falling edge to
RdCS, WrCS (with RW-
delay)

19 +

TCL - 6
+

ALE falling edge to
RdCS, WrCS (no RW-
delay)

-6 +

-6
+

RdCS to Valid Data In
(with RW-delay)

20 +

2TCL - 30
+

RdCS to Valid Data In
(no RW-delay)

45 +

3TCL

- 30

RdCS, WrCS Low Time
(with RW-delay)

38 +

2TCL - 12
+

RdCS, WrCS Low Time
(no RW-delay)

63 +

3TCL - 12
+

Data valid to WrCS

28 +

2TCL - 22
+

Data hold after RdCS

Data float after RdCS
(with RW-delay)

30 +

2TCL - 20
+ 2

Data float after RdCS
(no RW-delay)

5 +

TCL - 20
+ 2

Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

Address hold after
RdCS, WrCS

-16 +

Data hold after WrCS

9 +

TCL - 16
+

1) RW-delay and

refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes before the end of RD have no impact on read cycles.

3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE (see figures below).

Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(100 ns at 20 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

&3,

Data Sheet

1999-07

AC Characteristics

CLKOUT and READY (Standard Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

2TCL

CLKOUT high time

TCL 6

CLKOUT low time

TCL 10

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to
ALE falling edge

0 +

10 +

0 +

10 +

Synchronous READY
setup time to CLKOUT

Synchronous READY
hold time after CLKOUT

Asynchronous READY
low time

2TCL +

Asynchronous READY
setup time

1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Asynchronous READY
hold time

Async. READY hold time
after RD, WR high
(Demultiplexed Bus)

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.
The 2

and

refer to the next following bus cycle,

refers to the current bus cycle.

The maximum limit for

must be fulfilled if the next following bus cycle is READY controlled.

0
+ 2

TCL - 20
+ 2

&3,

Data Sheet

1999-07

AC Characteristics

CLKOUT and READY (Reduced Supply Voltage Range)
(Operating Conditions apply)

Parameter

Symbol

Max. CPU Clock

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

2TCL

CLKOUT high time

TCL 10

CLKOUT low time

TCL 12

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to
ALE falling edge

0 +

8 +

0 +

8 +

Synchronous READY
setup time to CLKOUT

Synchronous READY
hold time after CLKOUT

Asynchronous READY
low time

2TCL +

Asynchronous READY
setup time

1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Asynchronous READY
hold time

Async. READY hold time
after RD, WR high
(Demultiplexed Bus)

2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.
The 2

and

refer to the next following bus cycle,

refers to the current bus cycle.

The maximum limit for

must be fulfilled if the next following bus cycle is READY controlled.

0
+ 2

TCL - 25
+ 2

&3,

Data Sheet

1999-07

Figure 24

CLKOUT and READY

Notes

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill

in order to be safely synchronized. This is guaranteed,

if READY is removed in reponse to the command (see Note

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

The next external bus cycle may start here.

CLKOUT

ALE

Sync

READY