Edition 02.00

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München

Infineon Technologies AG 2000.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com

Enhanced Hooks Technology

is a trademark and patent of Metalink Corporation licensed to

Infineon Technologies.

C513AO Data Sheet
Revision History :

Current Version: 02.00

Previous Releases:

(Original Version)

c513ao_ds_0200.frm Page 0 Wednesday, August 30, 2000 12:45 PM

Data Sheet

02.00

8-Bit CMOS Microcontroller

Advance Information

C513AO

· Full upward compatibility with standard 8051 microcontroller
· Up to 16 MHz external operating frequency

750 ns instruction cycle at 16 MHz operation

· On-chip program memory

C513AO-2R: 16 Kbytes ROM (with optional ROM protection)
C513AO-2E: 16 Kbytes OTP
C513AO-L: version without on-chip program memory (ROMless)

· Up to 64K byte external data memory
· 256

8 RAM

· 256

8 XRAM

· Four 8-bit digital I/O ports
· Three 16-bit timers/counters (Timer 2 with Up/Down and 16-bit auto-reload features)
· Full duplex serial interface (USART)
· Synchronous Serial Channel (SSC)
· Seven interrupt sources with two priority levels
· On-chip emulation support logic (Enhanced Hooks Emulation Technology

)

(further features are on next page)

Figure 1
C513AO Functional Units

MCB04006

I/O

On-Chip Emulation Support Module

Watchdog Timer

SSC

Interface

Timer 2

Oscillator

Watchdog

XRAM

256 x 8

XRAM

256 x 8

ROM/OTP

16 K x 8

Port 3

Port 2

Port 1

Port 0

8-Bit

USART

C500

Core

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C513AO

Data Sheet

02.00

Features (continued):

· Programmable 15-bit Watchdog Timer
· Oscillator Watchdog
· Fast Power On Reset
· Power Saving Modes

Slow-down mode
Idle mode
Software power-down mode with optional wake up capability through pin P3.2/INT0

· Available in P-DIP40-2, P-LCC-44-1 and P-MQFP-44-2 packages
· Fully pin-compatible with C501, C504, C505C, C505CA and C511/C513-devices.
· Temperature ranges: SAB-C513AO

: 0 to 70

SAF-C513AO

: 40 to 85

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required
product. This ordering code identifies:

· the derivative itself, i.e. its function set
· the specified temperature range
· the package and the type of delivery

For the available ordering codes for the C513AO please refer to the "Product Information
Microcontrollers", which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after the

verification of the respective ROM code.

c513ao_ds_0200.frm Page 2 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Figure 3
P-DIP-40-2 Package Pin Configuration (top view)

C513AO

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

XTAL2

P3.7/RD

P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.1/TxD

P3.0/RxD

RESET

P1.7

P1.6

P1.5/SLS

P1.4/STO

P1.3/SRI

P1.2/SCLK

P1.1/T2EX

P1.0/T2

P3.2/INT0

MCP04008

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C513AO

Data Sheet

02.00

Figure 4
P-LCC-44-1 Package Pin Configuration (top view)

C513AO

P2.4/A12

27 26 25 24 23 22 21 20 19 18

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

XTAL2

P3.7/RD

P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TxD

N.C.

P3.0/RxD

RESET

P1.7

P1.6

P1.5/SLS

40 41 42 43 44 1

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

P1.0/T2

P1.1/T2EX

P1.2/SCLK

P1.3/SRI

P1.4/STO

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

N.C.

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

MCP04009

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C513AO

Data Sheet

02.00

Figure 5
P-MQFP-44-2 Package Pin Configuration (top view)

C513AO

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

N.C.

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8

XTAL1
XTAL2
P3.7/RD
P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TxD

N.C.

P3.0/RxD

RESET

P1.7

P1.6

P1.5/SLS

P1.4/STO

P1.3/SRI

P1.2/SCLK

P1.1/T2EX

P1.0/T2

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

32 31 30 29 28 27 26 25 24 23

9 10 11

MCP04010

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C513AO

Data Sheet

02.00

Table 1
Pin Definitions and Functions

Symbol Pin Number

I/O
*)

Function

P- DIP
-40

P-LCC-
44

P-MQFP-
44

P1.7-
P1.0

8-1

1
2

4
5
6

9-2

2
3

5
6
7

3-1,
44-40

40
41

43
44
1

I/O Port 1

Port 1 is an 8-bit quasi-bidirectional port with internal
pull-up arrangement. Port 1 pins that have "1s"
written to them are pulled high by the internal pull-up
transistors and in that state can be used as inputs.
As inputs, Port 1 pins being externally pulled low will
source current (

, in the DC characteristics)

because of the internal pull-up transistors.
The output latch corresponding to a secondary
function must be programmed to 1 for that function
to operate.

For the outputs of the Synchronous Serial Channel
(SSC), SCLK and STO, special circuitry is
implemented providing true push-pull capability.
The STO output, in addition, will have true tristate
capability. When used for SSC inputs, the pull-up
transistors will be switched off and the inputs float
(high ohm inputs).

The secondary functions are assigned to the pins of
Port 1 as follows:

P1.0 / T2

Input to Counter 2

P1.1 / T2EX

Capture/reload trigger of Timer 2
Up-Down count

P1.2 / SCLK

SSC Master Clock Output
SSC Slave Clock Input

P1.3 / SRI

SSC Receive Input

P1.4 / STO

SSC Transmit Output

P1.5 / SLS

Slave Select Input

I = Input
O = Output

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C513AO

Data Sheet

02.00

P3.0-
P.3.7

10-17

14
15
16

11,
13-19

16
17
18

5,
7-13

10
11
12

I/O Port 3

Port 3 is an 8-bit quasi-bidirectional port with internal
pull-up arrangement. Port 3 pins that have "1"s
written to them are pulled high by the internal pull-up
transistors and in that state can be used as inputs.
As inputs, Port 3 pins being externally pulled low will
source current (

, in the DC characteristics)

because of the internal pull-up transistors.
The output latch corresponding to a secondary
function must be programmed to a "1" for that
function to operate (except for TxD and WR).

The secondary functions are assigned to the pins of
Port 3 as follows:

P3.0 / RxD

Receiver data input (asynch.)
or data input/output (synch.) of
serial interface

P3.1 / TxD

Transmitter data output
(asynch.) or clock output
(synch.) of serial interface

P3.2 / INT0

External Interrupt 0 input /
Timer 0 gate control input

P3.3 / INT1

External Interrupt 1 input /
Timer 1 gate control input

P3.4 / T0

Timer 0 counter input

P3.5 / T1

Timer 1 counter input

P3.6 / WR

WR control output; latches the
data byte from Port 0 into the
external data memory

P3.7 / RD

RD control output; enables the
external data memory to Port 0

RESET

RESET
A high level on this pin for the duration of two
machine cycles while the oscillator is running resets
the device. An internal diffused resistor to

permits power-on reset using only an external
capacitor to

I = Input
O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol Pin Number

I/O
*)

Function

P- DIP
-40

P-LCC-
44

P-MQFP-
44

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C513AO

Data Sheet

02.00

XTAL2

XTAL2
Output of the inverting oscillator amplifier.

XTAL1

XTAL1
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left
unconnected.

There

are no requirements on the

duty

cycle of the external clock signal, since the

input to the internal clocking circuitry is divided down
by a divide-by-two flip-flop. Minimum and maximum
high and low times as well as rise/fall times specified
in the AC characteristics must be observed.

P2.0-
P2.7

21-28

24-31

18-25

I/O Port 2

Port 2 is a an 8-bit quasi-bidirectional I/O port with
internal pull-up arrangement. Port 2 pins that have
"1s" written to them are pulled high by the internal
pull-up transistors, and in that state can be used as
inputs. As inputs, Port 2 pins being externally pulled
low will source current (

, in the DC characteristics)

because of the internal pullup transistors. Port 2
emits the high-order address byte during fetches
from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup transistors when issuing
"1"s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), Port 2 issues the
contents of the P2 Special Function Register and
uses only the internal pull-up transistors.

PSEN

Program Store Enable
This is a control signal that enables output of the
external program memory to the bus during external
fetch operations. It is activated every three oscillator
periods except during external data memory
accesses. It remains high during internal program
execution.
This pin should not be driven during reset operation.

I = Input
O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol Pin Number

I/O
*)

Function

P- DIP
-40

P-LCC-
44

P-MQFP-
44

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C513AO

Data Sheet

02.00

ALE

Address Latch Enable
This output is used for latching the low-byte of the
address into external memory during normal
operation. It is activated every six oscillator periods
except during an external data memory access.
When instructions are executed from internal
program memory (EA = 1) the ALE generation can
be disabled by bit EALE in SFR SYSCON.
This pin should not be driven during reset operation.

External Access Enable
When held at high level, instructions are fetched
from the internal program memory when the PC is
less than 4000

. When held at low level, the

C513AO fetches all instructions from external
program memory.
This pin should not be driven during reset operation.
Note: For the C513AO-L this pin must be tied low.

P0.0-
P0.7

32-39

43-36

37-30

I/O Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have "1s" written to them float, and
in that state can be used as high-impendance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program or
data memory. In this application, it uses strong
internal pull-up transistors when issuing 1s. External
pull-up resistors are required during program
verification.

22, 1

16, 39

Ground (0 V)

44, 23

38, 17

Power Supply (+ 5 V)

N.C.

12, 34

6, 28

No Connection. These pins should not be
connected.

I = Input
O = Output

Table 1
Pin Definitions and Functions (cont'd)

Symbol Pin Number

I/O
*)

Function

P- DIP
-40

P-LCC-
44

P-MQFP-
44

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C513AO

Data Sheet

02.00

CPU

The C513AO is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and
15% three-byte instructions. With a 16-MHz crystal, 58% of the instructions execute in 750 ns.

Special Function Register PSW (Address D0

)

Reset Value: 00

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag 0

RS1
RS0

Register bank Select control bits
These bits are used to select one of the four register banks.

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag 1

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

PSW

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00

-07

Bank 1 selected, data address 08

-0F

Bank 2 selected, data address 10

-17

Bank 3 selected, data address 18

-1F

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C513AO

Data Sheet

02.00

Memory Organization

The C513AO CPU manipulates operands in the following five address spaces:

· Up to 64 Kbytes of program memory (up to 16 KB on-chip program memory for the C513AO-2R/

2E)

· Up to 64 Kbytes of external data memory
· 256 bytes of internal data memory
· 256 bytes of internal XRAM data memory
· One 128-byte special function register area

Figure 7 illustrates the memory address spaces of the C513AO.

Figure 7
C513AO Memory Map

MCA04012

Special

Function

Regs.

Direct

Addr.

Indirect

Addr.

Internal

RAM

Internal

RAM

"Internal Data Space"

Internal

XRAM

(256 byte)

FFFF

FF00

Ext.

Data

Memory

0000

FEFF

Ext.

Data

Memory

"Data Space"

4000

FFFF

Ext.

"Code Space"

Ext.

(EA = 0)

3FFF

0000

Int.

(EA = 1)

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C513AO

Data Sheet

02.00

Reset and System Clock

The reset input is an active high input. An internal Schmitt-trigger is used at the input for noise
rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least
two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running,
the internal reset is executed during the second machine cycle and is repeated every cycle until
RESET goes low again. Figure 8 shows the possible reset circuitries.

Figure 8
Reset Circuitries

C513AO

RESET

C513AO

RESET

C513AO

RESET

MCS03291

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C513AO

Data Sheet

02.00

Figure 9 shows the recommended oscillator circiutries for crystal and external clock operation.

Figure 9
Recommended Oscillator Circuitry

In this application, the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator
(a more detailed schematic is given in Figure 10). lt is operated in its fundamental response mode
as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal
specifications and capacitances are non-critical. In this circuit, 20 pF can be used as single
capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used
in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors
normally will have different values, dependent on the oscillator frequency. We recommend
consulting the manufacturer of the ceramic resonator for value specifications of these capacitors.

MCS04014

XTAL2

C513AO

XTAL1

3.5-16 MHz

= 20 pF ±10 pF for crystal operation

c513ao_ds_0200.frm Page 15 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Figure 10
On-Chip Oscillator Circuitry

To drive the C513AO with an external clock source, the external clock signal must be applied to
XTAL1, as shown in Figure 11. XTAL2 must be left unconnected. A pull-up resistor is suggested to
increase the noise margin, but is optional if

of the driving gate corresponds to the

IH2

specification of XTAL1.

Figure 11
External Clock Source

MCS04015

C513AO

To internal
timing circuitry

)

XTAL2

XTAL1

Crystal or ceramic resonator
Resistor is only in the C513AO-2E

)

MCS04016

External
Clock
Signal

C513AO

XTAL2

XTAL1

N.C.

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C513AO

Data Sheet

02.00

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 12
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon

Technologies.

SYSCON

PCON

TCON

RESET

ALE

PSEN

Port 0

Port 2

Port 1

Port 3

opt.

I/O Ports

C500

MCU

RPCON

RTCON

Enhanced Hooks

Interface Circuit

RSYSCON

RPORT RPORT

TEA TALE TPSEN

EH-IC

ICE-System interface

to emulation hardware

Target System Interface

MCS03254

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C513AO

Data Sheet

02.00

Special Function Registers

The registers reside in the special function register area, with the exception of the Program Counter
and the four General Purpose Register banks. The special function register area consists of two
portions: the

standard

special function register area and the

mapped

special function register area.

Four special function registers of the C513AO (PCON1, VR0, VR1 & VR2) are located in the
mapped special function register area. For accessing the mapped special function register area, bit
RMAP in special function register SYSCON must be set. All other special function registers of the
C513AO are located in the standard special function register area.

Special Function Register SYSCON (Address B1

)

Reset Value: XX10XXX0

If bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by
hardware automatically.

The forty Special Function Registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C513AO are listed in Table 2 and Table 3. In Table 2, they are organized in groups
which refer to the functional blocks of the C513AO. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.

Bit

Function

RMAP

Special function Register MAP bit
RMAP = 0: The access to the non-mapped (standard) special function

RMAP = 1: The access to the mapped special function register area is

enabled.

Reserved bits for future use. Read by CPU returns undefined values.

EALE

RMAP

SYSCON

Bit No.

MSB

LSB

XMAP

The functions of the shaded bits are not described in this section.

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Data Sheet

02.00

Table 2
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address Contents after

Reset

CPU

ACC
B
DPH
DPL
PSW
SP
SYSCON

VR0

4) 5)

VR1

4) 5)

VR2

4) 5)

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
System Control Register
Version Register 0
Version Register 1

Version Register 2

XX10XXX0

Interrupt
System

IE
IP

Interrupt Enable Register
Interrupt Priority Register

X0000000

Ports

P0
P1
P2
P3

Port 0
Port 1
Port 2
Port 3

Serial
Channel
(USART)

PCON

SBUF
SCON

Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register

000X0000

SSC
Interface

SSCCON
STB
SRB
SCF
SCIEN
SSCMOD

SSC Control Register
SSC Transmit Register
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register

XXXXXX00

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
4) This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) This SFR is read-only.
6) C513AO-L/2R: 13

C513AO-2E: 83

7) This SFR varies with the step of the microcontroller: for example, 01

for the first step

8) This register is only used for test purposes and must not be written during normal operation. Unpredictable

results may occur upon a write operation.

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C513AO

Data Sheet

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Timer 2

T2CON
T2MOD
RC2H
RC2L
TH2
TL2

Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload/Capture Register, High Byte
Timer 2 Reload/Capture Register, Low Byte
Timer 2 High Byte
Timer 2 Low Byte

XXXXXXX0

Watchdog WDCON

WDTREL

Watchdog Timer Control Register
Watchdog Timer Reload Register

XXXX0000

Power
Save
Mode

PCON

PCON1

Power Control Register
Power Control Register 1

000X0000

0XXXXXXX

C513AO-2E: 83

7) This SFR varies with the step of the microcontroller: for example, 01

for the first step

8) This register is only used for test purposes and must not be written during normal operation. Unpredictable

results may occur upon a write operation.

Table 2
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address Contents after

Reset

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C513AO

Data Sheet

02.00

Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses

Addr.

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DPL

DPH

WDTREL 00

WDT
PSEL

PCON

0XX0-
0000

SMOD

GF1

GF0

PDE

IDLE

2) 3)

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

PCON1

0XX0-
XXXX

EWPD

TMOD

GATE

C/T

GATE

C/T

TL0

TL1

TH0

TH1

.SLS

STO

SRI

SCLK

T2EX

SCON

SM0

SM1

SM2

REN

TB8

RB8

SBUF

ESSC ET2

ET1

EX1

ET0

EX0

INT1

INT0

TxD

RxD

SYSCON XX10-

XXX0

EALE RMAP

XMAP

X000-
0000

PSSC PT2

PT1

PX1

PT0

PX0

WDCON

XXXX-
0000

OWDS WDTS WDT

SWDT

1) "X" means that the value is undefined and the location is reserved.
2) Bit-addressable special function registers.
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers.
5) The content of this SFR varies with the actual step of the C513A0: for example, 01

for the first step).

6) This register is only used for test purposes and must not be written during normal operation. Unpredictable

results may occur upon a write operation.

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C513AO

Data Sheet

02.00

T2CON

TF2

EXF2 RCLK TCLK

EXEN2 TR2

C/T2

CP/
RL2

T2MOD

XXXX-
XXX0

DCEN

RC2L

RC2H

TL2

TH2

PSW

RS1

RS0

ACC

SSCCON 07

SCEN

TEN

MSTR CPOL

CPHA

BRS2

BRS1

BRS0

STB

SRB

SSCMOD 00

LOOPB TRIO

LSBSM

SCF

XXXX-
XX00

WCOL

SCIEN

XXXX-
XX00

WCEN

TCEN

3) 4)

VR0

3) 4)

VR1

3) 4)

VR2

1) "X" means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These SFRs are read-only registers.
5) The content of this SFR varies with the actual step of the C513A0: for example, 01

for the first step)

6) This register is only used for test purposes and must not be written during normal operation. Unpredictable

results may occur upon a write operation.

7) C513AO-L/2R: 13

C513AO-2E: 83

Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont'd)

Addr.

Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

c513ao_ds_0200.frm Page 22 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Parallel I/O Port

The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2,
and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as
inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will
float when configured as input.

The output drivers of Port 0 and Port 2 and the input buffers of Port 0 are also used for accessing
external memory. In this application, Port 0 outputs the low byte of the external memory address,
time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external
memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the
P2 SFR contents. In this case, Port 0 is not an open-drain port, but uses a strong internal pull-up
Field Effect Transistors (FETs).

Port 1 pins used for Synchronous Serial Channel (SSC) outputs are true push-pull outputs. When
used as SSC inputs, they float (no pull-up).

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C513AO

Data Sheet

02.00

Timer/Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Since a machine
cycle consists of twelve oscillator periods, the count rate is 1/12th of the oscillator frequency.

In "counter" function, the register is incremented in response to a 1-to-0 transition (falling edge) at
its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, respectively).
Since it takes two machine cycles to detect a falling edge; therefore, the maximum count rate is 1/
24th of the oscillator frequency. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to
function as a gate to facilitate pulse width measurements. Figure 13 illustrates the input clock logic.

Figure 13
Timer/Counter 0 and 1 Input Clock Logic

Table 4
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

Internal

External (max.)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/(12

32)

OSC

/(24

32)

16-bit timer/counter

OSC

/12

OSC

/24

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

OSC

/12

MCS01768

OSC

C/T

TMOD

Control

Timer 0/1
Input Clock

TCON

TR 0/1

Gate

TMOD

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

OSC

/24

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C513AO

Data Sheet

02.00

Timer/Counter 2 with Compare/Capture/Reload

Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes:

· 16-bit auto-reload mode (up or down counting)
· 16-bit capture mode
· Baudrate generator

Note:

denotes a falling edge

Table 5
Timer / Counter 2 Operating Modes

Mode

T2CON

T2MOD T2CON

P1.1/
T2EX

Remarks

Input Clock

RCLK
or
TCLK

CP/
RL2

TR2

DCEN

EXEN2

Internal

External
(P1.0/
T2)

16-bit
Auto-
reload

0
0

1
1

X
X

0
1

reload upon
overflow
reload trigger
(falling edge)
down counting
up counting

OSC

/12

max

OSC

/24

16-bit
Capture

16-bit Timer/
Counter (only
up-counting)
capture TH2,
TL2

RC2H,

RC2L

OSC

/12

max

OSC

/24

Baudrate
Generator

no overflow
interrupt
request (TF2)
extra external
interrupt
("Timer 2")

OSC

/12

max

OSC

/24

off

Timer 2 stops

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C513AO

Data Sheet

02.00

Serial Interface (USART)

The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also
receive-buffered; it can commence reception of a second byte before a previously-received byte
has been read from the receive register. The serial port can operate in 4 modes (one synchronous
and three asynchronous) as illustrated in Table 6.

For clarification, some terms regarding the difference between "baudrate clock" and "baudrate"
should be mentioned.

The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization.
Therefore, the baudrate generators must provide a "baudrate clock" to the serial interface which
divides it by 16, thereby resulting in the actual "baudrate".

The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be
determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive).

Table 6
USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode
Serial data enters and exits through R

D. T

D outputs the

shift clock. 8-bit data are transmitted/received (LSB first) at a
fixed baudrate of

th of the oscillator frequency.

8-bit USART, variable baudrate
10 bits are transmitted (through T

D) or received (at R

D).

9-bit USART, fixed baudrate
11 bits are transmitted (through T

D) or received (at R

D).

9-bit USART, variable baudrate
Similar to mode 2, except for the variable baudrate.

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C513AO

Data Sheet

02.00

Figure 14
Block Diagram of Baudrate Generation for the Serial Interface

Table 7 lists the values/formulas for the baudrate calculation of the serial interface with its
dependencies on the control bits SMOD (in SFR PCON), TCLK and RCLK (both in SFR T2CON).

Table 7
Serial Interface - Baudrate Dependencies

Serial Interface
Operating Modes

Control Bits

Baudrate Calculation

SMOD

TCLK/RCLK

Mode 0 (Shift Register)

OSC

/12

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

Determined by timer 1 overflow rate:
(2

SMOD

timer 1 overflow rate)/32

Determined by timer 2 overflow rate:
Timer 2 overflow rate/16

Mode 2 (9-bit UART)

0
1

OSC

/64

OSC

/32

MCS04017

SCON.7/

SCON.6

(SM0/

SM1)

Mode 1
Mode 3
Mode 2

Mode 0

÷ 6

OSC

Timer 1 Overflow

Only one mode
can be selected

PCON.7
(SMOD)

÷ 2

Baudrate
Clock

0
1

Note: The switch configuration shows the reset state

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C513AO

Data Sheet

02.00

SSC Interface

The Synchronous Serial Channel (SSC) interface is compatible to the popular SPI serial bus
interface. It can be used for simple I/O expansion via shift registers, for connection with a variety of
peripheral components (such as A/D converters, EEPROMs etc.), or interconnection of several
microcontrollers in a master/slave structure. The SSC unit supports full-duplex or half-duplex
operation and can run in Master Mode or Slave Mode.

Figure 15 shows the block diagram of the SSC.

Figure 15
SSC Block Diagram

Interrupt System

The C513AO provides seven interrupt sources with two priority levels. Five of the interrupts can be
generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, USART, and SSC) and three of the
interrupts may be triggered externally (P1.1/T2EX, P3.2/INT0, P3.3/INT1). A non-maskable eighth
interrupt is reserved for external wake-up from power-down mode.

Figure 16 gives a general overview of the interrupt sources and illustrates the request and the
control flags. Table 8 lists the vector addresses of each interrupt source.

MCB02735

P1.2/SCLK

P1.3/SRI

P1.4/STO

P1.5/SLS

Control

Logic

Shift Register

Receive Buffer Register

STB

Clock Selection

Clock Divider

SRB

OSC

Control Register

Status Register

Int. Enable Reg.

SCIEN

SSCCON

SCF

Control Logic

Internal Bus

Interrupt

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C513AO

Data Sheet

02.00

If two interrupt requests of different priority levels are received simultaneously, the request of higher
priority is serviced. If requests of the same priority are received simultaneously, an internal polling
sequence determines which request is serviced. Thus, within each priority level there is a second
priority structure determined by the polling sequence as shown in Table 9.

A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority
interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.

Table 8
Interrupt Vector Addresses

Interrupt Source

Request Flags

Vector Address

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
USART serial port interrupt
Timer 2 interrupt
Synchronous Serial Channel interrupt (SSC)
Wake-up from power-down mode

IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
WCOL+TC

0003

000B

0013

001B

0023

002B

0043

007B

Table 9
Interrupt Source Structure

Interrupt Source

Priority

External Interrupt 0
Synchronous Serial Channel
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Universal Serial Channel
Timer 2 Interrupt

IE0
WCOL OR TC
TFO
IE1
TF1
RI OR TI
TF2 OR EXF2

High

Low

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C513AO

Data Sheet

02.00

Fail Save Mechanisms

The C513AO offers enhanced fail-safe mechanisms which allow automatic recovery from a
software upset or a hardware failure:

· A programmable Watchdog Timer (WDT) has variable time-out period from 512

s up to approx.

1.1 sec. at 12 MHz

· An Oscillator Watchdog (OWD) monitors the on-chip oscillator and forces the microcontroller into

reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after
power-on.

The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either

CYCLE

/2 or

CYCLE

/32 (

CYCLE

OSC

/12). That is, the machine clock is divided by a fixed divide-by-two

prescaler and an optional divide-by-16 prescaler arranged in series. For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 17 shows
the block diagram of the watchdog timer unit.

Figure 17
Block Diagram of the Watchdog Timer

The Watchdog Timer can be started by software (bit SWDT in SFR WDCON); but, it cannot be
stopped during active mode of the device. If the software fails to clear the Watchdog Timer, an
internal reset will be initiated. The reset cause can be examined by software (status flag WDTS in
WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR WDCON) and
SWDT consecutively. This double instruction sequence has been implemented to increase system
security. During a refresh, the content of the SFR WDTREL is transferred to SFR WDTH, i.e. the
upper 7-bit of the watchdog timer. It must be noted, however, that the watchdog timer is stopped
during the idle mode and power down mode of the processor.

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C513AO

Data Sheet

02.00

Oscillator Watchdog

The Oscillator Watchdog (OWD) unit is used for three functions:

· Monitoring the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency. If the frequency is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the
RC oscillator and the device is brought into reset. If the failure condition disappears (that is, if the
on-chip oscillator has a higher frequency than the RC oscillator), the device executes a final reset
phase of typically 1 ms to allow the oscillator to stabilize. Then, the oscillator watchdog reset is
released and the device resumes program execution.

· Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for reset before the on-chip oscillator has
started. The oscillator watchdog unit reset works identically to the monitoring function.

· Control of external wake-up from software power-down mode

When power-down mode is terminated by a low level at the INT0 pin, the oscillator watchdog unit
ensures that the microcontroller resumes operation (execution of the power-down wake-up
interrupt) with the nominal clock rate. In power-down mode, the RC oscillator and the on-chip
oscillator are stopped. Both oscillators are started again when power-down mode is terminated.
When the on-chip oscillator has a frequency higher than the RC oscillator, the microcontroller
starts operation after a final delay of typ. 1 ms to allow the on-chip oscillator to stabilize.

Note: The Oscillator Watchdog unit is always enabled.

Figure 18 shows the block diagram of the Oscillator Watchdog unit.

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C513AO

Data Sheet

02.00

Power Saving Modes

The C513AO provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Power-
down Mode.

· Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are
able to function. Idle mode is entered by software and can be left by an interrupt or reset.

· Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is internally
divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32nd
of their normal operating frequency and also reduces power consumption.

· Power down mode

The operation of the C513AO is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. This power down
mode is entered by software and can be left by reset or a short low pulse at pin P3.2/INT0.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated. Table 10 gives
a general overview of the entry and exit procedures of the power saving modes.

Table 10
Power Saving Modes Overview

Mode

Entering
Example

Leaving by

Remarks

Idle mode

ORL PCON, #01

Occurrence of an any
enabled interrupt

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with clock

Hardware reset

Slow Down Mode

In normal mode:
ORL PCON,#10

ANL PCON,#0EF

or Hardware reset

Internal clock rate is reduced to
1/32 of its nominal frequency

With idle mode:
ORL PCON,#11

Occurrence of any
enabled interrupt and
the instruction
ANL PCON,#0EF

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/32
of its nominal frequency

Hardware reset

Power Down
Mode

ORL PCON, #02

Hardware reset

Oscillator is stopped;
contents of on-chip RAM and
SFRs are maintained;

Short low pulse at pin
P3.2/INT0

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C513AO

Data Sheet

02.00

Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During absolute maximum rating overload conditions
(

) the voltage on

pins with respect to ground (

) must not exceed

the values defined by the absolute maximum ratings.

Operating Conditions

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Storage temperature

150

° C

Voltage on

pins with respect

to ground (

)

0.5

6.5

Voltage on any pin with respect
to ground (

)

0.5

+ 0.5

Input current on any pin during
overload condition

Absolute sum of all input currents
during overload condition

|100 mA|

Power dissipation

DISS

t.b.d.

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Supply voltage

4.25

5.5

Ground voltage

Ambient temperature
SAB-C513AO
SAF-C513AO

0
40

70
85

° C

CPU clock

CPU

3.5

MHz

c513ao_ds_0200.frm Page 35 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C513AO and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column "Symbol":

CC (Controller Characteristics):
The logic of the C513AO will provide signals with the respective characteristics.

SR (System Requirement):
The external system must provide signals with the respective characteristics to the C513AO.

DC Characteristics
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Input low voltage
Pins except EA, RESET
EA pin
RESET pin

IL1

IL2

0.5
0.5
0.5

0.2

0.1

0.2

0.3

0.2

+ 0.1

V
V
V

Input high voltage
Pins except XTAL1, RESET
XTAL1 pin
RESET pin

IH1

IH2

0.6

0.7

0.6

+ 0.5

V
V
V

Output low voltage
Ports 1, 2, 3 (except P1.2, P1.4)
Port 0, ALE, PSEN
P1.2, P1.4 pull-up transistor
resistance

OL1

DSON CC

0.45
0.45
120

V
V

= 1.6 mA

= 3.2 mA

= 0.45 V

Output High Voltage
Ports 1, 2, 3

Port 0 in external bus mode,
ALE, PSEN
P1.2, P1.4 pull-up transistor
resistance

OH1

DSON CC

2.4
0.9

120

V
V
V
V

= 80

= 10

= 800

= 80

= 0.9

Logic 0 input current
Ports 1, 2, 3

= 0.45 V

Logical 0-to-1 transition current,
Ports 1, 2, 3

650

I
N

2 V

Input Leakage Current
Port 0, EA
P1.2, P1.3, P1.5 as SSC inputs

0.45 <

Input high current to RESET for
reset

100

0.6 <

c513ao_ds_0200.frm Page 36 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Notes see next page.

Power Supply Current

Input low current to XTAL1

IL2

I N

0.45 V

Pin capacitance

= 1 MHz,

= 25 °C

Overload current

8) 9)

Parameter

Symbol Limit Values Unit Test Condition

typ.

10)

max.

Active mode

C513AO-2E 12 MHz

16 MHz

10.3
13.1

13.0
16.6

mA
mA

C513AO-2R 12 MHz

16 MHz

6.9
8.5

9.0
10.9

mA
mA

Idle mode

C513AO-2E 12 MHz

16 MHz

5.7
6.8

7.2
8.7

mA
mA

C513AO-2R 12 MHz

16 MHz

4.1
4.8

5.5
6.0

mA
mA

Active mode with
slow-down enabled

C513AO-2E 12 MHz

16 MHz

4.5
5.1

5.7
6.5

mA
mA

C513AO-2R 12 MHz

16 MHz

3.3
3.6

4.1
4.5

mA
mA

Idle mode with
slow-down enabled

C513AO-2E 12 MHz

16 MHz

3.7
4.0

4.7
5.1

mA
mA

C513AO-2R 12 MHz

16 MHz

2.6
2.8

3.3
3.5

mA
mA

Power-down mode

C513AO-2E

8.8

= 2

...

5.5 V

C513AO-2R

1.28

= 2

...

5.5 V

DC Characteristics (cont'd)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

c513ao_ds_0200.frm Page 37 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,
or use an address latch with a Schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

(power-down mode) is measured under following conditions:

EA = Port0 =

; RESET =

; XTAL2 = N.C.; XTAL1 =

;

all other pins are disconnected.

would be

slightly higher if a crystal oscillator is used (appr. 1 mA).

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL1 = N.C.;

EA = PE/SWD = Port 0 = Port 6 =

; HWPD =

;

RESET =

;

all other pins are disconnected.

would be slightly higher if a crystal oscillator is used (appr. 1 mA).

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; Port0 =

; all other pins are disconnected.

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled; XTAL1 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; Port0 =

; all other pins are disconnected.

(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled; XTAL1 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; Port0 =

; all other pins are disconnected.

8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e.

+ 0.5 V or

0.5 V). The supply voltage

and

must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed
50 mA.

9) Not 100% tested, guaranteed by design characterization.

10)The typical

values are periodically measured at

= + 25 °C and

= 5 V but not 100% tested.

c513ao_ds_0200.frm Page 38 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Power Supply Current Calculation Formula

Note:

osc

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

C513-2E

DD typ

DD max

0.70

OSC

+ 1.8

0.91

OSC

+ 2.0

C513-2R

DD typ

DD max

0.40

OSC

+ 2.1

0.48

OSC

+ 3.2

Idle mode

C513-2E

DD typ

DD max

0.29

OSC

+ 2.2

0.36

OSC

+ 2.9

C513-2R

DD typ

DD max

0.18

OSC

+ 1.9

0.13

OSC

+ 3.9

Active mode with
slow-down enabled

C513-2E

DD typ

DD max

0.15

OSC

+ 2.6

0.20

OSC

+ 2.9

C513-2R

DD typ

DD max

0.08

OSC

+ 2.4

0.10

OSC

+ 2.9

Idle mode with
slow-down enabled

C513-2E

DD typ

DD max

0.09

OSC

+ 2.5

0.12

OSC

+ 3.2

C513-2R

DD typ

DD max

0.05

OSC

+ 2.0

0.05

OSC

+ 2.7

c513ao_ds_0200.frm Page 40 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

AC Characteristics (16 MHz)

(Operating Conditions apply)
(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Interfacing the C513AO to devices with float times up to 55 ns is permissible. This limited bus contention will
not cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

16 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 16 MHz

min.

max.

min.

max.

Program Memory Characteristics

ALE pulse width

LHLL

CLCL

Address setup to ALE

AVLL

CLCL

Address hold after ALE

LLAX

CLCL

ALE low to valid instruction in

LLIV

150

CLCL

100

ALE to PSEN

LLPL

CLCL

PSEN pulse width

PLPH

153

CLCL

PSEN to valid instruction in

PLIV

CLCL

100

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLCL

Address valid after PSEN

PXAV

CLCL

Address to valid instr in

AVIV

198

CLCL

115

Address float to PSEN

AZPL

c513ao_ds_0200.frm Page 41 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

AC Characteristics (16 MHz, cont'd)

(Operating Conditions apply)
(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Parameter

Symbol

Limit Values

Unit

16 MHz

Clock

Variable Clock

CLCL

= 3.5 MHz to 16 MHz

min.

max.

min.

max.

External Data Memory Characteristics

RD pulse width

RLRH

275

CLCL

100

WR pulse width

WLWH

275

CLCL

100

Address hold after ALE

LLAX2

CLCL

RD to valid data in

RLDV

148

CLCL

165

Data hold after RD

RHDX

Data float after RD

RHDZ

CLCL

ALE to valid data in

LLDV

350

CLCL

150

Address to valid data in

AVDV

398

CLCL

165

ALE to WR or RD

LLWL

138

238

CLCL

+ 50

Address valid to WR or RD

AVWL

120

CLCL

130

WR or RD high to ALE high

WHLH

103

CLCL

+ 40

Data valid to WR transition

QVWX

CLCL

Data setup before WR

QVWH

288

CLCL

150

Data hold after WR

WHQX

CLCL

Address float after RD

RLAZ

c513ao_ds_0200.frm Page 42 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Synchronous Serial Channel (SSC) Interface Characteristics

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

16 MHz Clock

min.

max.

Clock Cycle Time: Master Mode

Slave Mode

SCLK

500
450

ns
ns

Clock High Time

SCH

CC/SR

1) This parameter is `CC' in Master Mode, and `SR' in Slave Mode.

200

Clock Low Time

SCL

CC/SR

200

Data Output Delay

100

Data Output Hold

Data Input Setup

Data Input Hold

TC Bit Set Delay

DTC

CLCL

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 3.5 MHz to 16 MHz

min.

max.

Oscillator period

CLCL

62.5

285

High time

CHCX

CLCL

CLCX

Low time

CLCX

CLCL

CHCX

Rise time

CLCH

Fall time

CHCL

c513ao_ds_0200.frm Page 43 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Figure 23
SSC Timing

Figure 24
External Clock Drive on XTAL1

MCT02417

SCLK

STO

SRI

SCL

MSB

LSB

MSB

LSB

SCH

SCLK

~ ~

DTC

Notes: Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is

valid for the other cases accordingly.

In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).

In the case of master mode and CPHA = 0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.

MCT00033

CHCX

CLCX

CHCL

CLCH

CLCL

- 0.5V

0.45V

0.7

V - 0.1

0.2

c513ao_ds_0200.frm Page 47 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

OTP Memory Characteristics (C513AO-2E only)

Programming Mode Timing Characteristics
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit

min.

max.

PALE Pulse Width

PAW

PMSEL Set-up to PALE Rising Edge

PMS

Address Set-up to PALE, PROG, or PRD
Falling Edge

PAS

Address Hold after PALE, PROG, or PRD
Falling Edge

PAH

Address, Data Set-up to PROG or PRD

PCS

100

Address, Data Hold after PROG or PRD

PCH

PMSEL Set-up to PROG or PRD

PMS

PMSEL Hold after PROG or PRD

PMH

PROG Pulse Width

PWW

100

PRD Pulse Width

PRW

100

Address to Valid Data out

PAD

PRD to Valid Data out

PRD

Data Hold after PRD

PDH

Data float after PRD

PDF

PROG High between two Consecutive
PROG Low Pulses

PWH1

PRD High between two Consecutive PRD
Low Pulses

PWH2

100

XTAL Clock Period

CLKP

62.5

286

c513ao_ds_0200.frm Page 48 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Figure 27
Lock Bit Access Timing

Figure 28
Version Registers - Read Timing

PDR

MCT04320

PCS

PMS

D0, D1

PCH

PMH

PWW

PRW

PMS

PRD

PMH

PDH

H, L

D0, D1

PMSEL1, 0

Port 0

PROG

PRD

Notes: PALE should be low during a lock bit read/write cycle

MCT04321

PRW

PCS

PDH

e.g. FD

D0-7

Port 2

Port 0

PRD

PMSEL1, 0

L, H

PCH

PMH

PDF

PRD

PMS

Notes: PROG must be high during a programming read cycle

c513ao_ds_0200.frm Page 51 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

OTP Verification Mode Characteristics

Note: ALE pin described below is not the OTP Programming Mode pin PALE

Figure 29
OTP Verification Mode

Parameter

Symbol

Limit Values

Unit

min.

typ

max.

ALE Pulse Width

AWD

CLCL

ALE Period

ACY

CLCL

Data Valid after ALE

DVA

CLCL

Data Stable after ALE

DSA

CLCL

P3.5 Set-up to ALE Low

CLCL

Oscillator Frequency

CLCL

MHz

MCT04322

ALE

Port 0

P3.5

ACY

AWD

DSA

DVA

Data Valid

c513ao_ds_0200.frm Page 52 Wednesday, August 30, 2000 12:45 PM

C513AO

Data Sheet

02.00

Figure 30
AC Testing: Input, Output Waveforms

Figure 31
AC Testing: Float Waveforms

AC Inputs during testing are driven at

0.5 V for a logic "1" and 0.45 V for a logic "0".

Timing measurements are made at

IHmin

for a logic "1" and

ILmax

for a logic "0".

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.