Edition 2003-02

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany

Infineon Technologies AG 2003.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.

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For further information on technology, delivery terms and conditions and prices please contact your nearest
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(

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Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
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of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
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Enhanced Hooks TechnologyTM is a trademark of Infineon Technologies.

C515C Data Sheet

Revision History:

2003-02

Previous Version:

2000-08

Page

Subjects (major changes since last revision)

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Data Sheet

2003-02

C515C

8-Bit Single-Chip Microcontroller

Features

· Full upward compatibility with SAB 80C515A
· On-chip program memory (with optional memory protection)

C515C-8R 64 Kbytes on-chip ROM
C515C-8E 64 Kbytes on-chip OTP
alternatively up to 64 Kbytes external program memory

· 256 bytes on-chip RAM
· 2 Kbytes of on-chip XRAM
· Up to 64 Kbytes external data memory
· Superset of the 8051 architecture with 8 datapointers
· Up to 10 MHz external operating frequency (1

s instruction cycle time at 6 MHz

external clock)

· On-chip emulation support logic (Enhanced Hooks Technology)
· Current optimized oscillator circuit and EMI optimized design

(further features are on next page)

Figure 1

C515C Functional Units

MCA03646

On-Chip Emulation Support Module

Port 0

Port 1

Port 2

Port 3

RAM

256 x 8

XRAM

CPU

USART

I/O

8 Datapointer

Port 7

Port 6

Port 5

Port 4

Capture/Compare Unit

Timer 2

Full-CAN

Controller

10 Bit ADC

(8 inputs)

Oscillator

Watchdog

Save Modes

Idle/

Power down

Slow down

SSC (SPI)

Interface

I/O

Analog/

Digital

Input

Power

Bit

2k x 8

C515C-8R : 64k x 8 ROM

Program Memory

C515C-8E : 64k x 8 OTP

C515C

Data Sheet

2003-02

· Eight ports: 48 + 1 digital I/O lines, 8 analog inputs

Quasi-bidirectional port structure (8051 compatible)
Port 5 selectable for bidirectional port structure (CMOS voltage levels)

· Full-CAN controller on-chip

256 register/data bytes are located in external data memory area
max. 1 MBaud at 8 - 10 MHz operating frequency

· Three 16-bit timer/counters

Timer 2 can be used for compare/capture functions

· 10-bit A/D converter with multiplexed inputs and built-in self calibration
· Full duplex serial interface with programmable baudrate generator (USART)
· SSC synchronous serial interface (SPI compatible)

Master and slave capable
Programmable clock polarity/clock-edge to data phase relation
LSB/MSB first selectable
2.5 MHz transfer rate at 10 MHz operating frequency

· Seventeen interrupt vectors, at four priority levels selectable
· Extended watchdog facilities

15-bit programmable watchdog timer
Oscillator watchdog

· Power saving modes

Slow-down mode
Idle mode (can be combined with slow-down mode)
Software power-down mode with wake-up capability through INT0 or RXDC pin
Hardware power-down mode

· CPU running condition output pin
· ALE can be switched off
· Multiple separate

pin pairs

· P-MQFP-80-1 package
· Temperature Ranges:

SAB-C515C versions:

= 0 to 70

SAF-C515C versions:

= -40 to 85

SAH-C515C versions:

= -40 to 110

Note: Versions for extended temperature range -40

C to 110

C (SAH-C515C) are

available on request.

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller
which additionally provides a full CAN interface, a SPI compatible synchronous serial
interface, extended power save provisions, additional on-chip RAM, 64K of on-chip
program memory, two new external interrupts and RFI related improvements. With a
maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1

at 6 MHz).

C515C

Data Sheet

2003-02

The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The
C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory.
The C515C-8E is the OTP version in the C515C microcontroller with an on-chip
64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in
a P-MQFP-80-1 package.

If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally
provides two features:

· The wake-up from software power down mode can, additionally to the external pin

P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin
P4.7/RXDC.

· For power consumption reasons the on-chip CAN controller can be switched off.

Note: The term C515C refers to all versions described within this document unless

otherwise noted.

Ordering Information

The ordering code for Infineon Technologies' microcontrollers provides an exact
reference to the required product. This ordering code identifies:

· The derivative itself, i.e. its function set
· The specified temperature rage
· The package and the type of delivery

For the available ordering codes for the C515C please refer to the "Product information
Microcontrollers", which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Table 1

Differences in Internal Program Memory of the C505 MCUs

Device

Internal Program Memory

ROM

OTP

C515C-LM

C515C-8RM

64 Kbytes

C515C-8EM

64 Kbytes

C515C

Data Sheet

2003-02

Figure 3

C515C Pin Configuration P-MQFP-80-1 (top view)

MCP02715

1 2

N.C.

3 4 5

P6.7/AIN7

P6.6/AIN6

P6.5/AIN5

P6.4/AIN4

P6.3/AIN3

P6.2/AIN2

P6.1/AIN1

P6.0/AIN0

13 14 15

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

AGND

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

ALE

PSEN

CPUR

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P4.7/RXDC

P4.6/TXDC

P4.5/INT8

P4.4/SLS

P4.3/STO

PE/SWD

P4.2/SRI

P4.1/SCLK

P4.0/ADST

N.C.

HWPD

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

SSE1

P3.6/WR

P3.7/RD

P1.7/T2

P1.6/CLKOUT

P1.5/T2EX

P1.4/INT2

P1.3/INT6/CC3

P1.2/INT5/CC2

P1.1/INT4/CC1

P1.0/INT3/CC0

XTAL2

XTAL1

P2.0/A8

P2.1/A9

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

39
38
37
36
35
34
33
32

31
30

29
28
27
26
25
24
23
22

P5.6

P5.7

SS1

DDE1

DD1

P2.2/A10

AREF

RESET

C515C

SSCLK

DDCLK

P7.0/INT7

DDEXT

SSEXT

DDE2

SSE2

C515C

Data Sheet

2003-02

Table 2

Pin Definitions and Functions

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

RESET

RESET
A low level on this pin for the duration of two
machine cycles while the oscillator is running resets
the C515C. A small internal pullup resistor permits
power-on reset using only a capacitor connected to

AREF

Reference voltage for the A/D converter

AGND

Reference ground for the A/D converter

P6.0-P6.7

12-5

Port 6
is an 8-bit unidirectional input port to the
A/D converter. Port pins can be used for digital
input, if voltage levels simultaneously meet the
specifications high/low input voltages and for the
eight multiplexed analog inputs.

P7.0 / INT7 23

I/O

Port 7
is an 1-bit quasi-bidirectional I/O port with internal
pull-up resistor. When a 1 is written to P7.0 it is
pulled high by an internal pull-up resistor, and in that
state can be used as input. As input, P7.0 being
externally pulled low will source current (

, in the

DC characteristics) because of the internal pull-up
resistor. If P7.0 is used as interrupt input, its output
latch must be programmed to a one (1). The
secondary function is assigned to the port 7 pin as
follows:
P7.0 INT7, Interrupt 7 input

C515C

Data Sheet

2003-02

P3.0-P3.7

15-22

19
20
21

I/O

Port 3
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 3 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 3 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors. Port 3 also contains the
interrupt, timer, serial port and external memory
strobe pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate. The secondary functions are assigned to
the pins of port 3, as follows:
P3.0

RXD

Receiver data input (asynch.) or
data input/output (synch.) of
serial interface

P3.1

TXD

Transmitter data output (asynch.)
or clock output (synch.) of serial
interface

P3.2 INT0

External interrupt 0 input / timer 0
gate control input

P3.3 INT1

External interrupt 1 input / timer 1
gate control input

P3.4

Timer 0 counter input

P3.5

Timer 1 counter input

P3.6 WR

WR control output; latches the
data byte from port 0 into the
external data memory

P3.7 RD

RD control output; enables the
external data memory

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

P1.0 - P1.7 31-24

27
26

25
24

I/O

Port 1
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 1 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 1 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors. The port is used for the
low-order address byte during program verification.
Port 1 also contains the interrupt, timer, clock,
capture and compare pins that are used by various
options. The output latch corresponding to a
secondary function must be programmed to a one
(1) for that function to operate (except when used for
the compare functions). The secondary functions
are assigned to the port 1 pins as follows:
P1.0 INT3 CC0 Interrupt 3 input / compare 0

output / capture 0 input

P1.1 INT4 CC1 Interrupt 4 input / compare 1

output / capture 1 input

P1.2 INT5 CC2 Interrupt 5 input / compare 2

output / capture 2 input

P1.3 INT6 CC3 Interrupt 6 input / compare 3

output / capture 3 input

P1.4 INT2

Interrupt 2 input

P1.5 T2EX

Timer 2 external reload / trigger

input

P1.6 CLKOUT

System clock output

P1.7 T2

Counter 2 input

XTAL2

XTAL2
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source,
XTAL2 should be driven, while XTAL1 is left
unconnected. Minimum and maximum high and low
times as well as rise/fall times specified in the AC
characteristics must be observed.

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

XTAL1

XTAL1
Output of the inverting oscillator amplifier.

P2.0-P2.7

38-45

I/O

Port 2
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 2 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 2 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors.
Port 2 emits the high-order address byte during
fetches from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup resistors when issuing
1's. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register.

CPUR

CPU Running Condition
This output pin is at low level when the CPU is
running and program fetches or data accesses in
the external data memory area are executed. In idle
mode, hardware and software power down mode,
and with an active RESET signal CPUR is set to
high level.
CPUR can be typically used for switching external
memory devices into power saving modes.

PSEN

The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator
periods, except during external data memory
accesses. The signal remains high during internal
program execution.

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

ALE

The Address Latch Enable
output is used for latching the address into external
memory during normal operation. It is activated
every six oscillator periods, except during an
external data memory access. ALE can be switched
off when the program is executed internally.

External Access Enable
When held high, the C515C executes instructions
always from the internal ROM. When held low, the
C515C fetches all instructions from external
program memory.

Note: For the ROM protection version EA pin is

latched during reset.

P0.0-P0.7

52-59

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1's written to them float, and in
that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong
internal pullup resistors when issuing 1's.
Port 0 also outputs the code bytes during program
verification in the C515C. External pullup resistors
are required during program verification.

P5.0-P5.7

67-60

I/O

Port 5
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 5 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 5 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pullup resistors.
Port 5 can also be switched into a bidirectional
mode, in which CMOS levels are provided. In this
bidirectional mode, each port 5 pin can be
programmed individually as input or output.

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

HWPD

Hardware Power Down
A low level on this pin for the duration of one
machine cycle while the oscillator is running resets
the C515C.
A low level for a longer period will force the part to
power down mode with the pins floating.

P4.0-P4.7

72-74, 76-80

72
73

74
76
77
78
79

I/O

Port 4
is an 8-bit quasi-bidirectional I/O port with internal
pull-up resistors. Port 4 pins that have 1's written to
them are pulled high by the internal pull-up resistors,
and in that state can be used as inputs. As inputs,
port 4 pins being externally pulled low will source
current (

, in the DC characteristics) because of

the internal pull-up resistors.
P4 also contains the external A/D converter control
pin, the SSC pins, the CAN controller input/output
lines, and the external interrupt 8 input. The output
latch corresponding to a secondary function must
be programmed to a one (1) for that function to
operate. The alternate functions are assigned to
port 4 as follows:
P4.0 ADST

External A/D converter start pin

P4.1 SCLK

SSC Master Clock Output /
SSC Slave Clock Input

P4.2 SRI

SSC Receive Input

P4.3 STO

SSC Transmit Output

P4.4 SLS

Slave Select Input

P4.5 INT8

External interrupt 8 input

P4.6 TXDC

Transmitter output of the CAN
controller

P4.7 RXDC

Receiver input of the CAN controller

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

PE/SWD

Power saving mode enable / Start watchdog
timer
A low level on this pin allows the software to enter
the power down, idle and slow down mode. In case
the low level is also seen during reset, the watchdog
timer function is off on default.
Use of the software controlled power saving modes
is blocked, when this pin is held on high level. A high
level during reset performs an automatic start of the
watchdog timer immediately after reset. When left
unconnected this pin is pulled high by a weak
internal pull-up resistor.

SSCLK

Ground (0 V) for on-chip oscillator
This pin is used for ground connection of the on-chip
oscillator circuit.

DDCLK

Supply voltage for on-chip oscillator
This pin is used for power supply of the on-chip
oscillator circuit.

DDE1

DDE2

32
68

Supply voltage for I/O ports
These pins are used for power supply of the I/O
ports during normal, idle, and power down mode.

SSE1

SSE2

35
70

Ground (0 V) for I/O ports
These pins are used for ground connections of the
I/O ports during normal, idle, and power down
mode.

DD1

Supply voltage for internal logic
This pins is used for the power supply of the internal
logic circuits during normal, idle, and power down
mode.

SS1

Ground (0 V) for internal logic
This pin is used for the ground connection of the
internal logic circuits during normal, idle, and power
down mode.

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

DDEXT

Supply voltage for external access pins
This pin is used for power supply of the I/O ports and
control signals which are used during external
accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR,
and P3.7/RD).

SSEXT

Ground (0 V) for external access pins
This pin is used for the ground connection of the I/O
ports and control signals which are used during
external accesses (for Port 0, Port 2, ALE, PSEN,
P3.6/WR, and P3.7/RD).

N.C.

2, 71

Not connected
These pins should not be connected.

I = Input; O = Output

Table 2

Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O

Function

P-MQFP-80-1

C515C

Data Sheet

2003-02

Figure 4

Block Diagram of the C515C

MCB03647

Oscillator Watchdog

OSC & Timing

CPU

Timer 1

Timer 2

A/D Converter

Timer 0

S & H

MUX

XRAM
2k x 8

256 x 8

RAM

ROM/OTP

Port 0

Port 1

Port 2

Port 3

Port 0

Port 1

Port 2

XTAL2

XTAL1

RESET

ALE

AGND

AREF

Support

Emulation

Logic

8 Datapointers

Programmable

Watchdog Timer

PSEN

PE/SWD

HWPD

Capture

Compare Unit

Port 7

Port 6

Port 5

Port 4

C515C

8 Bit Digital I/O

8 Bit Analog/

Multiple

Lines

64k x 8

CPUR

8 Bit Digital I/O

Baud Rate Generator

SSC (SPI) Interface

Digital Inputs

Port 5

Port 4

Port 3

Port 6

Port 7
1 Bit Digital I/O

Reg./Data

256 Byte

Full-CAN

Controller

Interrupt Unit

10 Bit

USART

8 Bit Digital I/O

C515C

Data Sheet

2003-02

CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has
extensive facilities for binary and BCD arithmetic and excels in its bit-handling
capabilities. Efficient use of program memory results from an instruction set consisting
of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal,
58% of the instructions are executed in 1

s (10 MHz: 600 ns).

PSW
Special Function Register

(D0

)

Reset Value: 00

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an
odd/even number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

PSW

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00

-07

Bank 1 selected, data address 08

-0F

Bank 2 selected, data address 10

-17

Bank 3 selected, data address 18

-1F

C515C

Data Sheet

2003-02

Memory Organization

The C515C CPU manipulates data and operands in the following five address spaces:

· up to 64 Kbytes of internal/external program memory
· up to 64 Kbytes of external data memory
· 256 bytes of internal data memory
· 256 bytes CAN controller registers / data memory
· 2 Kbytes of internal XRAM data memory
· a 128 byte special function register area

Figure 5

illustrates the memory address spaces of the C515C.

Figure 5

C515C Memory Map

MCD02717

00 H

0000 H

External

FFFF H

"Code Space"

"Data Space"

"Internal Data Space"

0000

FFFF

External

F800 H

Internal

XRAM

RAM

Internal

RAM

FF H

Function

Special

Direct

Address

80 H

Address

Indirect

(2 KByte)

(EA = 0)

(EA = 1)

Internal

F6FF

Data

External

Memory

(256 Byte)

Controller

Int. CAN

F700

F7FF H

Alternatively

C515C

Data Sheet

2003-02

Control of XRAM/CAN Controller Access

The XRAM in the C515C is a memory area that is logically located at the upper end of
the external memory space, but is integrated on the chip. Because the XRAM and the
CAN controller is used in the same way as external data memory the same instruction
types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON,
XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.

SYSCON
Special Function Register

(B1

)

C515C-8R Reset Value: X010XX01

C515C-8E Reset Value: X010X001

Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access
enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit
again.

Bit

Function

XMAP1

XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller
accesses. If addresses are outside the XRAM/CAN controller
address range or if XRAM is disabled, this bit has no effect.
XMAP1 = 0: The signals RD and WR are not activated during

accesses to the XRAM/CAN Controller

XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated

during accesses to XRAM/CAN Controller. In this
mode, address and data information during
XRAM/CAN Controller accesses are visible externally.

XMAP0

Global XRAM/CAN controller access enable/disable control
XMAP0 = 0: The access to XRAM and CAN controller is enabled.
XMAP0 = 1: The access to XRAM and CAN controller is disabled

(default after reset). All MOVX accesses are
performed via the external bus. Further, this bit is
hardware protected.

Bit No.

MSB

LSB

EALE

RMAP

B1H

SYSCON

CSWO XMAP1

PMOD

XMAP0

The function of the shaded bits is not described in this section.

C515C

Data Sheet

2003-02

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR,
MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the
XRAM or CAN controller, the effective address stored in DPTR must be in the range of
F700

to FFFF

The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX
@Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1).
Therefore, a special page register XPAGE which provides the upper address information
(A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX
access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the
state of pin

Table 3

lists the various operating conditions.

C515C

Data Sheet

2003-02

modes compatible to 8051/C501 family

Table 3

Behaviour of P0/P2 and RD/WR During MOVX Accesses

XMAP1, XMAP0

EA = 0

MOVX
@DPTR

DPTR
<
XRAM/CAN
address range

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

DPTR

XRAMCAN
address range

a) P0/P2

Bus

(RD/WR-Data)
b) RD/WR inactive
c) XRAM is used

a) P0/P2

Bus

(RD/WR-Data)
b) RD/WR active
c) XRAM is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

MOVX
@ Ri

XPAGE
<
XRAMCAN
addr. page
range

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

XPAGE

XRAMCAN
addr. page
range

a) P0

Bus

(RD/WR-Data)
P2

I/O

b) RD/WR inactive
c) XRAM is used

a) P0

Bus

(RD/WR-Data only)
P2

I/O

b) RD/WR active
c) XRAM is used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

EA = 1

MOVX
@DPTR

DPTR
<
XRAM/CAN
address range

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

DPTR

XRAMCAN
address range

a) P0/P2

b) RD/WR inactive
c) XRAM is used

a) P0/P2

Bus

(RD/WR-Data)
b) RD/WR active
c) XRAM is used

a) P0/P2

Bus

b) RD/WR active
c) ext.memory
is used

MOVX
@ Ri

XPAGE
<
XRAMCAN
addr. page
range

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory is
used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

XPAGE

XRAMCAN
addr. page
range

a) P2

I/O

P0/P2

I/O

b) RD/WR inactive
c) XRAM is used

a) P0

Bus

(RD/WR-Data)
P2

I/O

b) RD/WR active
c) XRAM is used

a) P0

Bus

I/O

b) RD/WR active
c) ext.memory
is used

C515C

Data Sheet

2003-02

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized
internally, the RESET pin must be held low for at least two machine cycles (12 oscillator
periods) while the oscillator is running. A pullup resistor is internally connected to

allow a power-up reset with an external capacitor only. An automatic reset can be
obtained when

is applied by connecting the RESET pin to

via a capacitor.

Figure 6

shows the possible reset circuitries.

Figure 6

Reset Circuitries

Figure 7

shows the recommended oscillator circiutries for crystal and external clock

operation.

MCS02721

RESET

C515C

RESET

C515C

C515C

Data Sheet

2003-02

Figure 7

Recommended Oscillator Circuitries

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C515C contains
eight 16-bit datapointers instead of only one datapointer. The instruction set uses just
one of these datapointers at a time. The selection of the actual datapointer is done in the
special function register DPSEL.

Figure 8

illustrates the datapointer addressing

mechanism.

Figure 8

External Data Memory Addressing using Multiple Datapointers

MCT02765

XTAL1

XTAL2

XTAL1

Crystal/Resonator Oscillator Mode

Driving from External Source

External Oscillator
Signal

N.C.

2 - 10 MHz

C = 20 pF ± 10 pF (incl. stray capacitance)

Crystal Mode

:
:

Resonator Mode

= depends on selected ceramic resonator

DPH(83 )

DPL(82 )

DPTR0

DPTR7

DPSEL(92 )

DPSEL

Selected

Data-

pointer

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

MCD00779

External Data Memory

C515C

Data Sheet

2003-02

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new,
innovative way to control the execution of C500 MCUs and to gain extensive information
on the internal operation of the controllers. Emulation of on-chip ROM based programs
is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation
Concept. Therefore, no costly bond-out chips are necessary for emulation. This also
ensure that emulation and production chips are identical.

The Enhanced Hooks Technology, which requires embedded logic in the C500 allows
the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the
design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a
compatible C500 are able to emulate all operating modes of the different versions of the
C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and
ROMless modes of operation. It is also able to operate in single step mode and to read
the SFRs after a break.

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by
Enhanced Hooks Emulation Concept to control the operation of the device during
emulation and to transfer informations about the program execution and data transfer
between the external emulation hardware (ICE-system) and the C500 MCU.

MCS03280

SYSCON

PCON
TCON

RESET

PSEN

ALE

Port

I/O Ports

Optional

Port 3

Port 1

C500

MCU

Interface Circuit

Enhanced Hooks

RPort 0

RPort 2

RTCON

RPCON

RSYSCON

TEA

TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

C515C

Data Sheet

2003-02

Special Function Registers

The registers, except the program counter and the four general purpose register banks,
reside in the special function register area. The special function register area consists of
two portions: the standard special function register area and the mapped special function
register area. Two special function registers of the C515C (PCON1 and DIR5) are
located in the mapped special function register area. For accessing the mapped special
function register area, bit RMAP in special function register SYSCON must be set. All
other special function registers are located in the standard special function register area
which is accessed when RMAP is cleared ("0"). As long as bit RMAP is set, mapped
special function register area can be accessed. This bit is not cleared by hardware
automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit
RMAP must be cleared/set by software, respectively each.

SYSCON
Special Function Register

(B1

)

C515C-8R Reset Value: X010XX01

C515C-8E Reset Value: X010X001

The 59 special function registers (SFRs) in the standard and mapped SFR area include
pointers and registers that provide an interface between the CPU and the other on-chip
peripherals. The SFRs of the C515C are listed in

Table 4

and

Table 5

. In

Table 4

they

are organized in groups which refer to the functional blocks of the C515C. The CAN-
SFRs are also included in

Table 4

Table 5

illustrates the contents of the SFRs in

numeric order of their addresses.

Table 6

list the CAN-SFRs in numeric order of their

addresses.

Bit

Function

RMAP

Special function register map bit
RMAP = 0: The access to the non-mapped (standard) special

function register area is enabled (reset value).

RMAP = 1: The access to the mapped special function register

area is enabled.

Bit No.

MSB

LSB

EALE

RMAP

B1H

SYSCON

CSWO XMAP1

PMOD

XMAP0

The function of the shaded bits is not described in this section.

C515C

Data Sheet

2003-02

Table 4

Special Function Registers - Functional Block

Block

Symbol

Name

Addr

Contents after
Reset

CPU

ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
System Control Register

C515C-8R

C515C-8E

XXXXX000

X010XX01

X010X001

A/D-
Converter

ADCON0

ADCON1
ADDATH
ADDATL

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte

0XXXX000

00XXXXXX

Interrupt
System

IEN0

IEN1

IEN2
IP0

IP1
TCON

T2CON

SCON

IRCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register
Interrupt Request Control Register

XX00X00X

0X000000

XRAM

XPAGE

SYSCON

Page Address Register for Extended
on-chip XRAM and CAN Controller
System Control Register

C515C-8R

C515C-8E

X010XX01

X010X001

Ports

P0
P1
P2
P3
P4
P5
DIR5
P6
P7
SYSCON

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 5 Direction Register
Port 6, Analog/Digital Input
Port 7
System Control Register

C515C-8R

C515C-8E

2)4)

XXXXXXX1

X010XX01

X010X001

Watchdog

WDTREL
IEN0

IEN1

IP0

Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

C515C

Data Sheet

2003-02

Serial
Channel

ADCON0

PCON

SBUF
SCON
SRELL
SRELH

A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte

XXXXXX11

CAN
Controller

CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0

UMLM1

LMLM0

LMLM1

MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0n
DB1n
DB2n
DB3n
DB4n
DB5n
DB6n
DB7n

Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register
Low
Upper Mask of Last Message Register
High
Lower Mask of Last Message Register
Low
Lower Mask of Last Message Register
High
Message Object Registers:
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7

F700

F701

F702

F704

F705

F706

F707

F708

F709

F70A

F70B

F70C

F70D

F70E

F70F

F7n0

F7n1

F7n2

F7n3

F7n4

F7n5

F7n6

F7n7

F7n8

F7n9

F7nA

F7nB

F7nC

F7nD

F7nE

101

0UUUUUUU

UUU11111

UUUUU000

UUUUUU00

Table 4

Special Function Registers - Functional Block (cont'd)

Block

Symbol

Name

Addr

Contents after
Reset

C515C

Data Sheet

2003-02

SSC
Interface

SSCCON
STB
SRB
SCF
SCIEN
SSCMOD

SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register

XXXXXX00

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Compare/
Capture Unit/
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

Power Save
Modes

PCON

PCON1

Power Control Register
Power Control Register 1

C515C-8R

C515C-8E

0XXXXXXX

0XX0XXXX

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

Bit-addressable special function registers

"X" means that the value is undefined and the location is reserved.

This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

The notation "n" in the message object address definition defines the number of the related message object.

"X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by
a reset operation. "U" values are undefined (as "X") after a power-on reset operation.

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 4

Special Function Registers - Functional Block (cont'd)

Block

Symbol

Name

Addr

Contents after
Reset

C515C

Data Sheet

2003-02

Table 5

Contents of the SFRs, SFRs in Numeric Order
of their Addresses

Addr. Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DPL

DPH

WDTREL

WDT
PSEL

PCON

SMOD

PDS

IDLS

GF1

GF0

PDE

IDLE

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

PCON1

0XXX-
XXXX

EWPD

PCON1

0XX0-
XXXX

EWPD

TMOD

GATE

C/T

GATE

C/T

TL0

TL1

TH0

TH1

CLK-
OUT

T2EX

INT2

INT6

INT5

INT4

INT3

XPAGE

DPSEL

XXXX-
X000

SSCCON

SCEN

TEN

MSTR

CPOL

CPHA

BRS2

BRS1

BRS0

STB

SRB

SSCMOD

LOOPB TRIO

LSBSM

SCON

SM0

SM1

SM2

REN

TB8

RB8

SBUF

IEN2

X00X-
X00X

EX8

EX7

ESSC

ECAN

IEN0

EAL

WDT

ET2

ET1

EX1

ET0

EX0

IP0

OWDS

WDTS

C515C

Data Sheet

2003-02

SRELL

SCF

XXXX-
XX00

WCOL

SCIEN

XXXX-
XX00

WCEN

TCEN

INT1

INT0

TxD

RxD

SYSCON

X010-
XX01

PMOD

EALE

RMAP

XMAP1

XMAP0

SYSCON

X010-
X001

PMOD

EALE

RMAP

CSWO

XMAP1

XMAP0

IEN1

EXEN2

SWDT

EX6

EX5

EX4

EX3

EX2

EADC

IP1

0X00-
0000

PDIR

SRELH

XXXX-
XX11

IRCON

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

CCEN

COCA
H3

COCA
L3

COCA
H2

COCA
L2

COCA
H1

COCA
L1

COCA
H0

COCA
L0

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

T2CON

T2PS

I3FR

I2FR

T2R1

T2R0

T2CM

T2I1

T2I0

CRCL

CRCH

TL2

TH2

Table 5

Contents of the SFRs, SFRs in Numeric Order
of their Addresses (cont'd)

Addr. Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C515C

Data Sheet

2003-02

PSW

RS1

RS0

ADCON0

CLK

ADEX

BSY

ADM

MX2

MX1

MX0

ADDATH

ADDATL

00XX-
XXXX

ADCON1

0XXX-
X000

ADCL

MX2

MX1

MX0

ACC

RXDC

TXDC

INT8

SLS

STO

SRI

SCLK

ADST

DIR5

XXXX-
XXX1

INT7

VR0

7)8)

VR1

7)8)

VR2

7)8)

"X" means that the value is undefined and the location is reserved.

Bit-addressable special function registers

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

This SFR is available in the C515C-8R and C515C-L.

This SFR is available in the C515C-8E.

This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

These SFRs are read-only registers (C515C-8E only).

The content of this SFR varies with the actual step of the C515C-8E (e.g. 01

for the first step).

Table 5

Contents of the SFRs, SFRs in Numeric Order
of their Addresses (cont'd)

Addr. Register

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C515C

Data Sheet

2003-02

Table 6

Contents of the CAN Registers in Numeric Order
of their Addresses

Addr.
n = 1 to F

Regis-
ter

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

F700

TEST

CCE

EIE

SIE

INIT

F701

BOFF

EWRN

RXOK

TXOK

LEC2

LEC1

LEC0

F702

INTID

F704

BTR0

SJW

BRP

F705

BTR1

0UUU.
UUUU

TSEG2

TSEG1

F706

GMS0

ID28-21

F707

GMS1

UUU1.
1111

ID20-18

F708

UGML0

ID28-21

F709

UGML1

ID20-13

F70A

LGML0

ID12-5

F70B

LGML1

UUUU.
U000

ID4-0

F70C

UMLM0

ID28-21

F70D

UMLM1

ID20-18

ID17-13

F70E

LMLM0

ID12-5

F70F

LMLM1

UUUU.
U000

ID4-0

F7n0

MCR0

MSGVAL

TXIE

RXIE

INTPND

F7n1

MCR1

RMTPND

TXRQ

MSGLST

CPUUPD

NEWDAT

F7n2

UAR0

ID28-21

F7n3

UAR1

ID20-18

ID17-13

F7n4

LAR0

ID12-5

F7n5

LAR1

UUUU.
U000

ID4-0

F7n6

MCFG

UUUU.
UU00

DLC

DIR

XTD

F7n7

DB0n

F7n8

DB1n

F7n9

DB2n

F7nA

DB3n

F7nB

DB4n

C515C

Data Sheet

2003-02

F7nC

DB5n

F7nD

DB6n

F7nE

DB7n

The notation "n" in the address definition defines the number of the related message object.

"X" means that the value is undefined and the location is reserved. "U" means that the value is
unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation.

Table 6

Contents of the CAN Registers in Numeric Order
of their Addresses (cont'd)

Addr.
n = 1 to F

Regis-
ter

Content
after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C515C

Data Sheet

2003-02

Digital I/O Ports

The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and
one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read
and write accesses to the I/O ports P0 through P7 are performed via their corresponding
special function registers P0 to P7. The port structure of port 5 of the C515C is especially
designed to operate either as a quasi-bidirectional port structure, compatible to the
standard 8051-Family, or as a genuine bidirectional port structure. This port operating
mode can be selected by software (setting or clearing the bit PMOD in the SFR
SYSCON).

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for
accessing external memory. In this application, port 0 outputs the low byte of the external
memory address, time-multiplexed with the byte being written or read. Port 2 outputs the
high byte of the external memory address when the address is 16 bits wide. Otherwise,
the port 2 pins continue emitting the P2 SFR contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital
inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines.
When used for analog inputs the desired analog channel is selected by a three-bit field
in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to
these input-only ports by writing to the SFR P6. This will have no effect.

If a digital value is to be read, the voltage levels are to be held within the input voltage
specifications (

). Since P6 is not bit-addressable, all input lines of P6 are read at

the same time by byte instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input.
However, care must be taken that all bits of P6 that have an undetermined value caused
by their analog function are masked.

C515C

Data Sheet

2003-02

Port Structure Selection of Port 5

After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port
structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit
PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as
an input or an output, additionally, after the selection of the bidirectional mode the
direction register DIR5 of port 5 must be written. This direction register is mapped to the
port 5 register. This means, the port register address is equal to its direction register
address.

Figure 10

illustrates the port and direction register configuration.

Figure 10

Port Register, Direction Register

MCS02649

Int. Bus, Bit 7

Write to IP 1

Delay:

2.5 Machine Cycles

Port Register

Direction Register

Enable

PDIR

Enable

Write to Port

Read Port

Internal

Bus

Instruction sequence for the programming of the direction registers:

ORL IP1, #80H ; Set bit PDIR

Write port x direction register with value YYH

;

#OYYH

DIRx,

MOV

C515C

Data Sheet

2003-02

Timer / Counter 0 and 1

Timer / Counter 0 and 1 can be used in four operating modes as listed in

Table 7

In the "timer" function (C/

= `0') the register is incremented every machine cycle.

Therefore the count rate is

OSC

/6.

In the "counter" function the register is incremented in response to a 1-to-0 transition at
its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine
cycles to detect a falling edge the max. count rate is

OSC

/12. External inputs

INT0

and

INT1

(P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width

measurements.

Figure 11

illustrates the input clock logic.

Figure 11

Timer/Counter 0 and 1 Input Clock Logic

Table 7

Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Timer/Counter Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/12

16-bit timer/counter

OSC

/12

8-bit timer/counter with 8-bit
autoreload

Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer / Timer 1
stops

MCS03117

OSC

C/T = 0

C/T = 1

Control

TR1

P3.5/T1

(TMOD)

P3.2/INT0

Timer 0/1
Input Clock

OSC

P3.4/T0

TR0

Gate

P3.3/INT1

C515C

Data Sheet

2003-02

Timer / Counter 2 with Compare/Capture/Reload

The timer 2 of the C515C provides additional compare/capture/reload features, which
allow the selection of the following operating modes:

· Compare: up to 4 PWM signals with 16-bit/600 ns resolution
· Capture: up to 4 high speed capture inputs with 600 ns resolution
· Reload: modulation of timer 2 cycle time

The block diagram in

Figure 12

shows the general configuration of timer 2 with the

additional compare/capture/reload registers. The I/O pins which can used for timer 2
control are located as multifunctional port functions at port 1.

Figure 12

Timer 2 Block Diagram

MCB02730

Comparator

CCL3/CCH3

Capture

Input/

Output

Control

P1.0/
INT3/
CC0

CC1

INT4/

P1.1/

CC2

INT5/

P1.2/

CC3

INT6/

P1.2/

CCL2/CCH2

Comparator

CCL1/CCH1

Comparator

CRCL/CRCH

Comparator

Bit

16 Bit

OSC

÷6

÷12

OSC

T2PS

Sync.

P1.7/
T2

T2EX

P1.5/

Sync.

T2I1

T2I0

Timer 2

TH2

TL2

TF2

Reload

EXEN2

Reload

EXF2

Interrupt
Request

Compare

C515C

Data Sheet

2003-02

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated
timer. A roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer
overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register
T2CON are used to control the timer 2 operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A
prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator
frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as
a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer.
T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The
external gate signal is sampled once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in
response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this
function, the external input is sampled every machine cycle. Since it takes two machine
cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is
1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at least once before it changes,
it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also
causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which
is preset by software.

In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2
in SFR IEN1 has been set.

C515C

Data Sheet

2003-02

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows: the 16-bit
value stored in a compare or compare/capture register is compared with the contents of
the timer register; if the count value in the timer register matches the stored value, an
appropriate output signal is generated at a corresponding port pin and an interrupt can
be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output
signal changes from low to high. lt goes back to a low level on timer overflow. As long as
compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit
only and writing to the port will have no effect.

Figure 13

shows a functional diagram of

a port circuit when used in compare mode 0. The port latch is directly controlled by the
timer overflow and compare match signals. The input line from the internal bus and the
write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.

Figure 13

Port Latch in Compare Mode 0

MCS02661

Latch

Port

CLK

Port

Read Pin

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Overflow

Timer

16 Bit

Bit

C515C

Data Sheet

2003-02

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at
the port, the new value will not appear at the output pin until the next compare match
occurs. Thus, it can be choosen whether the output signal has to make a new transition
(1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the
time when the timer value matches the stored compare value.

In compare mode 1 (see

Figure 14

) the port circuit consists of two separate latches. One

latch (which acts as a "shadow latch") can be written under software control, but its value
will only be transferred to the port latch (and thus to the port pin) when a compare match
occurs.

Figure 14

Compare Function in Compare Mode 1

MCS02662

Latch

Port

CLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Port

16 Bit

C515C

Data Sheet

2003-02

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode,
three asynchronous modes) as illustrated in

Table 8

For clarification some terms regarding the difference between "baud rate clock" and
"baud rate" should be mentioned. In the asynchronous modes the serial interfaces
require a clock rate which is 16 times the baud rate for internal synchronization.
Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output
signal in

Figure 15

to the serial interface which - there divided by 16 - results in the

actual "baud rate". Further, the abbreviation

OSC

refers to the oscillator frequency

(crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either
from timer 1 or from a dedicated baud rate generator (see

Figure 15

Table 8

USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode, fixed baud rate
Serial data enters and exits through R

D; T

D outputs

the shift clock; 8-bit are transmitted/received (LSB first)

8-bit UART, variable baud rate
10 bits are transmitted (through T

D) or received (at

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D) or received (at

9-bit UART, variable baud rate
Like mode 2

C515C

Data Sheet

2003-02

Figure 15

Block Diagram of Baud Rate Generation for the Serial Interface

Table 9

below lists the values/formulas for the baud rate calculation of the serial

interface with its dependencies of the control bits BD and SMOD.

Table 9

Serial Interface - Baud Rate Dependencies

Serial Interface
Operating Modes

Active Control

Bits

Baud Rate Calculation

SMOD

Mode 0 (Shift
Register)

OSC

/ 6

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

Controlled by timer 1 overflow:
(2

SMOD

timer 1 overflow rate) / 32

Controlled by baud rate generator
(2

SMOD

OSC

) /

(32

baud rate generator overflow rate)

Mode 2 (9-bit UART)

0
1

OSC

/ 32

OSC

/ 16

MCS02733

Rate

OSC

(SMOD)

Baud

Clock

PCON.7

(SM0/

SM1)

SCON.7
SCON.6

Only one mode

can be selected

ADCON0.7

(BD)

0
1

Baud

Rate

Generator

(SRELH

SRELL)

Timer 1

Mode 2

Mode 0

Note: The switch configuration shows the reset state.

Mode 3

Mode 1

Overflow

C515C

Data Sheet

2003-02

SSC Interface

The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This
interface is compatible to the popular SPI serial bus interface.

Figure 16

shows the block

diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input
and the output of this shift register are each connected via a control logic to the pin P4.2
/ SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can
be written to (SFR STB) and can be read through the Receive Buffer Register SRB.

Figure 16

SSC Block Diagram

The SSC has implemented a clock control circuit, which can generate the clock via a
baud rate generator in the master mode, or receive the transfer clock in the slave mode.
The clock signal is fully programmable for clock polarity and phase. The pin used for the
clock signal is P4.1 / SCLK. When operating in slave mode, a slave select input is
provided which enables the SSC interface and also will control the transmitter output.
The pin used for this is P4.4 / SLS.

The SSC control block is responsible for controlling the different modes and operation of
the SSC, checking the status, and generating the respective status and interrupt signals.

MCB02735

P4.1/SCLK

P4.2/SRI

P4.3/STO

P4.4/SLS

Control

Logic

Shift Register

Receive Buffer Register

STB

Clock Selection

Clock Divider

SRB

OSC

Control Register

Status Register

Int. Enable Reg.

SCIEN

SSCCON

SCF

Control Logic

Internal Bus

Interrupt

C515C

Data Sheet

2003-02

CAN Controller

The on-chip CAN controller is the functional heart which provides all resources that are
required to run the standard CAN protocol (11-bit identifiers) as well as the extended
CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects
(up to 15). This includes bus arbitration, resending of garbled messages, error handling,
interrupt generation, etc. In order to implement the physical layer, external components
have to be connected to the C515C.

The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a
specific 256 bytes wide address range of the external data memory area (F700

F7FF

) and can be accessed using MOVX instructions.

Figure 17

shows a block

diagram of the on-chip CAN controller.

C515C

Data Sheet

2003-02

Figure 17

CAN Controller Block Diagram

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the
parallel access to the whole data or remote frame for the acceptance match test and the
parallel transfer of the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream
between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also
controls the EML and the parallel data stream between the TX/RX Shift Register and the
Intelligent Memory such that the processes of reception, arbitration, transmission, and
error signalling are performed according to the CAN protocol. Note that the automatic
retransmission of messages which have been corrupted by noise or other external error
conditions on the bus line is handled by the BSP.

MCB02736

Bit

Timing

Logic

Timing

Generator

BTL-Configuration

CRC

Gen./Check

TX/RX Shift Register

TXDC

RXDC

Intelligent

Interrupt

Memory

Processor

Status

Stream

Bit

Error

Logic

Management

Messages

Handlers

Control

Status +

to internal Bus

Clocks

Control

Messages

(to all)

C515C

Data Sheet

2003-02

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy
Check code to be transmitted after the data bytes and checks the CRC code of incoming
messages. This is done by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the
CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are
incremented and decremented by commands from the Bit Stream Processor. According
to the values of the error counters, the CAN controller is set into the states error active,
error passive and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline
related bit timing according to the CAN protocol. The BTL synchronizes on a recessive
to dominant busline transition at Start of Frame (hard synchronization) and on any further
recessive to dominant busline transition, if the CAN controller itself does not transmit a
dominant bit (resynchronization). The BTL also provides programmable time segments
to compensate for the propagation delay time and for phase shifts and to define the
position of the Sample Point in the bit time. The programming of the BTL depends on the
baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message
objects of maximum 8 data bytes length. Each of these objects has a unique identifier
and its own set of control and status bits. After the initial configuration, the Intelligent
Memory can handle the reception and transmission of data without further CPU actions.

Switch-off Capability of the CAN Controller (C515C-8E only)

For power consumption reasons, the on-chip CAN controller in the C515C-8E can be
switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is
switched off its clock signal is turned off and the operation of the CAN controller is
stopped. This switch-off state of the CAN controller is equal to its state in software power
down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.

C515C

Data Sheet

2003-02

10-Bit A/D Converter

The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with
8 analog input channels. It operates with a successive approximation technique and
uses self calibration mechanisms for reduction and compensation of offset and linearity
errors. The A/D converter provides the following features:

· 8 multiplexed input channels (port 6), which can also be used as digital inputs
· 10-bit resolution
· Single or continuous conversion mode
· Internal or external start-of-conversion trigger capability
· Interrupt request generation after each conversion
· Using successive approximation conversion technique via a capacitor array
· Built-in hidden calibration of offset and linearity errors

The main functional blocks of the A/D converter are shown in

Figure 19

The A/D converter uses basically two clock signals for operation: the input clock

(= 1/

) and the conversion clock

ADC

(= 1/

ADC

). These clock signals are derived from

the C515C system clock

OSC

which is applied at the XTAL pins. The input clock

equal to

OSC

. The conversion clock is limited to a maximum frequency of 2 MHz and

therefore must be adapted to

OSC

by programming the conversion clock prescaler. The

table in

Figure 18

shows the prescaler ratios and the resulting A/D conversion times

which must be selected for typical system clock rates.

C515C

Data Sheet

2003-02

Figure 19

A/D Converter Block Diagram

Input
Clock

Clock

Conversion

S & H

Conversion

Start of

Shaded bit locations are not used in ADC-functions.

Write to
ADDATL

P4.0/ADST

AGND

OSC

AREF

Port 6

MUX

Conversion

Clock

Prescaler

IRCON (C0 )

ADCON0 (D8 )

ADCON1 (DC )

ADCL

P6 (DB )

P6.7

EXF2

ADEX

CLK

BSY

P6.5

IEX6

P6.6

TF2

P6.4

IEX5

SWDT

IEN1 (B8 )

EXEN2

EX6

EX5

Single/

Converter

Continuous

A/D

ADC

Mode

MSB

LSB

MCB02747

Bus

Internal

ADDATL
(DA )

MX2

ADM

MX1

IEX3

P6.2

P6.3

IEX4

P6.1

IEX2

ADDATH

(D9 )

MX0

P6.0

IADC

EX3

EX4

EX2

EADC

Bus

Internal

C515C

Data Sheet

2003-02

Interrupt System

The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can
be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface,
A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered
externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The wake-up from power-down mode
interrupt has a special functionality which allows to exit from the software power-down
mode by a short low pulse at pin P3.2/INT0.

In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt
sources. Each interrupt group can be programmed to one of the four interrupt priority
levels.

Figure 20

Figure 22

give a general overview of the interrupt sources and

illustrate the interrupt request and control flags.

C515C

Data Sheet

2003-02

Figure 20

Interrupt Request Sources (Part 1)

Polling Sequence

ECAN

Error

CAN Controller Interrupt Sources

Note: Each of the 15 CAN controller message objects provides the bits/flags in the shaded area.

IEN0.7

cleared by hardware

Request Flag is

Receive

INT2

P1.4/

T2CON.5

Bit addressable

I2FR

RXIE

MCR0.5/4

Message
Transmit

Message

TXIE

MCR0.3/2

CR.3

EIE

IEN1.1

IEX2

IRCON.1

EX2

EAL

004B

IEN2.1

INTPND

MCR0.0/1

CR.1

see Note

MCS02752

IP1.1

IP0.1

0003

INT0

Overflow

Status

Timer 0

CR.2

SIE

A/D Converter

TCON.0

IT0

IEN0.1

< 1

TCON.5

TF0

008B

ET0

000B

IEN0.0

EADC

IEN1.0

IADC

IRCON.0

TCON.1

0043

EX0

P3.2/

IE0

Priority Level

IP1.0

IP0.0

Lowest

Highest
Priority Level

C515C

Data Sheet

2003-02

Figure 21

Interrupt Request Sources (Part 2)

MCS02753

Bit addressable

Request Flag is
cleared by hardware

IP1.2

0013

TCON.3

IEN0.2

IE1

EX1

P3.3/

IT1

TCON.2

ESSC

IEN2.2

0093 H

SCF.1

WCOL

SCF.0

SSC

IP0.2

Highest
Priority Level

0053 H

IP1.3

IP0.3

Timer 1

001B

TCON.7

IEN0.3

TF1

ET1

Overflow

INT1

INT4/

P1.1/

EX4

IEX4

IEN1.3

IRCON.3

005B H

CC1

Lowest
Priority Level

EAL

IEN0.7

Polling Sequence

T2CON.6

I3FR

EX3

IEX3

IEN1.2

IRCON.2

CC0

P1.0/
INT3/

Inerface

SCIEN.1

WCEN

TCEN

SCIEN.0

C515C

Data Sheet

2003-02

Figure 22

Interrupt Request Sources (Part 3)

MCS02754

Bit addressable

Request Flag is
cleared by hardware

IP1.4

0023

IEN0.4

00A3 H

SCON.0

SCON.1

USART

IP0.4

Highest
Priority Level

EX5

IEX5

IEN1.4

IRCON.4

0063 H

IP1.5

IP0.5

Timer 2

00AB

Overflow

006B H

Lowest
Priority Level

EAL

IEN0.7

Polling Sequence

IEN2.4

EX7

CC2

P1.2/
INT5/

IRCON.7

EXF2

TF2

IRCON.6

IEN0.5

ET2

002B H

EXEN2

IEN1.7

P1.5/

T2EX

INT6/

P1.3/

CC3

EX8

IEN2.5

IRCON.5

IEN1.5

IEX6

EX6

INT7

P7.0/

P4.5/
INT8

C515C

Data Sheet

2003-02

Table 10

Interrupt Source and Vectors

Interrupt Source

Interrupt Vector
Address

Interrupt Request Flags

External Interrupt 0

0003

IE0

Timer 0 Overflow

000B

TF0

External Interrupt 1

0013

IE1

Timer 1 Overflow

001B

TF1

Serial Channel

0023

RI / TI

Timer 2 Overflow / Ext. Reload 002B

TF2 / EXF2

A/D Converter

0043

IADC

External Interrupt 2

004B

IEX2

External Interrupt 3

0053

IEX3

External Interrupt 4

005B

IEX4

External Interrupt 5

0063

IEX5

External Interrupt 6

006B

IEX6

Wake-up from power-down
mode

007B

CAN controller

008B

External Interrupt 7

00A3

External Interrupt 8

00AB

SSC interface

0093

TC / WCOL

C515C

Data Sheet

2003-02

Fail Save Mechanisms

The C515C offers two on-chip peripherals which monitor the program flow and ensure
an automatic "fail-safe" reaction for cases where the controller's hardware fails or the
software hangs up:

· A programmable watchdog timer (WDT) with variable time-out period from

512 microseconds up to approx. 1.1 seconds at 6 MHz.

· An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the
clock for a fast internal reset after power-on.

Programmable Watchdog Timer

The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate
of

OSC

/12 up to

OSC

/192. For programming of the watchdog timer overflow rate, the

upper 7 bit of the watchdog timer can be written.

Figure 23

shows the block diagram of

the watchdog timer unit.

Figure 23

Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin
PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails
to refresh the running watchdog timer an internal reset will be initiated on watchdog timer
overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is
transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of

MCB02755

Control Logic

PE/SWD

External HW Power-Down

WDT Reset Request

WDTH

WDTREL (86 )

7 6

IEN1 (B8 )

IEN0 (A8 )

WDTL

IP0 (A9 )

WDT

SWDT

External HW Reset

WDTS

WDTPSEL

÷16

OSC

÷2

C515C

Data Sheet

2003-02

two consecutive instructions which set the bits WDT and SWDT each. The reset cause
(external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle
mode and power down mode of the processor.

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

· Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is brought into reset; if the failure
condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC
oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the
oscillator to stabilize; then the oscillator watchdog reset is released and the part starts
program execution again.

· Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip
oscillator has started. The oscillator watchdog unit also works identically to the
monitoring function.

· Restart from the hardware power down mode

If the hardware power down mode is terminated the oscillator watchdog has to control
the correct start-up of the on-chip oscillator and to restart the program. The oscillator
watchdog function is only part of the complete hardware power down sequence;
however, the watchdog works identically to the monitoring function.

· Control of external wake-up from software power-down mode

When the software power-down mode is left by a low level at the P3.2/INT0 pin, the
oscillator watchdog unit assures that the microcontroller resumes operation
(execution of the power-down wake-up interrupt) with the nominal clock rate. In the
power-down mode the RC oscillator and the on-chip oscillator are stopped. Both
oscillators are started again when power-down mode is released. When the on-chip
oscillator has a higher frequency than the RC oscillator, the microcontroller starts
operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to
stabilize.

C515C

Data Sheet

2003-02

Power Saving Modes

The C515C provides two basic power saving modes, the idle mode and the power down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can be also used for further power
reduction in idle mode.

· Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock
and are able to work. Idle mode is entered by software and can be left by an interrupt
or reset.

· Power down mode

The operation of the C515C is completely stopped and the oscillator is turned off. This
mode is used to save the contents of the internal RAM with a very low standby current.
Software power down mode: Software power down mode is entered by software
and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC,
C515C-8E only).
Hardware power down mode: Hardware power down mode is entered when the pin
HWPD is put to low level.

· Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency
is internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32

of their normal operating frequency. Slowing down the frequency

significantly reduces power consumption. The slow down mode can be combined with
the idle mode.

Table 11

gives a general overview of the entry and exit conditions of the power saving

modes.

In the power down mode of operation,

can be reduced to minimize power

consumption. It must be ensured, however, that

is not reduced before the power

down mode is invoked, and that

is restored to its normal operating level, before the

power down mode is terminated.

If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports,
peripherals) remains preserved. If a power saving mode is left by a hardware reset, the
microcontroller state is disturbed and replaced by the reset state of the C515C.

If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively
selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1
is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software
power down mode.

For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.

C515C

Data Sheet

2003-02

Table 11

Power Saving Modes Overview

Mode

Entering
(2-Instruction
Example)

Leaving by

Remarks

Idle mode

ORL PCON, #01

ORL PCON, #20

Occurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Software
Power-Down
Mode

ORL PCON, #02

ORL PCON, #40

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM
and SFR's are maintained;

Short low pulse at
pin P3.2/INT0
(or P4.7/RXDC,
C515C-8E only)

Hardware
Power-Down
Mode

HWPD = low

HWPD = high

C515C is put into its reset
state and the oscillator is
stopped;
ports become floating
outputs

Slow Down
Mode

ORL PCON, #10

ANL PCON, #0EF

or
Hardware Reset

Oscillator frequency is
reduced to 1/32 of its
nominal frequency

C515C

Data Sheet

2003-02

OTP Memory Operation (C515C-8E only)

The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory.
With the C515C-8E fast programming cycles are achieved (1 byte in 100

s). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C515C-8E must be put into the programming mode.
This typically is done not in-system but in a special programming hardware. In the
programming mode the C515C-8E operates as a slave device similar as an EPROM
standalone memory device and must be controlled with address/data information,
control lines, and an external 11.5 V programming voltage.

Figure 25

shows the pins of

the C515C-8E which are required for controlling of the OTP programming mode.

Figure 25

Programming Mode Configuration of the C515C-8E

MCP03651

A0-7
A8-A15

PALE

PMSEL0
PMSEL1

XTAL1
XTAL2

P0-7

EA/

PROG
PRD

RESET
PSEN
PSEL

Port 2

Port 0

C515C-8E

C515C

Data Sheet

2003-02

C515C-8E Pin Configuration in Programming Mode

Figure 26

P-MQFP-80-1 Pin Configuration of the C515C-8E in Programming
Mode (top view)

MCP03652

1 2 3 4 5 6 7 8 9 10 11

N.C.

12 13 14 15 16 17 18 19 20

A2/A10

N.C.

PALE

PRD

PSEL

PMSEL1

PMSEL0

N.C.

RESET

A3/A11

A4/A12

A5/A13

A6/A14

A7/A15

N.C.

PSEN

PROG

EA/

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

39
38
37
36
35
34
33
32

31
30

29
28
27
26
25
24
23
22

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

N.C.

A1/A9
A0/A8
XTAL1
XTAL2

N.C.

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

N.C.

C515C-8E

N.C.

N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.

N.C.

C515C

Data Sheet

2003-02

The following

Table 12

contains the functional description of all C515C-8E pins which

are required for OTP memory programming.

Table 12

Pin Definitions and Functions in Programming Mode

Symbol

Pin Number I/O

Function

RESET

Reset
This input must be at static "0" (active) level during the
whole programming mode.

PMSEL0
PMSEL1

15
16

I
I

Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the logic
level of PMSEL1,0 is changed, PALE must be at low
level.

PSEL

17 I

Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according

Figure 27

PRD

Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.

PALE

Programming address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/from
the falling edge of PALE. PALE must be at low level
whenever the logic level of PMSEL1,0 is changed.

XTAL2

XTAL2
Input to the oscillator amplifier.

XTAL1

XTAL1
Output of the inverting oscillator amplifier.

PMSEL1

PMSEL0

Access Mode

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory
byte

C515C

Data Sheet

2003-02

A0/A8 -
A7/A15

38 - 45

Address lines
P2.0-7 are used as multiplexed address input lines
A0-A7 and A8-A15. A8-A15 must be latched with PALE.

PSEN

Program store enable
This input must be at static "0" level during the whole
programming mode.

PROG

Programming mode write strobe
This input is used in programming mode as a write
strobe for OTP memory program and lock bit write
operations. During basic programming mode selection
a low level must be applied to PROG.

EA/

External Access / Programming voltage
This pin must be at 11.5 V (

) voltage level during

programming of an OTP memory byte or lock bit. During
an OTP memory read operation this pin must be at high
level (

). This pin is also used for basic programming

mode selection. At basic programming mode selection
a low level must be applied to EA/

D0 - 7

52 - 58

I/O

Data lines 0-7
During programming mode, data bytes are read or
written from or to the C515C-8E via the bidirectional
D0-7 which are located at port 0.

13, 34, 35,
51, 70

Circuit ground potential
must be applied to these pins in programming mode.

14, 32, 33,
50, 69

Power supply terminal
must be applied to these pins in programming mode.

N.C.

2-12, 20-31,
46, 60-67,
69, 71-80

Not Connected
These pins should not be connected in programming
mode.

I = Input; O = Output

Table 12

Pin Definitions and Functions in Programming Mode (cont'd)

Symbol

Pin Number I/O

Function

C515C

Data Sheet

2003-02

C515C-8E Lock Bits Programming / Read

The C515C-8E has two programmable lock bits which, when programmed according

Table 14

, provide four levels of protection for the on-chip OTP code memory. The state

of the lock bits can also be read.

Table 13

Access Modes Selection

Access Mode

EA/

PROG

PRD

PMSEL

Address
(Port 2)

Data
(Port 0)

Program OTP memory
byte

A0-7
A8-15

D0-7

Read OTP memory byte

Program OTP lock bits

D1, D0
see

Table 14

Read OTP lock bits

Read OTP version byte

Byte addr.
of version
byte

D0-7

C515C

Data Sheet

2003-02

Table 14

Lock Bit Protection Types

Lock Bits at
D1, D0

Protection
Level

Protection Type

Level 0

The OTP lock feature is disabled. During normal
operation of the C515C-8E, the state of the EA pin is
not latched on reset.

Level 1

During normal operation of the C515C-8E, MOVC
instructions executed from external program memory
are disabled from fetching code bytes from internal
memory. EA is sampled and latched on reset. An OTP
memory read operation is only possible according to
ROM verification mode 2, as it is defined for a
protected ROM version of the C515C-8R. Further
programming of the OTP memory is disabled
(reprogramming security).

Level 2

Same as level 1, but also OTP memory read operation
using ROM verification mode 2 is disabled.

Level 3

Same as level 2; but additionally external code
execution by setting EA = low during normal operation
of the C515C-8E is no more possible.
External code execution, which is initiated by an
internal program (e.g. by an internal jump instruction
above the ROM boundary), is still possible.

C515C

Data Sheet

2003-02

Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage of the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for longer periods may
affect device reliability. During absolute maximum rating overload
conditions (

) the voltage on

pins with respect to

ground (

) must not exceed the values defined by the absolute maximum

ratings.

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Storage temperature

-65

150

Voltage on

pins with

respect to ground (

)

-0.5

6.5

Voltage on any pin with respect
to ground (

)

-0.5

+ 0.5

Input current on any pin during
overload condition

-10

Absolute sum of all input
currents during overload
condition

|100 mA|

Power dissipation

DISS

C515C

Data Sheet

2003-02

Operating Conditions

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Supply voltage

4.25

5.5

Active mode,

OSCmax

= 10 MHz

5.5

Power Down
mode

Ground voltage

Reference voltage

Ambient temperature:

SAB-C515C

SAF-C505

-40

SAH-C505

-40

110

Analog reference voltage

AREF

+ 0.1 V

Analog ground voltage

AGND

- 0.1

+ 0.2

Analog input voltage

AIN

AGND

AREF

XTAL clock

OSC

MHz

C515C

Data Sheet

2003-02

DC Characteristics (Operating Conditions apply)

Parameter

Sym-
bol

Limit Values

Unit Test

Condition

min.

max.

Input low voltages all except
EA, RESET, HWPD
EA pin
RESET and HWPD pins
Port 5 in CMOS mode

IL1

IL2

ILC

-0.5
-0.5
-0.5
-0.5

0.2

- 0.1

0.2

- 0.3

0.2

+ 0.1

0.3

Input high voltages
all except XTAL2, RESET,
and HWPD)
XTAL2 pin
RESET and HWPD pins
Port 5 in CMOS mode

IH1

IH2

IHC

0.2

+ 0.9

0.7

0.6

0.7

+ 0.5

Output low voltages
Ports 1, 2, 3, 4, 5, 7 (incl. CMOS)
Port 0, ALE, PSEN, CPUR
P4.1, P4.3 in push-pull mode

OL1

OL3

0.45
0.45
0.45

= 1.6 mA

= 3.2 mA

= 3.75 mA

Output high voltages
Ports 1, 2, 3, 4, 5, 7

Port 0 in external bus mode,
ALE, PSEN, CPUR
Port 5 in CMOS mode
P4.1, P4.3 in push-pull mode

OH2

OHC

OH3

2.4
0.9

0.9

= -80

= -10

= -800

= -80

= -800

= -833

Logic 0 input current
Ports 1, 2, 3, 4, 5, 7

-10

-70

= 0.45 V

Logical 0-to-1 transition current
Ports 1, 2, 3, 4, 5, 7

-65

-650

= 2 V

Input leakage current
Port 0, EA, P6, HWPD, AIN0-7

0.45 <

Input low current
To RESET for reset
XTAL2
PE/SWD

LI2

LI3

LI4

-100
-15
-20

= 0.45 V

Pin capacitance

= 1 MHz,

= 25

Overload current

3)4)

Programming voltage

10.9

12.1

11.5 V

C515C

Data Sheet

2003-02

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,
or use an address latch with a Schmitt-trigger strobe input.

Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified
operating range (i.e.

+ 0.5 V or

- 0.5 V). The absolute sum of input overload currents on

all port pins may not exceed 50 mA. The supply voltage (

and

) must remain within the specified limits.

Not 100% tested, guaranteed by design characterization.

C515C

Data Sheet

2003-02

Power Supply Current

Parameter

Sym-
bol

Limit Values

Unit Test Condition

typ.

The typical

values are periodically measured at

= +25

C and

= 5 V but not 100% tested.

max.

The maximum

values are measured under worst case conditions (

= 0

C or -40

C and

= 5.5 V)

Active mode

C515C-8R/
C515C-LM

6 MHz
10 MHz

11.97
18.81

13.74
21.10

(active mode) is measured with:

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

- 0.5 V; XTAL1 = N.C.;

EA = PE/SWD = Port 0 = Port 6 =

; HWPD =

; RESET =

; all other pins are disconnected.

C515C-8E

6 MHz
10 MHz

11.3
17.66

12.94
20.10

Idle mode

C515C-8R/
C515C-LM

6 MHz
10 MHz

6.9
10.46

7.87
11.87

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

- 0.5 V; XTAL1 = N.C.;

RESET =

; EA =

; Port0 =

; all other pins are disconnected;

C515C-8E

6 MHz
10 MHz

3.95
4.71

4.70
5.50

Active mode
with slow-down
enabled

C515C-8R/
C515C-LM

6 MHz
10 MHz

4.06
4.62

5.03
5.75

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;
XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

- 0.5 V; XTAL1 = N.C.;

RESET =

; all other pins are disconnected; the microcontroller is put into slow-down mode by software.

C515C-8E

6 MHz
10 MHz

4.01
4.65

4.77
5.53

Idle mode with
slow-down
enabled

C515C-8R/
C515C-LM

6 MHz
10 MHz

3.54
3.86

4.46
4.90

C515C-8E

6 MHz
10 MHz

3.62
4.14

4.21
4.77

Power-down
mode

C515C-8R/
C515C-LM

42.9

= 2 ... 5.5 V

C515C-8E

11.14

At EA/

programming
mode

C515C-8E

DDP

C515C

Data Sheet

2003-02

(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;
XTAL2 driven with

CLCH

CHCL

= 5 ns,

+ 0.5 V,

- 0.5 V; XTAL1 = N.C.;

RESET =

; EA =

; Port0 =

; all other pins are disconnected; the microcontroller is put into idle mode

with slow-down enabled by software.

(power-down mode) is measured under following conditions:

EA = RESET = Port 0 = Port 6 =

; XTAL1 = N.C.; XTAL2 =

; PE/SWD =

;

HWPD =

;

AGND

;

AREF

; all other pins are disconnected.

(hardware power-down mode) is independent of any particular pin connection.

C515C

Data Sheet

2003-02

Power Supply Current Calculation Formulas

Note:

OSC

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

C515C-8R/
C515C-LM

DD typ

DD max

1.71

OSC

+ 1.71

1.84

OSC

+ 2.7

C515C-8E

DD typ

DD max

1.59

OSC

+ 1.76

1.79

OSC

+ 2.2

Idle mode

C515C-8R/
C515C-LM

DD typ

DD max

0.89

OSC

+ 1.56

1.00

OSC

+ 1.87

C515C-8E

DD typ

DD max

0.19

OSC

+ 2.81

0.20

OSC

+ 3.5

Active mode with
slow-down enabled

C515C-8R/
C515C-LM

DD typ

DD max

0.14

OSC

+ 3.22

0.18

OSC

+ 3.95

C515C-8E

DD typ

DD max

0.16

OSC

+ 3.05

0.19

OSC

+ 3.63

Idle mode with slow-down
enabled

C515C-8R/
C515C-LM

DD typ

DD max

0.08

OSC

+ 3.06

0.11

OSC

+ 3.8

C515C-8E

DD typ

DD max

0.13

OSC

+ 2.84

0.14

OSC

+ 3.37

C515C

Data Sheet

2003-02

A/D Converter Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

Analog input voltage

AIN

AGND

AREF

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

Sample time

Prescaler

During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion result.

Conversion cycle time

ADCC

Prescaler

This parameter includes the sample time

, the time for determining the digital result and the time for the

calibration. Values for the conversion clock

ADC

depend on programming and can be taken from the table on

the previous page.

Total unadjusted error

LSB

is tested at

AREF

= 5.0 V,

AGND

= 0 V,

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

Internal resistance of
reference voltage source

AREF

ADC

/ 250

- 0.25

ADC

in [ns]

5)6)

During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

Not 100% tested, but guaranteed by design characterization.

Internal resistance of
analog source

ASRC

/ 500

- 0.25

in [ns]

2)6)

ADC input capacitance

AIN

C515C

Data Sheet

2003-02

AC Characteristics (Operating Conditions apply)

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Unit

10-MHz Clock

Duty Cycle

0.4 to 0.6

Variable Clock
1/CLP = 2 MHz

to 10 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLP - 40

Address setup to ALE

AVLL

TCL

Hmin

- 25

Address hold after ALE

LLAX

TCL

Hmin

- 25

ALE to valid instruction
in

LLIV

113

2 CLP - 87

ALE to PSEN

LLPL

TCL

Lmin

- 20

PSEN pulse width

PLPH

115

CLP +
TCL

Hmin

- 30

PSEN to valid
instruction in

PLIV

CLP +
TCL

Hmin

- 65

Input instruction hold
after PSEN

PXIX

Input instruction float
after PSEN

PXIZ

Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

TCL

Lmin

- 10 ns

Address valid after
PSEN

PXAV

TCL

Lmin

- 5

Address to valid
instruction in

AVIV

180

2 CLP +
TCL

Hmin

- 60

Address float to PSEN

AZPL

C515C

Data Sheet

2003-02

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

10-MHz Clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 10 MHz

min.

max.

min.

max.

RD pulse width

RLRH

230

3 CLP - 70

WR pulse width

WLWH

230

3 CLP - 70

Address hold after
ALE

LLAX2

CLP

- 15

RD to valid data in

RLDV

150

2 CLP +
TCL

Hmin

- 90

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP - 20

ALE to valid data in

LLDV

267

4 CLP - 133

Address to valid data
in

AVDV

285

4 CLP +
TCL

Hmin

- 155

ALE to WR or RD

LLWL

190

CLP +
TCL

Lmin

- 50

CLP +
TCL

Lmin

+ 50

Address valid to WR

AVWL

103

2 CLP - 97

WR or RD high to
ALE high

WHLH

TCL

Hmin

- 25

TCL

Hmin

+ 25

Data valid to WR
transition

QVWX

TCL

Lmin

- 35

Data setup before
WR

QVWH

218

3 CLP +
TCL

Lmin

- 122

Data hold after WR

WHQX

TCL

Hmin

- 27

Address float after
RD

RLAZ

C515C

Data Sheet

2003-02

Note: The 10 MHz values in the tables are given as an example for a typical duty cycle

variation of the oscillator clock from 0.4 to 0.6.

SSC Interface Characteristics

Parameter

Symbol

Limit Values

Unit

min.

max.

Clock Cycle Time:
Master Mode
Slave Mode

SCLK

0.4
1.0

Clock high time

SCH

360

Clock low time

SCL

360

Data output delay

100

Data output hold

Data input setup

100

Data input hold

100

TC bit set delay

DTC

8 CLP

External Clock Drive at XTAL2

Parameter

Symbol CPU Clock = 10 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 10 MHz

Unit

min.

max.

min.

max.

Oscillator period CLP

100

500

High time

TCL

CLP - TCL

Low time

TCL

CLP - TCL

Rise time

Fall time

Oscillator duty
cycle

0.4

0.6

40 / CLP

1 - 40 / CLP

Clock cycle

TCL

CLP

min

CLP

max

C515C

Data Sheet

2003-02

Figure 34

SSC Timing

Notes:

1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is

valid for the other cases accordingly.

2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the

falling edge of SLS (if transmitter is enabled).

3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data

has been written into the shift register, i.e. at least one half SCLK clock cycle before
the first clock transition.

MCT02417

SCLK

STO

SRI

SCL

MSB

LSB

MSB

LSB

SCH

SCLK

~ ~

DTC

C515C

Data Sheet

2003-02

OTP Memory Programming Mode Characteristics

= 5 V

10%;

= 11.5 V

5%;

= 25

Parameter

Symbol

Limit Values

Unit

min.

max.

ALE pulse width

PAW

PMSEL setup to ALE rising edge

PMS

Address setup to ALE, PROG, or PRD
falling edge

PAS

Address hold after ALE, PROG, or PRD
falling edge

PAH

Address, data setup to PROG or PRD

PCS

100

Address, data hold after PROG or PRD

PCH

PMSEL setup to PROG or PRD

PMS

PMSEL hold after PROG or PRD

PMH

PROG pulse width

PWW

100

PRD pulse width

PRW

100

Address to valid data out

PAD

PRD to valid data out

PRD

Data hold after PRD

PDH

Data float after PRD

PDF

PROG high between two consecutive
PROG low pulses

PWH1

PRD high between two consecutive PRD
low pulses

PWH2

100

XTAL clock period

CLKP

MHz

C515C

Data Sheet

2003-02

ROM/OTP Verification Characteristics for C515C-8R / C515C-8E

Figure 39

ROM Verification Mode 1

ROM Verification Mode 1 (C515C-8R)

Parameter

Symbol

Limit Values

Unit

min.

max.

Address to valid data

AVQV

5 CLP

MCT02764

Inputs: PSEN =

ALE, EA = V

RESET = V

IL2

Address

Port 0

New Address

Data Out

New Data Out

AVQV

Data:
Addresses:

P2.0 - P2.7

P1.0 - P1.7

P1.0 - P1.7 = A0 - A7
P2.0 - P2.7 = A8 - A15

P0.0 - P0.7 = D0 - D7

C515C

Data Sheet

2003-02

Figure 40

ROM/OTP Verification Mode 2

Parameter

Symbol

Limit Values

Unit

min.

typ.

max.

ALE pulse width

AWD

CLP

ALE period

ACY

6 CLP

Data valid after ALE

DVA

2 CLP

Data stable after ALE

DSA

4 CLP

P3.5 setup to ALE low

Oscillator frequency

1 / CLP

MHz

MCT02613

ACY

AWD

DSA

DVA

Data Valid

ALE

Port 0

P3.5

C515C

Data Sheet

2003-02

Figure 41

AC Testing: Input, Output Waveforms

Figure 42

AC Testing: Float Waveforms

Figure 43

Recommended Oscillator Circuits for Crystal Oscillator

AC Inputs during testing are driven at

- 0.5 V for a logic `1' and 0.45 V for a logic `0'.

Timing measurements are made at

IHmin

for a logic `1' and

ILmax

for a logic `0'.

0.45 V

0.2

- 0.1

+ 0.9

0.2

Test Points

MCT00039

- 0.5 V

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.

20 mA

MCT02765

XTAL1

XTAL2

XTAL1

Crystal/Resonator Oscillator Mode

Driving from External Source

External Oscillator
Signal

N.C.

2 - 10 MHz

C = 20 pF ± 10 pF (incl. stray capacitance)

Crystal Mode

:
:

Resonator Mode

= depends on selected ceramic resonator

C515C

Data Sheet

2003-02

Package Outlines

0.65

0.3

12.35

0.1

2.45 max

Index Marking

17.2

0.25 min

+0.1

0.88

0.6x45°

1) Does not include plastic or metal protrusions of 0.25 max per side

A-B

0.2

A-B

0.2

D 80x

0.12

80x

A-B

17.2

-0.05

7°max

-0.02

+0.08

0.15

±0.08

P-MQFP-80-1
(Plastic Metric Quad Flat Package)

GPM05249

You can find all of our packages, sorts of packing and others in our
Infineon Internet Page "Products": http://www.infineon.com/products.

Dimensions in mm

SMD = Surface Mounted Device

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: C515C

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: C515C

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: C515C