Edition 2004-12-28
Published by Infineon Technologies AG,

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Infineon Technologies AG 1999.

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CCM-PFC

Revision History:

2004-12-28

Datasheet

Previous Version:

CCM-PFC

ICE1PCS02

ICE1PCS02G

Version 1.1

28 Dec 2004

Type

Package

ICE1PCS02

PG-DIP-8-4

ICE1PCS02G

PG-DSO-8-13

Standalone Power Factor Correction (PFC)
Controller in Continuous Conduction Mode
(CCM) with Input Brown-Out Protection

ICE1PCS02

PG-DIP-8-4

ICE1PCS02G

PG-DSO-8-13

Product Highlights

· Leadfree DIP and DSO Package
· Wide Input Range
· Direct sensing, Input Brown-Out Detection
· Optimized for applications which require fast Startup
· Output Power Controllable by External Sense Resistor
· Fast Output Dynamic Response during Load Jumps
· Trimmed, internal fixed Switching Frequency (65kHz)

Features

· Ease of Use with Few External Components
· Supports Wide Input Range
· Average Current Control
· External Current and Voltage Loop Compensation

for Greater User Flexibility

· Trimmed internal fixed Switching Frequency

(65kHz +7.7% at 25

· Direct sensing, Input Brown-Out Detection

with Hysteresis

· Short Startup(SoftStart) duration
· Max Duty Cycle of 97% (typ)
· Trimmed Internal Reference Voltage (5V+2%)
· VCC Under-Voltage Lockout

· Cycle by Cycle Peak Current Limiting
· Over-Voltage Protection
· Open Loop Detection
· Soft Overcurrent Protection
· Enhanced Dynamic Response
· Fulfills Class D Requirements of IEC 1000-3-2

Description

The ICE1PCS02/G is a 8-pin wide input range controller
IC for active power factor correction converters. It is de-
signed for converters in boost topology, and requires few
external components. Its power supply is recommended
to be provided by an external auxiliary supply which will
switch on and off the IC.
The IC operates in the CCM with average current control,
and in DCM only under light load condition. The switching
frequency is trimmed and fixed internally at 65kHz. Both
current and voltage loop compensations are done exter-
nally to allow full user control.
There are various protection features incorporated to en-
sure safe system operation conditions. The internal refer-

ence is trimmed (5V+2%) to ensure precise protection and
output control level.
The ICE1PCS02/G is a design variant of ICE1PCS01 to
incorporate the new input brown-out protection function
and optimised to have a faster startup time with controlled
peak startup current.

85 ... 265 VAC

EMI-Filter

Voltage Loop

Compensation

Protection Unit

Fixed

Oscillator

Current Loop

Compensation

PWM Logic

Driver

ICE1PCS02 /G

CCM PFC

VCC

Auxiliary Supply

OUT

Typical Application

Ramp

Generator

ICOMP

VSENSE

VCOMP

ISENSE

GND

Nonlinear

Gain

GATE

VINS

Brown-out

CCM-PFC

ICE1PCS02/G

Version 1.1

28 Dec 2004

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.1

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3

Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.4

System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.1

Input Brown-Out Protection (IBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.4.2

Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.3

Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.4

Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.4.5

Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.5

Fixed Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6

Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.6.1

Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.6.2

Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6.3

Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.6.4

Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.7

PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8

Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8.1

Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8.2

Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.9

Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.2

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.3

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3.1

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3.2

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3.3

System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.3.4

Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.3.5

Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.3.6

Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Version 1.1

28 Dec 2004

CCM-PFC

ICE1PCS02/G

Pin Configuration and Functionality

1.1

Pin Configuration

Figure1

Pin Configuration (top view)

1.2

Pin Functionality

GND (Ground)
The ground potential of the IC.

ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control

loop. The capacitor which is connected at this pin
integrates the output current of OTA2 and averages the
current sense signal.

ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (R1). This is the input signal for
the average current regulation in the current loop. It is
also fed to the peak current limitation block.
During power up time, high inrush currents cause high
voltage drop at R1, driving currents into pin 3 which
could be beyond the absolute maximum ratings.
Therefore a series resistor (R2) of around 220

recommended in order to limit this current into the IC.

VINS (Brown-out Sense Input)
This VINS pin senses a filtered input voltage divider

and detects for the input voltage Brown-out condition.
A Brown-out condition of VINS<0.8V, shuts down the
IC. The IC turns on at VINS>1.5V.

VSENSE (Voltage Sense/Feedback)
The output bus voltage is sensed at this pin via a
resistive divider. The reference voltage for this pin is
5V.

VCOMP (Voltage Loop Compensation)
This pin provides the compensation of the output
voltage loop with a compensation network to ground
(see Figure 2).

VCC (Power Supply)
The VCC pin is the positive supply of the IC and should
be connected to an external auxiliary supply. The
operating range is between 10V and 21V. The turn-on
threshold is at 11.2V and under voltage occurs at
10.2V. There is no internal clamp for a limitation of the
power supply.

GATE
The GATE pin is the output of the internal driver stage,
which has a capability of 1.5A source and sink current.
Its gate drive voltage is internally clamped at 11.5V
(typically).

Pin

Symbol

Function

GND

IC Ground

ICOMP

Current Loop Compensation

ISENSE Current Sense Input

VINS

Brown-out Sense Input

VCOMP Voltage Loop Compensation

VSENSE V

O U T

Sense (Feedback) Input

VCC

IC Supply Voltage

GATE

Gate Drive Output

Package PG-DIP-8-4 / PG-DSO-8-13

GATE

GND

ICOMP

ISENSE

VCC

VSENSE

VINS

VCOMP

CCM-PFC

ICE1PCS02/G

Functional Description

Version 1.1

28 Dec 2004

3.1

General

The ICE1PCS02/G is a 8 pin control IC for power factor
correction converters. It comes in both DIP and DSO

packages and is suitable for wide range line input
applications from 85 to 265 VAC. The IC supports
converters in boost topology and it operates in
continuous conduction mode (CCM) with average
current control.
It is a design derivative from the ICE1PCS01/G with the
differences in the supporting functions, namely the
input brown-out detection, internal fixed switching
frequency 65kHz and shortened startup time.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner

current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics but still meeting
the Class D requirement of IEC 1000-3-2.
The outer voltage loop controls the output bus voltage.
Depending on the load condition, OTA1 establishes an
appropriate voltage at VCOMP pin which controls the

amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.

3.2

Power Supply

An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
11.2V and both voltages at pin 6 (VSENSE) >0.8V and
pin 4 (VINS) >1.5V, the IC begins operating its gate
drive and performs its Startup as shown in Figure 3.
.

Figure3

State of Operation respect to VCC

If VCC drops below 10.2V, the IC is off. The IC will then
be consuming typically 200

A, whereas consuming

18mA during normal operation.
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 6 (VSENSE) to lower
than 0.8V. In this standby mode, the current
consumption is reduced to 3mA. Other condition that
can result in the standby mode is when a Brown-out
condition occurs, ie pin 4 (VINS) <0.8V.

3.3

Start-up

Figure 4 shows the operation of voltage loop's OTA1
during startup. The VCOMP pin is pull internally to
ground via switch S1 during UVLO and other fault
conditions (see later section on "System Protection").
During power up when V

OUT

is less than 85% of the

rated level, it sources a constant 30

A into the

compensation network at pin 5 (VCOMP) causing the
voltage at this pin to rise linearly. This results in a
controlled linear increase of the input current from 0A
thus reducing the stress on the external component.

Figure4

Startup Circuit

As V

OUT

has not reached within 5% from the rated

value, VCOMP voltage is level-shifted by the window
detect block as shown in Figure 5, to ensure there is no
long period of low or no current.
When V

OUT

approaches its rated value, OTA1's

sourcing current drops and so does the level shift of the
window detect block. The normal voltage loop then
takes control.

VSENSE

> 0.8 V)

AND (V

VINS

> 1.5 V)

11.2 V

10.5 V

OFF

Start
Up

Open loop/

Standby

Normal

Operation

IC's
State

OFF

Normal

Operation

VSENSE

< 0.8 V)

OR (V

VINS

< 0.8 V)

VSENSE

> 0.8 V)

AND (V

VINS

> 1.5 V)

VCOMP

VSENSE

OTA1

ICE1PCS02/G

fault

R3 + R4

x V

OUT

)

(

+/-30uA, 42uS

Functional Description

CCM-PFC

ICE1PCS02/G

Functional Description

Version 1.1

28 Dec 2004

Figure5

Startup with controlled maximum current

ICE1PCS02/G is different from ICE1PCS01/G in this
block as it does not has a reduced current (~10uA in
ICE1PCS01/G) during startup. The OTA1 in

ICE1PCS02/G has the same maximum source current
of 30uA (typ) in startup as in the normal operation. This
higher sourcing current in the startup time, will charge
VCOMP faster to its normal operating point, which in
turn results in a faster startup for V

OUT

3.4

System Protection

The IC provides several protection features in order to

ensure the PFC system in safe operating range:
· VCC Undervoltage Lockout (UVLO)
· Input Brown-out Detection (IBOP)
· Soft Over Current Control (SOC)
· Peak Current Limit (PCL)
· Open-Loop Detection (OLP)
· Output Over-Voltage Protection (OVP)
After the system is supplied with the correct level of
VCC and V

I N

, the system will enter into its normal mode

of operation. Figure 6 shows situation when these
protections features are active, as a function of the
output voltage V

OUT

An activation of the UVLO, IBOP and OLP results in the
internal fault signal going high and brings the IC into the
standby mode.
As the function of UVLO has already described in the
earlier "Power Supply" section, the following sections
continue to describe the functionality of these
protection features.

Figure6

Protection Features

3.4.1

Input Brown-Out Protection (IBOP)

Brown-out occurs when the input voltage V

falls below

the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the VCC has not
entered into the V

CCUVLO

level yet. For a system without

IBOP, the boost converter will increasingly draw a

higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
ICE1PCS02/G provides a new IBOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network as shown in Figure 7. This network provides a
filtered value of V

which turns the IC on when the

voltage at pin 4 (VINS) is more than 1.5V. The IC enters
into the standby mode when VINS goes below 0.8V.
The hysteresis prevents the system to oscillate

between normal and standby mode. Note also that V

I N

needs to at least 16% of the rated V

OUT

in order to

overcome OLP and powerup the system.

Figure7

Input Brown-Out Protection (IBOP)

av(I

)

OUT

=rated

95%rated

Window Detect

Normal Control

Max Vcomp current

85%rated

VCOMP

Level-shifted VCOMP

OUT

PCL / SOC

16%

100%

OLP

105%

OVP

OUT,Rated

UVLO / IBOP

Supply

related
Current

related
Output

ICE1PCS02/G

85 ... 265 VAC

Vin

D2 ... D5

VINS

1.5V

0.8V

Brown-Out Detection

brown-out

20k

CCM-PFC

ICE1PCS02/G

Functional Description

Version 1.1

28 Dec 2004

3.4.2

Soft Over Current Control (SOC)

The IC is designed not to support any output power
that corresponds to a voltage lower than -0.73V at the
ISENSE pin. A further increase in the inductor current,
which results in a lower ISENSE voltage, will activate
the Soft Over Current Control (SOC). This is a soft
control as it does not directly switch off the gate drive
like the PCL. It acts on the nonlinear gain block to result
in a reduced PWM duty cycle.

3.4.3

Peak Current Limit (PCL)

The IC provides a cycle by cycle peak current limitation

(PCL). It is active when the voltage at pin 3 (ISENSE)
reaches -1.08V. This voltage is amplified by OP1 by a
factor of -1.43 and connected to comparator C2 with a
reference voltage of 1.5V as shown in Figure 8. A
deglitcher with 300ns after the comparator improves
noise immunity to the activation of this protection.

Figure8

Peak Current Limit (PCL)

3.4.4

Open Loop Protection (OLP)

Whenever VSENSE voltage falls below 0.8V, or
equivalently V

O U T

falls below 16% of its rated value, it

indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V

for

normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using

comparator C3 with a threshold of 0.8V as shown in the
IC block diagram in Figure 2.

3.4.5

Over-Voltage Protection (OVP)

Whenever V

O U T

exceeds the rated value by 5%, the

over-voltage protection OVP is active as shown in
Figure 6. This is implemented by sensing the voltage at
pin VSENSE with respect to a reference voltage of
5.25V. A VSENSE voltage higher than 5.25V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower

input power to reduce the output voltage V

OUT

3.5

Fixed Switching Frequency

ICE1PCS02/G has an internally fixed switching
frequency as opposed to the ICE1PCS01/G which can
be externally set. This frequency is trimmed to 65kHz
with an accuracy +/-7.7% at 25

3.6

Average Current Control

3.6.1

Complete Current Loop

The complete system current loop is shown in Figure 9.

Figure9

Complete System Current Loop

It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.

3.6.2

Current Loop Compensation

The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
9). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4V in the event
of standby mode.

3.6.3

Pulse Width Modulation (PWM)

The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.

ISENSE

ICE1PCS02/G

R 2

INDUCTOR

OP1

1.43x

Current Limit

300ns

Deglitcher

Turn Off

Driver

1.5V

Full-wave

Rectifier

R
S

ICE1PCS02/G

Vout

Gate

Driver

From

Full-wave

Retifier

GATE

OTA2

ICOMP

Current Loop

Compensation

Current Loop

Nonlinear

Gain

1.1mS
+/-50uA (linear range)

Fault

ISENSE

PWM

Comparator

PWM Logic

Input From

Voltage Loop

voltage

proportional to

averaged

Inductor current

CCM-PFC

ICE1PCS02/G

Functional Description

Version 1.1

28 Dec 2004

Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D

O F F

for a

CCM PFC system is given as

From the above equation, D

O F F

is proportional to V

I N

The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D

OFF

, and thus to the input voltage

I N

. Figure 10 shows the scheme to achieve the

objective.

Figure10

Average Current Control in CCM

The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T

OFFMIN

(250ns typ.) and the ramp is

kept discharged. The ramp is then allowed to rise after
T

OFFMIN

expires. The off time of the boost transistor

ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current

and the off duty cycle D

OFF

Figure 11 shows the timing diagrams of T

OFFMIN

and the

PWM waveforms.

Figure11

Ramp and PWM waveforms

3.6.4

Nonlinear Gain Block

The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).

3.7

PWM Logic

The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on

the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T

OFFMIN

are designed to meet a maximum duty cycle D

MAX

95% at the GATE output.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 12.

Figure12

PWM Logic

3.8

Voltage Loop

The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V

OUT

. This loop is closed by the feedback

sensing voltage at VSENSE which is a resistive divider
tapping from V

OUT

. The pin VSENSE is the input of

OTA1 which has an accurate internal reference of 5V
(+/-2%). Figure 13 shows the important blocks of this
voltage loop.

3.8.1

Voltage Loop Compensation

The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 13). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.

OFF

O U T

--------------

ave(I

) at ICOMP

ramp profile

GATE

drive

OFFMIN

250ns

CREF

(1)

RAMP

PWM

ramp

released

PWM cycle

(1)

CREF

is a function of V

ICOMP

Peak Current

Limit

Current Loop

PWM on signal

Toffmin

250ns

Current

Limit Latch

PWM on

Latch

HIGH =

turn GATE on

CCM-PFC

ICE1PCS02/G

Functional Description

Version 1.1

28 Dec 2004

Figure13

Voltage Loop

3.8.2

Enhanced Dynamic Response

Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a "window detector" for the
feedback voltage V

VSENSE

at pin 6 (VSENSE).

Whenever V

VSENSE

exceeds the reference value (5V)

by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of V

OUT

3.9

Output Gate Driver

The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 14) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 11.5V.

Figure14

Gate Driver

The output is active HIGH and at VCC voltages below
the under voltage lockout threshold V

CCUVLO

, the gate

drive is internally pull low to maintain the off state.

VCOMP

VSENSE

OTA1

Av(I

)

Nonlinear

Gain

ICE1PCS02/G

Vout

Gate Driver

Current Loop

PWM Generation

From

Full-wave

Retifier

GATE

External
MOS

VCC

Gate Driver

PWM Logic
HIGH to
turn on

* LV: Level Shift

ICE1PCS02/G

CCM-PFC

ICE1PCS02/G

Electrical Characteristics

Version 1.1

28 Dec 2004

Electrical Characteristics

4.1

Absolute Maximum Ratings

Note:

Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit.

4.2

Operating Range

Note:

Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Supply Voltage

-0.3

VINS Voltage

VINS

-0.3

ICOMP Voltage

ICOMP

-0.3

ISENSE Voltage

ISENSE

-24

ISENSE Current

ISENSE

-1

Recommended R2=220

VSENSE Voltage

VSENSE

-0.3

VSENSE Current

VSENSE

-1

R3>400k

VCOMP Voltage

VCOMP

-0.3

GATE Voltage

GATE

-0.3

Clamped at 11.5V(typ)
if driven internally.

Junction Temperature

-40

150

Storage Temperature

-55

150

Thermal Resistance
Junction-Ambient for PG-DSO-8-13

thJA

(DSO)

185

K/W

PG-DSO-8-13

Thermal Resistance

Junction-Ambient for PG-DIP-8-4

thJA

(DIP)

K/W

PG-DIP-8-4

ESD Protection

ESD

Human Body Model

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k

series resistor)

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Supply Voltage

CCUVLO

Junction Temperature

JCon

-40

125

CCM-PFC

ICE1PCS02/G

Electrical Characteristics

Version 1.1

28 Dec 2004

4.3

Characteristics

Note:

The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range

from 40

C to 125

C.Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of

C C

=15V is assumed for test condition.

4.3.1

Supply Section

4.3.2

PWM Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

VCC Turn-On Threshold

CCon

10.5

11.2

11.9

VCC Turn-Off Threshold/
Under Voltage Lock Out

CCUVLO

9.4

10.2

10.8

VCC Turn-On/Off Hysteresis

CChy

0.8

1.3

Start Up Current

Before V

CCon

CCstart

100

200

VCC

VCCon

-0.1V

Operating Current with active GATE

CCHG

9.6

16.3

= 4.7nF

Operating Current during Standby

CCStdby

1.7

2.3

2.9

VSENSE

= 0.5V

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

Fixed Oscillator Frequency

kHz

kHz T

= 25°C

Max. Duty Cycle

MAX

99.3

Min. Duty Cycle

MIN

V C O M P

= 0V, V

VSENSE

= 5V

ICOMP

= 6.4V

Min. Off Time

OFFMIN

100

250

600

V C O M P

= 5V, V

VSENSE

= 5V

ISENSE

= 0.1V

CCM-PFC

ICE1PCS02/G

Electrical Characteristics

Version 1.1

28 Dec 2004

4.3.3

System Protection Section

4.3.4

Current Loop Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

Open Loop Protection (OLP)
VSENSE Threshold

OLP

0.77

0.81

0.86

Peak Current Limitation (PCL)
ISENSE Threshold

PCL

-1.15

-1.08

-1.00

Soft Over Current Control (SOC)
ISENSE Threshold

SOC

-0.79

-0.73

-0.66

Output Over-Voltage Protection (OVP)

OVP

5.12

5.25

5.38

Input Brown-out Protection (IBOP)
High to Low Threshold

VINSL

0.76

0.82

0.88

Input Brown-out Protection (IBOP)

Low to High Threshold

VINSH

1.40

1.50

1.60

Input Brown-out Protection (IBOP)
VINS Bias Current

VIN0V

-1.0

-0.2

VINS

= 0V

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

OTA2 Transconductance Gain

OTA2

0.75

0.95

1.15

mS At Temp = 25°C

OTA2 Output Linear Range

The parameter is not subject to production test - verified by design/characterization

OTA2

+/- 50

ICOMP Voltage during OLP

ICOMPF

3.6

4.0

VSENSE

= 0.5V

CCM-PFC

ICE1PCS02/G

Electrical Characteristics

Version 1.1

28 Dec 2004

4.3.5

Voltage Loop Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

OTA1 Reference Voltage

OTA1

4.90

5.00

5.10

OTA1 Transconductance Gain

OTA1

31.5

52.5

OTA1 Max. Source Current
At Startup

OTA1SO1

A V

VSENSE

= 4V

VCOMP

= 0V

OTA1 Max. Source Current
Under Normal Operation

OTA1SO

VSENSE

= 4.25V

V C O M P

= 4V

OTA1 Max. Sink Current
Under Normal Operation

OTA1SK

VSENSE

= 6V

V C O M P

= 4V

Enhanced Dynamic Response
VSENSE High Threshold
VSENSE Low Threshold

H i

5.12
4.63

5.25
4.75

5.38
4.87

V
V

VSENSE Input Bias Current at 5V

VSEN5V

1.5

VSENSE

= 5V

VSENSE Input Bias Current at 1V

VSEN1V

VSENSE

= 1V

VCOMP Voltage during OLP

VCOMPF

0.2

0.4

VSENSE

= 0.5V

V C O M P

= 0.5mA

CCM-PFC

ICE1PCS02/G

Electrical Characteristics

Version 1.1

28 Dec 2004

4.3.6

Driver Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

GATE Low Voltage

GATEL

1.2

C C

= 5 V

GATE

= 5 mA

1.5

C C

= 5 V

GATE

= 20 mA

0.8

GATE

= 0 A

1.6

2.0

GATE

= 20 mA

-0.2

0.2

GATE

= -20 mA

GATE High Voltage

GATEH

11.5

C C

= 20V

= 4.7nF

10.5

C C

= 11V

= 4.7nF

7.5

C C

= V

VCCoff

+ 0.2V

= 4.7nF

GATE Rise Time

Gate

= 2V ...8V

= 4.7nF

GATE Fall Time

Gate

= 8V ...2V

= 4.7nF

GATE Current, Peak,

Rising Edge

GATE

-1.5

= 4.7nF

Design characteristics (not meant for production testing)

GATE Current, Peak,

Falling Edge

GATE

1.5

= 4.7nF

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nicht nur um die Produktqualität
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direct our efforts equally at quality of
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