BTS
716G
Infineon Technologies AG
1 of 14
2003-Oct-01
Smart High-Side Power Switch
Four Channels: 4 x 140m
Status Feedback
Product Summary Package
Operating Voltage
V
bb
5.5
...40V
Active channels one
four parallel
On-state Resistance
R
ON
140m
35m
Nominal load current
I
L(NOM)
2.6A
5.3A
Current limitation
I
L(SCr)
6.5A
6.5A
General Description
N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and
diagnostic feedback, monolithically integrated in Smart SIPMOS
technology.
Providing embedded protective functions
Applications
C compatible high-side power switch with diagnostic feedback for 12V and 24V grounded loads
All types of resistive, inductive and capacitve loads
Most suitable for loads with high inrush currents, so as lamps
Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
Very low standby current
CMOS compatible input
Improved electromagnetic compatibility (EMC)
Fast demagnetization of inductive loads
Stable behaviour at undervoltage
Wide operating voltage range
Logic ground independent from load ground
Protection
Functions
Block Diagram
Short circuit protection
Overload protection
Current
limitation
Thermal
shutdown
Overvoltage protection (including load dump) with external
resistor
Reverse battery protection with external resistor
Loss of ground and loss of V
bb
protection
Electrostatic discharge protection (ESD)
Diagnostic Function
Diagnostic feedback with open drain output
Open load detection in OFF-state
Feedback of thermal shutdown in ON-state
P-DSO-20
Vbb
Logic
Channel 3
Channel 4
GND
Load 1
Load 2
Logic
Channel 1
Channel 2
Load 4
Load 3
IN1
ST1/2
IN2
IN3
ST3/4
IN4
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716G
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2003-Oct-01
Functional diagram
.
channel 1
OUT1
overvoltage
protection
logic
internal
voltage supply
ESD
temperature
sensor
clamp for
inductive load
gate
control
+
charge
pump
current limit
reverse
battery
protection
Open load
detection
control and protection circuit
of
channel 2
control and protection circuit
of
channel 3
control and protection circuit
of
channel 4
IN1
VBB
GND1/2
IN2
IN3
IN4
ST3/4
OUT2
OUT3
OUT4
LOAD
GND3/4
ST1/2
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716G
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2003-Oct-01
Pin Definitions and Functions
Pin
Symbol Function
1,10,
11,12,
15,16,
19,20
V
bb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
3 IN1
5 IN2
7 IN3
9 IN4
Input 1,2,3,4 activates channel 1,2,3,4 in case
of logic high signal
18 OUT1
17 OUT2
14 OUT3
13 OUT4
Output 1,2,3,4 protected high-side power output
of channel 1,2,3,4. Design the wiring for the
max. short circuit current
4 ST1/2
Diagnostic feedback 1/2,3/4 of channel 1,2,3,4
8
ST3/4
open drain, low on failure
2 GND1/2
Ground of chip 1 (channel 1,2)
6 GND3/4
Ground of chip 2 (channel 3,4)
Pin configuration
(top view)
V
bb
1
20 V
bb
GND1/2 2
19 V
bb
IN1 3
18 OUT1
ST1/2 4
17 OUT2
IN2 5
16 V
bb
GND3/4 6
15 V
bb
IN3 7
14 OUT3
ST3/4 8
13 OUT4
IN4 9
12 V
bb
V
bb
10
11 V
bb
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716G
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2003-Oct-01
Maximum Ratings
at T
j
= 25C unless otherwise specified
Parameter Symbol
Values
Unit
Supply voltage (overvoltage protection see page 6)
V
bb
43
V
Supply voltage for full short circuit protection
T
j,start
=
-40 ...+150C
V
bb
36
V
Load current (Short-circuit current, see page 6)
I
L
self-limited
A
Load dump protection
1
)
V
LoadDump
= V
A
+ V
s
, V
A
= 13.5 V
R
I
2
)
= 2
, t
d
= 400
ms; IN
= low or high,
each channel loaded with R
L
=
13.5
,
V
Load
dump
3
)
60
V
Operating temperature range
Storage temperature range
T
j
T
stg
-40 ...+150
-55 ...+150
C
Power dissipation (DC)
4)
T
a
= 25C:
(all channels active)
T
a
= 85C:
P
tot
3.6
1.9
W
Maximal switchable inductance, single pulse
V
bb
=
12V, T
j,start
=
150C
4)
,
see diagrams on page 10
I
L
=
2.3
A, E
AS
=
76 mJ, 0
one
channel:
I
L
=
3.3
A, E
AS
=
182 mJ, 0
two parallel channels:
I
L
=
4.7
A, E
AS
=
460 mJ, 0
four parallel channels:
Z
L
21
25
30
mH
Electrostatic discharge capability (ESD)
IN:
(Human Body Model)
ST:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5k
; C=100pF
V
ESD
1.0
4.0
8.0
kV
Input voltage (DC)
see internal circuit diagram page 9
V
IN
-10 ... +16
V
Current through input pin (DC)
Pulsed current through input pin
5
)
Current through status pin (DC)
I
IN
I
IN
I
ST
0.3
5.0
5.0
mA
1
) Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150
resistor for the GND connection is recommended.
2)
R
I
= internal resistance of the load dump test pulse generator
3)
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
4
) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70
m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
5
) only for testing
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2003-Oct-01
Thermal Characteristics
Parameter and Conditions Symbol
Values
Unit
min typ
max
Thermal resistance
junction - soldering point
6)7)
each
channel:
R
thjs
-- --
17
K/W
junction ambient
6)
@ 6 cm
2
cooling area
one channel active:
all channels active:
R
thja
--
--
--
--
44
35
--
--
--
Electrical Characteristics
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= -40...+150C, V
bb
= 12 V unless otherwise specified
min typ
max
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT);
IL = 2 A
each channel, T
j
= 25C:
T
j
= 150C:
two parallel channels, T
j
= 25C:
four parallel channels, T
j
= 25C:
see diagram, page 11
R
ON
--
--
--
--
110
210
55
28
140
280
70
35
m
Nominal load current
one channel active:
two parallel channels active:
four parallel channels active:
Device on PCB
6)
, Ta
=
85C, Tj
150C
I
L(NOM)
2.3
3.3
4.7
2.6
3.7
5.3
--
--
--
A
Output current
while GND disconnected or pulled
up
8
)
;
Vbb = 32 V, VIN = 0,
see diagram page 9
I
L(GNDhigh)
-- -- 2
mA
Turn-on time
9
)
IN
to 90% V
OUT
:
Turn-off time
IN
to 10% V
OUT
:
R
L
=
12
t
on
t
off
--
--
100
100
250
270
s
Slew rate on
9
)
10 to 30% V
OUT
,
R
L
=
12
: dV/dt
on
0.2 --
1.0
V/
s
Slew rate off
9
)
70 to 40% V
OUT
, R
L
=
12
: -dV/dt
off
0.2 --
1.1
V/
s
6
) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70
m thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
7
) Soldering point: upper side of solder edge of device pin 15. See page 14
8
) not subject to production test, specified by design
9
) See timing diagram on page 12.
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716G
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2003-Oct-01
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= -40...+150C, V
bb
= 12 V unless otherwise specified
min typ
max
Operating Parameters
Operating voltage
V
bb(on)
5.5
--
40
V
Undervoltage switch off
10
)
T
j
=-40...25C: V
bb(u so)
--
--
4.5
V
T
j
=125C:
--
-- 4.5
11)
Overvoltage protection
12
)
I
bb
=
40 mA
V
bb(AZ)
41
47
52
V
Standby current
13
)
T
j
=-40C...25C
:
V
IN
=
0;
see diagram page 11
T
j
=150C:
I
bb(off)
--
--
9
--
16
24
A
T
j
=125C:
--
--
16
11)
Off-State output current (included in I
bb(off)
)
V
IN
=
0; each channel
I
L(off)
-- 1 5
A
Operating current
14)
, V
IN
=
5V,
I
GND
= I
GND1
+ I
GND2
,
one channel on:
all channels on:
I
GND
--
--
0.5
1.9
0.9
3.3
mA
Protection Functions
15)
Current limit,
Vout = 0V
,
(see timing diagrams, page 12)
T
j
=-40C:
T
j
=25C:
T
j
=+150C:
I
L(lim)
--
--
5
--
9
--
14
--
--
A
Repetitive short circuit current limit,
T
j
= T
jt
each channel
two,three or four parallel channels
(see timing diagrams, page 12)
I
L(SCr)
--
--
6.5
6.5
--
--
A
Initial short circuit shutdown time
T
j,start
=25C:
Vout = 0V
(see timing diagrams on page 12)
t
off(SC)
--
2
--
ms
Output clamp (inductive load switch off)
16)
at VON(CL) = Vbb - VOUT
,
IL= 40 mA
V
ON(CL)
41 47 52
V
Thermal overload trip temperature
T
jt
150 -- --
C
Thermal hysteresis
T
jt
-- 10 --
K
10)
is the voltage, where the device doesnt change its switching condition for 15ms after the supply voltage
falling below the lower limit of Vbb(on)
11
) not subject to production test, specified by design
12
)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150
resistor for the GND connection is recommended). See also V
ON(CL)
in table of protection functions and
circuit diagram on page 9.
13
) Measured with load; for the whole device; all channels off
14
)
Add I
ST
, if I
ST
> 0
15
) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
16
)
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
V
ON(CL)
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716G
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2003-Oct-01
Parameter and Conditions,
each of the four channels
Symbol
Values
Unit
at T
j
= -40...+150C, V
bb
= 12 V unless otherwise specified
min typ
max
Reverse Battery
Reverse battery voltage
17
)
-V
bb
--
--
32
V
Drain-source diode voltage
(V
out
> V
bb
)
I
L
=
-
2.0
A, T
j
=
+150C
-V
ON
--
600
--
mV
Diagnostic Characteristics
Open load detection voltage
V
OUT(OL)
1
1.7 2.8 4.0
V
Input and Status Feedback
18
)
Input resistance
(see circuit page 9)
R
I
2.5
4.0 6.0
k
Input turn-on threshold voltage
V
IN(T+)
-- --
2.5
V
Input turn-off threshold voltage
V
IN(T-)
1.0 -- --
V
Input threshold hysteresis
V
IN(T)
-- 0.2 --
V
Status change after positive input slope
19)
with open load
t
d(STon)
-- 10 20
s
Status change after positive input slope
19)
with overload
t
d(STon)
30 -- --
s
Status change after negative input slope
with open load
t
d(SToff)
--
--
500
s
Status change after negative input slope
19)
with overtemperature
t
d(SToff)
--
--
20
s
Off state input current
V
IN
= 0.4 V: I
IN(off)
5
-- 20
A
On state input current
V
IN
= 5 V: I
IN(on)
10 35 60
A
Status output (open drain)
Zener limit voltage
I
ST
= +1.6 mA:
ST low voltage
I
ST
= +1.6 mA:
V
ST(high)
V
ST(low)
5.4
--
--
--
--
0.6
V
17
) Requires a 150
resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 4 and
circuit page 9).
18
) If ground resistors R
GND
are used, add the voltage drop across these resistors.
19
) not subject to production test, specified by design
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Truth Table
Channel 1 and 2
Chip 1
IN1
IN2
OUT1
OUT2
ST1/2
Channel 3 and 4
(equivalent to channel 1 and 2)
Chip 2
IN3
IN4
OUT3
OUT4
ST3/4
Normal operation
L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
H
H
H
H
H
Open load
Channel 1 (3)
L
H
X
X
Z
H
X
X
L
20
)
H
Channel 2 (4)
X
X
L
H
X
X
Z
H
L
15
)
H
Overtemperature
both channel
L
X
H
L
H
X
L
L
L
L
L
L
H
L
L
Channel 1 (3)
L
H
X
X
L
L
X
X
H
L
Channel 2 (4)
X
X
L
H
X
X
L
L
H
L
L = "Low" Level
X = don't care
Z = high impedance, potential depends on external circuit
H = "High" Level
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
PROFET
IN2
ST1/2
OUT2
GND1/2
Vbb
VOUT2
IGND1/2
VON2
18
2
Leadframe
3
4
IN1
V
OUT1
VON1
I L1
OUT1
5
17
V
IN1 VIN2 VST1/2
Ibb
IIN1
I IN2
I ST1/2
I L2
R
GND1/2
V
bb
Chip 1
PROFET
IN4
ST3/4
OUT4
GND3/4
Vbb
VOUT4
IGND3/4
VON4
14
6
Leadframe
7
8
IN3
V
OUT3
VON3
I L3
OUT3
9
13
V
IN3 VIN4 VST3/4
I IN3
IIN4
I ST3/4
I L4
R
GND3/4
Chip 2
Leadframe (V
bb
) is connected to pin 1,10,11,12,15,16,19,20
External R
GND
optional; two resistors R
GND1
, R
GND2
=
150
or a single resistor R
GND
=
75
for reverse
battery protection up to the max. operating voltage.
20
) L, if potential at the Output exceeds the OpenLoad detection voltage
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2003-Oct-01
Input circuit (ESD protection),
IN1 to IN4
IN
GND
I
R
ESD-ZD
I
I
I
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
Status output,
ST1/2 or ST3/4
ST
GND
ESD-
ZD
+5V
R
ST(ON)
ESD-Zener diode: 6.1
V typ., max 0.3 mA; R
ST(ON)
< 375
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
Inductive and overvoltage output clamp,
OUT1...4
+Vbb
OUT
VZ
V
ON
Power GND
V
ON
clamped to V
ON(CL)
= 47 V typ.
Overvolt. and reverse batt. protection
+ Vbb
IN
ST
ST
R
GND
GND
R
Signal GND
Logic
VZ2
I
R
VZ1
Load GND
Load
R
OUT
ST
R
+ 5V
V
Z1
= 6.1 V typ., V
Z2
= 47 V typ., R
GND
= 150
,
R
ST
= 15 k
, R
I
= 3.5 k
typ.
In case of reverse battery the load current has to be
limited by the load. Temperature protection is not
active
Open-load detection,
OUT1...4
OFF-state diagnostic condition:
Open Load, if V
OUT
> 3 V typ.; IN low
Open load
detection
Logic
unit
VOUT
Signal GND
OFF
REXT
Vbb
GND disconnect
PROFET
V
IN
ST
OUT
GND
bb
V
bb
V
IN
V
ST
V
GND
Any kind of load. In case of IN
=
high is V
OUT
V
IN
-
V
IN(T+)
.
Due to V
GND
>
0, no V
ST
= low signal available.
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GND disconnect with GND pull up
PROFET
V
IN
ST
OUT
GND
bb
V
bb
V
GND
V
IN
V
ST
Any kind of load. If V
GND
> V
IN
- V
IN(T+)
device stays off
Due to V
GND
>
0, no V
ST
= low signal available.
V
bb
disconnect with energized inductive
load
PROFET
V
IN
ST
OUT
GND
bb
V
bb
high
For inductive load currents up to the limits defined by Z
L
(max. ratings and diagram on page 10) each switch is
protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load all the load current
flows through the GND connection.
Inductive load switch-off energy
dissipation
PROFET
V
IN
ST
OUT
GND
bb
=
E
E
E
EAS
bb
L
R
ELoad
RL
L
{
L
Z
Energy stored in load inductance:
E
L
=
1/2
L
I
2
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
AS
= E
bb
+ E
L
- E
R
=
V
ON(CL)
i
L
(t) dt,
with an approximate solution for RL
>
0
:
E
AS
=
I
L
L
2
R
L
(
V
bb
+
|V
OUT(CL)
|)
ln
(1+
I
L
R
L
|V
OUT(CL)
|
)
Maximum allowable load inductance for
a single switch off
(one channel)
4)
L = f (IL );
Tj,start =
150C, Vbb =
12
V, RL =
0
ZL [mH]
1
10
100
1000
1
2
3
4
5
6
IL [A]
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716G
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Typ. on-state resistance
R
ON
= f (Vbb,Tj )
; I
L
=
2
A, IN
= high
R
ON
[mOhm]
240
180
120
60
0
5 7 9 11
30
40
Tj = 150C
25C
-40C
V
bb
[V]
Typ. standby current
I
bb(off)
= f (T
j
)
; V
bb
= 9...34 V, IN1,2,3,4
= low
I
bb(off)
[
A]
0
5
10
15
20
25
30
35
40
45
-50
0
50
100
150
200
T
j
[C]
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Figure 1a: V
bb
turn on:
IN2
V
OUT1
t
V
bb
ST1 open drain
IN1
V
OUT2
ST2 open drain
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition:
IN
t
V
OUT
I
L
t
t
on
off
90%
dV/dton
dV/dtoff
10%
Figure 2b: Switching a lamp:
IN
ST
OUT
L
t
V
I
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
other channel: normal operation
t
I
ST
IN1
L1
L(SCr)
I
I
L(lim)
t off(SC)
Heating up of the chip may require several milliseconds, depending
on external conditions
Timing diagrams
All channels are symmetric and consequently the diagrams are valid for channel 1 to
channel 4
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Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
t
ST1/2
IN1/2
L1 L2
L(SCr)
I
2xIL(lim)
I + I
toff(SC)
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor.
Figure 4a: Overtemperature:
Reset if T
j
<T
jt
IN
ST
OUT
J
t
V
T
Figure 5a: Open load: detection in OFF-state, turn
on/off to open load
Open load of channel 1; other channels normal
operation
OUT1
V
ST
IN1
I
L1
10s
500s
Figure 6a: Status change after, turn on/off to
overtemperature
Overtemperature of channel 1; other channels normal
operation
ST
IN1
30s
20s
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716G
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2003-Oct-01
Package and Ordering Code
Standard: P-DSO-20-15
Sales Code
BTS 716G
Ordering Code
Q67060-S7025
All dimensions in millimetres
Definition of soldering point with temperature T
s
:
upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70
m, 6cm
2
active heatsink area) as a reference for
max. power dissipation P
tot
, nominal load current
I
L(NOM)
and thermal resistance R
thja
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Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 Mnchen
Infineon Technologies AG 2001
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