Edition 2000-12

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany

Infineon Technologies AG 2000.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

Data Sheet

12.00

C505/C505C/C505A/

C505CA

8-Bit Single-Chip Microcontroller
C500 Family

Advance Information

Fully compatible to standard 8051 microcontroller

Superset of the 8051 architecture with 8 datapointers

Up to 20 MHz operating frequency
375 ns instruction cycle time @16 MHz
300 ns instruction cycle time @20 MHz (50 % duty cycle)

On-chip program memory (with optional memory protection)
C505(C)(A)-2R :

16K byte on-chip ROM

C505A-4R/C505CA-4R: 32K byte on-chip ROM
C505A-4E/C505CA-4E: 32K byte on-chip OTP
alternatively up to 64k byte external program memory

256 byte on-chip RAM

On-chip XRAM
C505/C505C :

256 byte

C505A/C505CA : 1K byte

(more features on next page)

Figure 1
C505 Functional Units

Oscillator
Watchdog

Timer

C500

8-bit

USART

I/O

8 digit. I/O

I/O

RAM

XRAM

On-Chip Emu

l
ation

pport Mod

Timer 2

Watchdog Timer

8 analog inputs /

Full-CAN Controller

8 Datapointers

I/O (2-bit I/O port)

Port 0

Port 1

Port 2

Port 4

Port 3

C505/C505C : 8-bit

A/D Converter

C505A/C505CA : 10-bit

C505C/C505CA only

C505(C)(A)-2R : 16K ROM

C505A-4R/C505CA-4R : 32K ROM

C505A-4E/C505CA-4E : 32K OTP

C505/C505C: 256 byte

C505A/C505CA: 1K byte 256 byte

Program Memory

Timer

Core

C505/C505C/C505A/C505CA

Data Sheet

12.00

Features (continued) :

32 + 2 digital I/O lines
Four 8-bit digital I/O ports
One 2-bit digital I/O port (port 4)
Port 1 with mixed analog/digital I/O capability

Three 16-bit timers/counters
Timer 0 / 1 (C501 compatible)
Timer 2 with 4 channels for 16-bit capture/compare operation

Full duplex serial interface with programmable baudrate generator (USART)

Full CAN Module, version 2.0 B compliant (C505C and C505CA only)
256 register/data bytes located in external data memory area
1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz
internal CAN clock prescaler when input frequency is over 10 MHz

On-chip A/D Converter
up to 8 analog inputs
C505/C505C

: 8-bit resolution

C505A/C505CA: 10-bit resolution

Twelve interrupt sources with four priority levels

On-chip emulation support logic (Enhanced Hooks Technology

)

Programmable 15-bit watchdog timer

Oscillator watchdog

Fast power on reset

Power Saving Modes
Slow-down mode
Idle mode (can be combined with slow-down mode)
Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin

P-MQFP-44 package

Pin configuration is compatible to C501, C504, C511/C513-family

Temperature ranges:

SAB-C505 versions

= 0 to 70

SAF-C505 versions

= -40 to 85

SAH-C505 versions

= -40 to 110

SAK-C505 versions

= -40 to 125

C505/C505C/C505A/C505CA

Data Sheet

12.00

Note: The term C505 refers to all versions described within this document unless otherwise noted.

However the term C505 may also be restricted by the context to refer to only CAN-less
derivatives with 8-Bit ADC which are C505-2R and C505-L in this document.

Note: The term C505(C)(A)-2R, for simplicity, is used to stand for C505 16K byte ROM versions

within this document which are C505-2R, C505C-2R, C505A-2R and C505CA-2R.

Ordering Information

The ordering code for Infineon Technologies' microcontrollers provides an exact reference to the
required product. This ordering code identifies:

the derivative itself, i.e. its function set

the specificed temperature rage

the package and the type of delivery

For the available ordering codes for the C505 please refer to the "Product information
Microcontrollers", which summarizes all available microcontroller variants.

Table 1
Differences in Functionality of the C505 MCUs

Device

Internal Program Memory XRAM Size

A/D Converter
Resolution

CAN
Controller

ROM

OTP

C505-2R

16K byte

256 byte

8 Bit

C505-L

256 byte

8 Bit

C505C-2R

16K byte

256 byte

8 Bit

C505C-L

256 byte

8 Bit

C505A-4R

32K byte

1K byte

10 Bit

C505A-2R

16K byte

1K byte

10 Bit

C505A-L

1K byte

10 Bit

C505CA-4R

32K byte

1K byte

10 Bit

C505CA-2R

16K byte

1K byte

10 Bit

C505CA-L

1K byte

10 Bit

C505A-4E

32K byte

1K byte

10 Bit

C505CA-4E

32K byte

1K byte

10 Bit

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 3
C505 Pin Configuration P-MQFP-44 Package (Top View)

This pin functionality is not available in the C505/C505A.

ALE

PSE

P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
V

XTAL1
XTAL2
P3.7 / RD
P3.6 / WR

32 31 30 29 28 27 26 25 24 23

6 7

9 10

/ T2

ESE

RxD

TxD

P0.3 / AD3
P0.2 / AD2
P0.1 / AD1

AREF

AGND

P1.1 / AN1 / INT4 / CC1
P1.2 / AN2 / INT5 / CC2
P1.3 / AN3 / INT6 / CC3

P1.4 / AN4

P0.0 / AD0

P1.0 / AN0 / INT3 / CC0

C505

C505C
C505A

C505CA

C505/C505C/C505A/C505CA

Data Sheet

12.00

Table 2
Pin Definitions and Functions

Symbol

Pin Number

I/O
*)

Function

P1.0-P1.7

40-44,1-3

44
1

I/O

Port 1
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 1 pins can be used for digital input/output
or as analog inputs of the A/D converter. Port 1 pins that
have 1's written to them are pulled high by internal pull-up
transistors and in that state can be used as inputs. As
inputs, port 1 pins being externally pulled low will source
current (

, in the DC characteristics) because of the

internal pullup transistors. Port 1 pins are assigned to be
used as analog inputs via the register P1ANA.
As secondary digital functions, port 1 contains the interrupt,
timer, clock, capture and compare pins. The output latch
c o r r e s p o n d i n g t o a s e c o n d a r y f u n c t i o n m u s t b e
programmed to a one (1) for that function to operate (except
for compare functions). The secondary functions are
assigned to the pins of port 1 as follows:

P1.0 / AN0 / INT3 / CC0

Analog input channel 0
interrupt 3 input /
capture/compare channel 0 I/O

P1.1 / AN1 / INT4 / CC1 Analog input channel 1/

interrupt 4 input /
capture/compare channel 1 I/O

P1.2 / AN2 / INT5 / CC2

Analog input channel 2 /
interrupt 5 input /
capture/compare channel 2 I/O

P1.3 / AN3 / INT6 / CC3 Analog input channel 3

interrupt 6 input /
capture/compare channel 3 I/O

P1.4 / AN4

Analog input channel 4

P1.5 / AN5 / T2EX

Analog input channel 5 / Timer 2
external reload / trigger input

P1.6 / AN6 / CLKOUT

Analog input channel 6 /
system clock output

P1.7 / AN7 / T2

Analog input channel 7 /
counter 2 input

Port 1 is used for the low-order address byte during program
verification of the C505 ROM versions (i.e. C505(C)(A)-2R/
C505A-4R/C505CA-4R).

*) I = Input

O = Output

C505/C505C/C505A/C505CA

Data Sheet

12.00

RESET

RESET
A high level on this pin for two machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to

permits power-on reset using only an

external capacitor to

P3.0-P3.7

5, 7-13

10
11
12

I/O

Port 3
is an 8-bit quasi-bidirectional port with internal pull-up
arrangement. Port 3 pins that have 1's written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup transistors.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to operate
(except for TxD and WR). The secondary functions are
assigned to the pins of port 3 as follows:
P3.0 / RxD

Receiver data input (asynch.) or data
input/output (synch.) of serial interface

P3.1 / TxD

Transmitter data output (asynch.) or
clock output (synch.) of serial interface

P3.2 / INT0

External interrupt 0 input / timer 0 gate
control input

P3.3 / INT1

External interrupt 1 input / timer 1 gate
control input

P3.4 / T0

Timer 0 counter input

P3.5 / T1

Timer 1 counter input

P3.6 / WR

WR control output; latches the data
byte from port 0 into the external data
memory

P3.7 / RD

RD control output; enables the external
data memory

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O
*)

Function

C505/C505C/C505A/C505CA

Data Sheet

12.00

P4.0
P4.1

6
28

I/O
I/O

Port 4
is a 2-bit quasi-bidirectional port with internal pull-up
arrangement. Port 4 pins that have 1's written to them are
pulled high by the internal pull-up transistors and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (

, in the DC

characteristics) because of the internal pullup transistors.
The output latch corresponding to the secondary function
RXDC must be programmed to a one (1) for that function to
operate. The secondary functions are assigned to the two
pins of port 4 as follows (C505C and C505CA only) :
P4.0 / TXDC

Transmitter output of CAN controller

P4.1 / RXDC

Receiver input of CAN controller

XTAL2

XTAL2
Output of the inverting oscillator amplifier.

XTAL1

XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. To
operate above a frequency of 16 MHz, a duty cycle of the
etxernal clock signal of 50 % should be maintained.
Minimum and maximum high and low times as well as rise/
fall times specified in the AC characteristics must be
observed.

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O
*)

Function

C505/C505C/C505A/C505CA

Data Sheet

12.00

P2.0-P2.7

18-25

I/O

Port 2
is a an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are pulled
high by the internal pullup resistors, and in that state can be
used as inputs. As inputs, port 2 pins being externally pulled
low will source current (

, in the DC characteristics)

because of the internal pullup resistors. Port 2 emits the
high-order address byte during fetches from external
program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup transistors when
issuing 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register and uses only
the internal pullup resistors.

PSEN

The Program Store Enable
output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every three oscillator periods except during
external data memory accesses. Remains high during
internal program execution. This pin should not be driven
during reset operation.

ALE

The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every three oscillator periods except during an external data
memory access. When instructions are executed from
internal ROM or OTP (EA=1) the ALE generation can be
disabled by bit EALE in SFR SYSCON.
ALE should not be driven during reset operation.

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O
*)

Function

C505/C505C/C505A/C505CA

Data Sheet

12.00

External Access Enable
When held at high level, instructions are fetched from the
internal program memory when the PC is less than 4000H
(C505(C)(A)-2R) or 8000

(C505A-4R/C505CA-4R/C505A-

4E/C505CA-4E). When held at low level, the C505 fetches
all instructions from external program memory.
For the C505 romless versions (i.e. C505-L, C505C-L,
C505A-L and C505CA-L) this pin must be tied low.
For the ROM protection version EA pin is latched during
reset.

P0.0-P0.7

37-30

I/O

Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1's written to them float, and in that state can be used
as high-impendance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external
program or data memory. In this application it uses strong
internal pullup transistors when issuing 1's.
Port 0 also outputs the code bytes during program
verification in the C505 ROM versions. External pullup
resistors are required during program verification.

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

Ground (0V)

Power Supply (+5V)

*) I = Input

O = Output

Table 2
Pin Definitions and Functions (cont'd)

Symbol

Pin Number

I/O
*)

Function

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 4
Block Diagram of the C505/C505C/C505A/C505CA

Port 0
8-bit digit. I/O

Port 2
8-bit digit. I/O

Port 3

8-bit digit. I/O

Port 0

Port 1

Port 2

Port 3

OSC & Timing

CPU

Timer 0

Timer 1

Timer 2

USART

XTAL1

XTAL2

RESET

ALE

PSEN

Vss

Oscillator Watchdog

A/D Converter

8-/10-Bit

S&H

MUX

AGND

AREF

Port 1

8-bit digit. I/O /

8-bit analog In

16K or 32K

ROM/

256 Byte

XRAM

256 Byte

RAM

Emulation

Support

Logic

Programmable
Watchdog Timer

Full-CAN

Controller

6 By

t
e

eg.

/
D

Interrupt Unit

8 datapointers

Port 4

2-bit digit. I/O

Port 4

C505C/C505CA only.

or 1K Byte

OTP

Byte

1) Please refer to

Table 1

for device specific configuration.

Baudrate generator

C505/C505C/C505A/C505CA

Data Sheet

12.00

CPU

The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-
byte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz:
300 ns).

Special Function Register PSW (Address D0H)

Reset Value : 00H

Bit

Function

Carry Flag
Used by arithmetic instruction.

Auxiliary Carry Flag
Used by instructions which execute BCD operations.

General Purpose Flag

RS1
RS0

Register Bank Select Control Bits
These bits are used to select one of the four register banks.

Overflow Flag
Used by arithmetic instruction.

General Purpose Flag

Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.

RS1

RS0

D0H

PSW

D7H

D6H

D5H

D4H

D3H

D2H

D1H

D0H

Bit No.

MSB

LSB

RS1

RS0

Function

Bank 0 selected, data address 00H-07H

Bank 1 selected, data address 08H-0FH

Bank 2 selected, data address 10H-17H

Bank 3 selected, data address 18H-1FH

C505/C505C/C505A/C505CA

Data Sheet

12.00

Memory Organization

The C505 CPU manipulates operands in the following four address spaces:

On-chip program memory :16K byte ROM (C505(C)(A)-2R) or

32K byte ROM (C505A-4R/C505CA-4R) or
32K byte OTP (C505A-4E/C505CA-4E)

Totally up to 64K byte internal/external program memory
up to 64 Kbyte of external data memory
256 bytes of internal data memory
Internal XRAM data memory :256 byte (C505/C505C)

1K byte (C505A/C505CA)

a 128 byte special function register area

Figure 5

illustrates the memory address spaces of the C505 versions.

Figure 5
C505 Memory Map Memory Map

Ext.

Int.

(EA = 1)

Ext.

Data

Memory

Int. CAN

Contr.

(256 Byte)

(EA = 0)

Ext.

FFFF

8000

3FFF /

0000

Data

Memory

Ext.

F700

F6FF

0000

Regs.

Function

Special

RAM

Internal

RAM

Internal

Addr.

Indirect

Addr.

Direct

Alternatively

"Code Space"

"Data Space"

"Internal Data Space"

MCB03632

XRAM

Internal

FFFF

See table below
for detailed
Data Memory
partitioning

4000 /

7FFF

Device

CAN Area

C505

C505C

C505A

C505CA

F700 F7FF

Unused Area

F800 FEFF

F700 FEFF

FF00 FFFF

XRAM Area

"Data Space" F700 to FFFF :

F700 F7FF

F800 FBFF

F700 FBFF

FF00 FFFF

FC00 FFFF

Unused

Area

C505/C505C/C505A/C505CA

Data Sheet

12.00

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to

to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when

is applied by connecting

the RESET pin to

via a capacitor.

Figure 6

shows the possible reset circuitries.

Figure 6
Reset Circuitries

RESET

C505

C505C
C505A

C505CA

RESET

C505

C505C
C505A

C505CA

RESET

C505

C505C
C505A

C505CA

C505/C505C/C505A/C505CA

Data Sheet

12.00

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit
datapointers instead of only one datapointer. The instruction set uses just one of these datapointers
at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL.

Figure 8

illustrates the datapointer addressing mechanism.

Figure 8
External Data Memory Addressing using Multiple Datapointers

DPH(83 )

DPL(82 )

DPTR0

DPTR7

DPSEL(92 )

DPSEL

Selected

Data-

pointer

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

MCD00779

External Data Memory

C505/C505C/C505A/C505CA

Data Sheet

12.00

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

The Enhanced Hooks Technology

, which requires embedded logic in the C500 allows the C500

together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

Figure 9
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

"Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon
Technologies.

MCS02647

SYSCON

PCON
TCON

RESET

PSEN

ALE

Port 0

Port 2

I/O Ports

Optional

Port 3

Port 1

C500

MCU

Interface Circuit

Enhanced Hooks

RPort 0

RPort 2

RTCON

RPCON

RSYSCON

TEA

TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

C505/C505C/C505A/C505CA

Data Sheet

12.00

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions : the
standard special function register area and the mapped special function register area. Five special
function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special
function register area. For accessing the mapped special function register area, bit RMAP in special
function register SYSCON must be set. All other special function registers are located in the
standard special function register area which is accessed when RMAP is cleared ("0").

The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data
memory area at addresses F700H to F7FFH..

Special Function Register SYSCON (Address B1H)

Reset Value : XX100X01B

(C505CA only)

Reset Value : XX100001B

As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set respectively by software.

All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are
bitaddressable.

The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C505 are listed in

Table 3

and

Table 4

. In

Table 3

they are organized in groups which

refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA
only) are also included in

Table 3

Table 4

illustrates the contents of the SFRs in numeric order of

their addresses.

Table 5

list the CAN-SFRs in numeric order of their addresses.

Bit

Function

RMAP

Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function register

area is enabled.

RMAP = 1 : The access to the mapped special function register area is enabled.

CSWO

CAN Controller switch-off bit
CSWO = 0 : CAN Controller is enabled (default after reset).
CSWO = 1 : CAN Controller is switched off.

EALE

RMAP CMOD

B1H

SYSCON

Bit No.

MSB

LSB

CSWO XMAP1

XMAP0

The functions of the shaded bits are not described here.

1) This bit is only available in the C505CA.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Table 3
Special Function Registers - Functional Blocks

Block

Symbol

Name

Address

Contents after
Reset

CPU

ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON

VR0

VR1

VR2

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
System Control Register

Version Register 0
Version Register 1
Version Register 2

E0H

F0H

83H
82H
92H
D0H

81H
B1H

FCH
FDH
FEH

00H
00H
00H
00H
XXXXX000B

00H
07H
XX100X01B

3) 6)

XX100001B

3) 7)

C5H
05H

A/D-
Converter

ADCON0

ADCON1
ADDAT
ADST
ADDATH

ADDATL

P1ANA

2) 4)

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Reg. (C505/C505C)
A/D Converter Start Reg. (C505/C505C)
A/D Converter High Byte Data Register
(C505A/C505CA)
A/D Converter Low Byte Data Register
(C505A/C505CA)
Port 1 Analog Input Selection Register

D8H

DCH
D9H
DAH
D9H

DAH

90H

00X00000B

01XXX000B

00H
XXH

00H

00XXXXXXB

FFH

Interrupt
System

IEN0

IEN1

IP0

IP1
TCON

T2CON

SCON

IRCON

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Timer Control Register
Timer 2 Control Register
Serial Channel Control Register
Interrupt Request Control Register

A8H

B8H

A9H
B9H
88H

C8H

98H

C0H

00H
00H
00H
XX000000B

00H
00X00000B
00H
00H

XRAM

XPAGE

SYSCON

Page Address Register for Extended on-chip
XRAM and CAN Controller
System Control Register

91H

B1H

00H

XX100X01B

3) 6)

XX100001B

3) 7)

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The content of this SFR varies with the actual step of the C505 (eg. 01

for the first step)

6) C505 / C505A/C505C only
7) C505CA only

C505/C505C/C505A/C505CA

Data Sheet

12.00

Ports

P0
P1
P1ANA

2) 4)

P2
P3
P4

Port 0
Port 1
Port 1 Analog Input Selection Register
Port 2
Port 3
Port 4

80H

90H

A0H

B0H

E8H

FFH
FFH
FFH
FFH
FFH
XXXXXX11B

Serial
Channel

ADCON0

PCON

SBUF
SCON
SRELL
SRELH

A/D Converter Control Register 0
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte

D8H

87H
99H
98H

AAH
BAH

00X00000B

00H
XXH

00H
D9H
XXXXXX11B

Timer 0/
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

88H

8CH
8DH
8AH
8BH
89H

00H
00H
00H
00H
00H
00H

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON
IEN0

IEN1

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Reload Register High Byte
Reload Register Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
Interrupt Enable Register 0
Interrupt Enable Register 1

C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8H

A8H

B8H

00H

00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00X00000B

00H
00H

Watchdog WDTREL

IEN0

IEN1

IP0

Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0

86H
A8H

B8H

A9H

00H
00H
00H
00H

Pow. Save
Modes

PCON

PCON1

Power Control Register
Power Control Register 1

87H
88H

00H
0XX0XXXXB

1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) "X" means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

C505/C505C/C505A/C505CA

Data Sheet

12.00

CAN
Controller

(C505C/
C505CA
only)

CR
SR
IR
BTR0
BTR1
GMS0
GMS1
UGML0
UGML1
LGML0
LGML1
UMLM0
UMLM1
LMLM0
LMLM1

MCR0
MCR1
UAR0
UAR1
LAR0
LAR1
MCFG
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High
Message Object Registers :
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7

F700H
F701H
F702H
F704H
F705H
F706H
F707H
F708H
F709H
F70AH
F70BH
F70CH
F70DH
F70EH
F70FH

F7n0H

F7n1H

F7n2H

F7n3H

F7n4H

F7n5H

F7n6H

F7n7H

F7n8H

F7n9H

F7nAH

F7nBH

F7nCH

F7nDH

F7nEH

01H
XXH

XXH

UUH

0UUUUUUU

UUH

UUU11111

UUH

UUUUU000

UUH

UUUUU000

UUH

UUUUU000

UUUUUU00

XXH

a reset operation. "U" values are undefined (as "X") after a power-on reset operation

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation "n" (n= 1 to F) in the message object address definition defines the number of the related
message object.

Table 3
Special Function Registers - Functional Blocks (cont'd)

Block

Symbol

Name

Address

Contents after
Reset

C505/C505C/C505A/C505CA

Data Sheet

12.00

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses

Addr

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

80H

FFH

81H

07H

82H

DPL

00H

83H

DPH

00H

86H

WDTREL 00H

WDT
PSEL

87H

PCON

00H

SMOD PDS

IDLS

GF1

GF0

PDE

IDLE

88H

TCON

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

88H

PCON1

0XX0-
XXXXB

EWPD

89H

TMOD

00H

GATE

C/T

GATE

C/T

8AH

TL0

00H

8BH

TL1

00H

8CH

TH0

00H

8DH

TH1

00H

90H

FFH

CLK-
OUT

T2EX

INT6

INT5

INT4

.INT3

90H

P1ANA

FFH

EAN7

EAN6

EAN5

EAN4

EAN3

EAN2

EAN1

EAN0

91H

XPAGE

00H

92H

DPSEL

XXXX-
X000B

98H

SCON

00H

SM0

SM1

SM2

REN

TB8

RB8

99H

SBUF

XXH

A0H

FFH

A8H

IEN0

00H

WDT

ET2

ET1

EX1

ET0

EX0

A9H

IP0

00H

OWDS WDTS

AAH

SRELL

D9H

C505/C505C/C505A/C505CA

Data Sheet

12.00

B0H

FFH

INT1

INT0

TxD

RxD

B1H

SYSCON

XX10-
0X01B

EALE

RMAP

CMOD

XMAP1 XMAP0

B1H

SYSCON

XX10-
0001B

EALE

RMAP

CMOD CSWO XMAP1 XMAP0

B8H

IEN1

00H

EXEN2 SWDT

EX6

EX5

EX4

EX3

ECAN

EADC

B9H

IP1

XX00-
0000B

BAH

SRELH

XXXX-
XX11B

C0H

IRCON

00H

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

SWI

IADC

C1H

CCEN

00H

COCA
H3

COCAL
3

COCA
H2

COCAL
2

COCA
H1

COCAL
1

COCA
H0

COCAL
0

C2H

CCL1

00H

C3H

CCH1

00H

C4H

CCL2

00H

C5H

CCH2

00H

C6H

CCL3

00H

C7H

CCH3

00H

C8H

T2CON

00X0-
0000B

T2PS

I3FR

T2R1

T2R0

T2CM

T2I1

T2I0

CAH

CRCL

00H

CBH

CRCH

00H

CCH

TL2

00H

CDH

TH2

00H

D0H

PSW

00H

RS1

RS0

D8H

ADCON0 00X0-

0000B

CLK

BSY

ADM

MX2

MX1

MX0

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) C505 /C505C/C505A only
4) C505CA only

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C505/C505C/C505A/C505CA

Data Sheet

12.00

D9H ADDAT

00H

D9H

ADDATH

00H

DAH ADST

XXXX-
XXXXB

DAH ADDATL

00XX-
XXXXB

DCH

ADCON1 01XX-

X000B

ADCL1 ADCL0

MX2

MX1

MX0

E0H

ACC

00H

E8H

XXXX-
XX11B

RXDC

TXDC

F0H

00H

FCH

3)4)

VR0

C5H

FDH

3)4)

VR1

05H

FEH

3)4)

VR2

01H

12H

33H

10)

1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) These are read-only registers
5) The content of this SFR varies with the actual of the step C505 (eg. 01

or 11

or 21

for the first step)

6) C505 / C505C only
7) C505A / C505CA only
8) C505 / C505C AB step only
9) C505A-4E / C505CA-4E BA step only (11

for the AA step)

10) C505A-4R / C505CA-4R BB step only (32

for the BA step)

Table 4

Contents of the SFRs, SFRs in numeric order of their addresses (cont'd)

Addr

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C505/C505C/C505A/C505CA

Data Sheet

12.00

Table 5
Contents of the CAN Registers in numeric order of their addresses
(C505C/C505CA only)

Addr.
n=1-FH

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

F700H CR

01H

TEST

CCE

EIE

SIE

INIT

F701H SR

XXH

BOFF

EWRN

RXOK TXOK

LEC2

LEC1

LEC0

F702H IR

XXH

INTID

F704H BTR0

UUH

SJW

BRP

F705H BTR1

0UUU.
UUUUB

TSEG2

TSEG1

F706H GMS0

UUH

ID28-21

F707H GMS1

UUU1.
1111B

ID20-18

F708H UGML0

UUH

ID28-21

F709H UGML1

UUH

ID20-13

F70AH LGML0

UUH

ID12-5

F70BH LGML1

UUUU.
U000B

ID4-0

F70CH UMLM0

UUH

ID28-21

F70DH UMLM1

UUH

ID20-18

ID17-13

F70EH LMLM0

UUH

ID12-5

F70FH LMLM1

UUUU.
U000B

ID4-0

F7n0H MCR0

UUH

MSGVAL

TXIE

RXIE

INTPND

F7n1H MCR1

UUH

RMTPND

TXRQ

MSGLST

CPUUPD

NEWDAT

F7n2H UAR0

UUH

ID28-21

F7n3H UAR1

UUH

ID20-18

ID17-13

F7n4H LAR0

UUH

ID12-5

F7n5H LAR1

UUUU.
U000B

ID4-0

1) The notation "n" (n= 1 to F) in the address definition defines the number of the related message object.
2) "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged

by a reset operation. "U" values are undefined (as "X") after a power-on reset operation

C505/C505C/C505A/C505CA

Data Sheet

12.00

F7n6H MCFG

UUUU.
UU00B

DLC

DIR

XTD

F7n7H DB0

XXH

F7n8H DB1

XXH

F7n9H DB2

XXH

F7nAH DB3

XXH

F7nBH DB4

XXH

F7nCH DB5

XXH

F7nDH DB6

XXH

F7nEH DB7

XXH

by a reset operation. "U" values are undefined (as "X") after a power-on reset operation

Table 5
Contents of the CAN Registers in numeric order of their addresses (cont'd)
(C505C/C505CA only)

Addr.
n=1-FH

Register Content

after
Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C505/C505C/C505A/C505CA

Data Sheet

12.00

I/O Ports

The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O
port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means,
when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally
pulled low. Port 0 will float when configured as input.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET .

Port 4 is 2-bit I/O port with CAN controller specific alternate functions. The eight analog input lines
are realized as mixed digital/analog inputs. The 8 analog inputs, AN0-AN7, are located at the port
1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are
configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR
P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog
input.

Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in

Table 6

In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the
count rate is

OSC

/6.

In the "counter" function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is

OSC

/12. External inputs INT0 and INT1 (P3.2, P3.3) can be

programmed to function as a gate to facilitate pulse width measurements.

Figure 10

illustrates the

input clock logic.

Figure 10
Timer/Counter 0 and 1 Input Clock Logic

Table 6
Timer/Counter 0 and 1 Operating Modes

Mode

Description

TMOD

Input Clock

internal

external (max)

8-bit timer/counter with a
divide-by-32 prescaler

OSC

/6x32

OSC

/12x32

16-bit timer/counter

OSC

/12

8-bit timer/counter with
8-bit autoreload

Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops

MCS03117

OSC

C/T = 0

C/T = 1

Control

TR1

P3.5/T1

(TMOD)

P3.2/INT0

Timer 0/1
Input Clock

OSC

P3.4/T0

TR0

Gate

P3.3/INT1

C505/C505C/C505A/C505CA

Data Sheet

12.00

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C505 provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

Compare

: up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock)

Capture

: up to 4 high speed capture inputs with 300 ns resolution

Reload

: modulation of timer 2 cycle time

The block diagram in

Figure 11

shows the general configuration of timer 2 with the additional

compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

Figure 11
Timer 2 Block Diagram

MCB02730

Comparator

CCL3/CCH3

Capture

Input/

Output

Control

P1.0/
INT3/
CC0

CC1

INT4/

P1.1/

CC2

INT5/

P1.2/

CC3

INT6/

P1.2/

CCL2/CCH2

Comparator

CCL1/CCH1

Comparator

CRCL/CRCH

Comparator

Bit

16 Bit

OSC

÷6

÷12

OSC

T2PS

Sync.

P1.7/
T2

T2EX

P1.5/

Sync.

T2I1

T2I0

Timer 2

TH2

TL2

TF2

Reload

EXEN2

Reload

EXF2

Interrupt
Request

Compare

C505/C505C/C505A/C505CA

Data Sheet

12.00

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.

Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1-
to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon-
ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect.

Figure 12

shows a functional diagram of a port circuit when used in compare

mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Figure 12
Port Latch in Compare Mode 0

MCS02661

Latch

Port

CLK

Port

Read Pin

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Overflow

Timer

16 Bit

Bit

C505/C505C/C505A/C505CA

Data Sheet

12.00

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see

Figure 13

) the port circuit consists of two separate latches. One latch

(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Figure 13
Compare Function in Compare Mode 1

Timer 2 Capture Modes

Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the
current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this
function.

In mode 0, the external event causing a capture is :

for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
for the CRC register:

a positive or negative transition at the corresponding pin, depending
on the status of the bit I3FR in SFR T2CON.

In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2
contents will be latched into the appropriate capture register in the cycle following the write
instruction. In this mode no interrupt request will be generated.

MCS02662

Latch

Port

CLK

Read Pin

CLK

Shadow

Latch

Read Latch

Port Circuit

Internal
Bus

Latch

Write to

Compare Reg.

Compare Register

Circuit

Comparator

Timer Register

Timer Circuit

Compare
Match

Port

16 Bit

C505/C505C/C505A/C505CA

Data Sheet

12.00

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in

Table 7

For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in

Figure 14

to the serial interface which - there divided

by 16 - results in the actual "baud rate". Further, the abbrevation f

OSC

refers to the oscillator

frequency (crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1
or from a decdicated baud rate generator (see

Figure 14

Table 7
USART Operating Modes

Mode

SCON

Description

SM0

SM1

Shift register mode, fixed baud rate
Serial data enters and exits through R

D; T

D outputs the shift

clock; 8-bit are transmitted/received (LSB first)

8-bit UART, variable baud rate
10 bits are transmitted (through T

D) or received (at R

9-bit UART, fixed baud rate
11 bits are transmitted (through T

D) or received (at R

9-bit UART, variable baud rate
Like mode 2

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 14
Block Diagram of Baud Rate Generation for the Serial Interface

Table 8

below lists the values/formulas for the baud rate calculation of the serial interface with its

dependencies of the control bits BD and SMOD.

Table 8
Serial Interface - Baud Rate Dependencies

Serial Interface
Operating Modes

Active Control Bits Baud Rate Calculation

SMOD

Mode 0 (Shift Register)

OSC

/ 6

Mode 1 (8-bit UART)
Mode 3 (9-bit UART)

Controlled by timer 1 overflow :
(2

SMOD

timer 1 overflow rate) / 32

Controlled by baud rate generator
(2

SMOD

OSC

) /

(32

baud rate generator overflow rate)

Mode 2 (9-bit UART)

0
1

OSC

/ 32

OSC

/ 16

MCS02733

Rate

OSC

(SMOD)

Baud

Clock

PCON.7

(SM0/

SM1)

SCON.7
SCON.6

Only one mode

can be selected

ADCON0.7

(BD)

0
1

Baud

Rate

Generator

(SRELH

SRELL)

Timer 1

Mode 2

Mode 0

Note: The switch configuration shows the reset state.

Mode 3

Mode 1

Overflow

C505/C505C/C505A/C505CA

Data Sheet

12.00

CAN Controller (C505C and C505CA only)

The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all
resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the
extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects (up to 15).
This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,
etc. In order to implement the physical layer, external components have to be connected to the
C505C/C505CA.

The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256
byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed
using MOVX instructions.

Figure 15

shows a block diagram of the on-chip CAN controller.

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error active, error passive and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline
transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline
transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.

C505/C505C/C505A/C505CA

Data Sheet

12.00

CAN Controller Software Initialization

The very first step of the initialization is the CAN controller input clock selection. A divide-by-2
prescaler is enabled by default after reset (

Figure 16

). Setting bit CMOD (SYSCON.3) disables the

prescaler. The purpose of the prescaler selection is:

to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0)
to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1)

Figure 16
CAN controller Input Clock Selection

Note : The switch configuration shows the reset state of bit CMOD.

SYSCON.3

(CMOD)

MCS03296

OSC

Full-CAN

Module

CAN

Condition: CMOD = 0, when > 10 MHz

OSC

Frequency (MHz)

CMOD

(SYSCON.3)

BRP

(BTR0.0-5)

CAN

baudrate

(Mbaud/sec)

OSC

CAN

000000B

0.5

000000B

C505/C505C/C505A/C505CA

Data Sheet

12.00

8-Bit A/D Converter (C505 and C505C only)

The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and provides the following
features:

8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs
8-bit resolution
Internal start-of-conversion trigger
Interrupt request generation after each conversion
Single or continuous conversion mode

The 8-bit ADC uses two clock signals for operation : the conversion clock f

ADC

(=1/t

ADC

) and the

input clock f

(1/t

). f

ADC

is derived from the C505 system clock f

OSC

which is applied at the XTAL

pins via the ADC clock prescaler as shown in

Figure 17

. The input clock is equal to f

OSC

. The

conversion clock f

ADC

is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock

prescaler must be programmed to a value which assures that the conversion clock does not exceed
1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.

Figure 17
8-Bit A/D Converter Clock Selection

MCS03299

OSC

MUX

Clock Prescaler

Conversion Clock

Input Clock

ADC

ADCL1

A / D

Converter

Condition:

ADC max

< 1.25 MHz

= f

OSC

CLP

ADCL0

MCU System Clock
Rate (f

OSC

)

[MHz]

Prescaler
Ratio

ADC

[MHz]

ADCL1

ADCL0

2 MHz

0.5

5 MHz

1.25

6 MHz

0.75

10 MHz

1.25

12 MHz

0.75

16 MHz

20 MHz

1.25

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 18
Block Diagram of the 8-Bit A/D Converter

ADC

Shaded Bit locations are not used in ADC-functions.

AGND

AREF

OSC

Port 1

Conversion

Prescaler

Clock

MUX

Conversion Clock

Input Clock f

S&H

ADCON1 (DC )

ADCON0 (D8 )

ADCL1

ADCL0

IRCON (C0 )

P1ANA (90 )

EAN7

EAN6

BSY

EAN5

EAN4

IEN1 (B8 )

Write to ADST

MCB03298

(DA )

ADST

conversion

Converter

A / D

Continuous Mode

Single /

Start of

MSB

LSB

(D9 )

ADDAT

Bus

Internal

ADM

MX2

EAN3

EAN2

MX1

MX0

EAN1

IADC

EAN0

EADC

Bus

Internal

CLK

SWI

IEX3

IEX4

IEX5

IEX6

TF2

EXF2

ECAN

EX3

EX4

EX5

EX6

SWDT

EXEN2

C505/C505C/C505A/C505CA

Data Sheet

12.00

10-Bit A/D Converter (C505A and C505CA only)

The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8
analog input channels. It operates with a successive approximation technique and uses self
calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D
converter provides the following features:

8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
10-bit resolution
Single or continuous conversion mode
Internal start-of-conversion trigger capability
Interrupt request generation after each conversion
Using successive approximation conversion technique via a capacitor array
Built-in hidden calibration of offset and linearity errors

The 10-bit ADC uses two clock signals for operation : the conversion clock f

ADC

(=1/t

ADC

) and the

input clock f

(=1/t

). f

ADC

is derived from the C505 system clock f

OSC

which is applied at the

XTAL pins. The input clock f

is equal to f

OSC

The conversion f

ADC

clock is limited to a maximum

frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.

Figure 19
10-Bit A/D Converter Clock Selection

MCS03635

OSC

MUX

Clock Prescaler

Conversion Clock

Input Clock

ADC

ADCL1

A / D

Converter

Condition:

ADC max

< 2 MHz

= f

OSC

CLP

ADCL0

MCU System Clock
Rate (f

OSC

)

[MHz]

Prescaler
Ratio

ADC

[MHz]

ADCL1

ADCL0

2 MHz

0.5

6 MHz

1.5

8 MHz

12 MHz

1.5

16 MHz

20 MHz

1.25

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 20
Block Diagram of the 10-Bit A/D Converter

ADC

Shaded Bit locations are not used in ADC-functions.

AGND

AREF

OSC

Port 1

Conversion

Prescaler

Clock

MUX

Conversion Clock

Input Clock f

S&H

ADCON1 (DC )

ADCON0 (D8 )

ADCL1

ADCL0

IRCON (C0 )

P1ANA (90 )

EAN7

EAN6

BSY

EAN5

EAN4

IEN1 (B8 )

Write to ADDATL

MCB03636

(DA )

ADST

conversion

Converter

A / D

Continuous Mode

Single /

Start of

MSB

LSB

(D9 )

ADDAT

Bus

Internal

ADM

MX2

EAN3

EAN2

MX1

MX0

EAN1

IADC

EAN0

EADC

Bus

Internal

IEX5

EX5

EXF2

EXEN2

CLK

TF2

SWDT

IEX6

EX6

IEX4

EX4

IEX3

EX3

SWI

ECAN

ADDATH

(D9

)

ADDATL

(DA

)

C505/C505C/C505A/C505CA

Data Sheet

12.00

Interrupt System

The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be
generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One
interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting
and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/
INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/
CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down
mode interrupt has a special functionality which allows to exit from the software power-down mode
by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC.

Figure 21

Figure 23

give a general overview of the interrupt sources and illustrate the request

and the control flags which are described in the next sections.

Table 9

lists all interrupt sources with

their request flags and interrupt vector addresses.

Table 9
Interrupt Source and Vectors

Interrupt Source

Interrupt Vector Address

Interrupt Request Flags

External Interrupt 0

0003H

IE0

Timer 0 Overflow

000BH

TF0

External Interrupt 1

0013H

IE1

Timer 1 Overflow

001BH

TF1

Serial Channel

0023H

RI / TI

Timer 2 Overflow / Ext. Reload

002BH

TF2 / EXF2

A/D Converter

0043H

IADC

CAN Controller / Software Interrupt 004BH

/ SWI

External interrupt 3

0053H

IEX3

External Interrupt 4

005BH

IEX4

External Interrupt 5

0063H

IEX5

External interrupt 6

006BH

IEX6

Wake-up from power-down mode

007BH

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 21
Interrupt Structure, Overview Part 1

Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the

shaded area of

Figure 21

provides the bits/flags.

ET0

IP1.1

IP0.1

IADC

EADC

EX0

IP1.0

IP0.0

IE0

IEN0.0

TCON.1

0003

0043

000B

004B

IEN1.0

IRCON.0

IEN1.1

IEN0.1

A / D Converter

IEN0.7

Highest
Priority Level

Lowest
Priority Level

l
l
i

n
g

e
q
u
e
n
c
e

MCB03303

IT0

TCON.5

TF0

TCON.0

P3.2 /

INT0

Overflow

Timer 0

Bit addressable

Request flag is cleared by hardware

IRCON.1

C505C and C505CA Only

ECAN

SWI

MCR0.5 / 4

MCR0.3 / 2

Receive

Message

Transmit

Message

Error

Status

MCR0.0 / 1

INTPND

CR.1

CR.3

RXIE

TXIE

EIE

CR.2

SIE

CAN Controller Interrupt Sources

ECAN

C505/C505C/C505A/C505CA

Data Sheet

12.00

Fail Save Mechanisms

The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure :

a programmable watchdog timer (WDT), with variable time-out period from 192

s up to

approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).

an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of

OSC

/12

upto

OSC

/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written.

Figure 24

shows the block diagram of the watchdog timer unit.

Figure 24
Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped
during active mode of the device. If the software fails to refresh the running watchdog timer an
internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the
content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh
sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The
reset cause (external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and
power down mode of the processor.

MCB03306

IP0 (A9 )

OSC

WDTS

WDTL

WDTH

/ 6

External HW Reset

Control Logic

IEN0 (A8 )

IEN1 (B8 )

WDT Reset - Request

WDTPSEL

WDTREL (86 )

WDT

SWDT

OWDS

C505/C505C/C505A/C505CA

Data Sheet

12.00

Oscillator Watchdog

The oscillator watchdog unit serves for three functions:

Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-
chip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the
oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog
reset is released and the part starts program execution from address 0000H again.

Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

Control of external wake-up from software power-down mode

When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin,
the oscillator watchdog unit assures that the microcontroller resumes operation (execution of
the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the
RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts program execution by processing a power down
interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Power Saving Modes

The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.

Idle mode

In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from
the clock signal. All peripheral units are further provided with the clock. The CPU status is
preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a
peripheral unit or by a hardware reset.

Power down mode

The operation of the C505 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.or P4.1/RXDC.

Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption.

In the power down mode of operation,

can be reduced to minimize power consumption. It must

be ensured, however, that

is not reduced before the power down mode is invoked, and that

is restored to its normal operating level, before the power down mode is terminated.

Table 10

gives

a general overview of the entry and exit procedures of the power saving modes.

Table 10
Power Saving Modes Overview

Mode

Entering
(Instruction
Example)

Leaving by

Remarks

Idle Mode

ORL PCON, #01H
ORL PCON, #20H

Ocurrence of an
interrupt from a
peripheral unit

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Hardware Reset

Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

Hardware Reset

Oscillator is stopped;
contents of on-chip RAM and
SFR's are maintained;

Short low pulse at
pin P3.2/INT0 or
P4.1/RXDC

Slow Down Mode

ORL PCON,#10H

ANL PCON,#0EFH
or
Hardware Reset

Oscillator frequency is
reduced to 1/32 of its nominal
frequency

C505/C505C/C505A/C505CA

Data Sheet

12.00

OTP Memory Operation (C505A-4E and C505CA-4E only)

The C505A-4E/C505CA-4E contains a 32K byte one-time programmable (OTP) program memory.
With the C505A-4E/C505CA-4E fast programming cycles are achieved (1 byte in 100

sec). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C505A-4E/C505CA-4E must be put into the programming
mode. This typically is done not in-system but in a special programming hardware. In the
programming mode the C505A-4E/C505CA-4E operates as a slave device similar as an EPROM
standalone memory device and must be controlled with address/data information, control lines, and
an external 11.5V programming voltage.

Figure 26

shows the pins of the C505A-4E/C505CA-4E

which are required for controlling of the OTP programming mode.

Figure 26
Programming Mode Configuration

Port 0

D0-D7

C505A-4E

C505CA-4E

PROG

A0-A7 /

Port 2

EA/V

PMSEL0

PSEL

RESET

PSEN

PMSEL1

PRD

A8-A14

PALE

XTAL1
XTAL2

C505/C505C/C505A/C505CA

Data Sheet

12.00

The following

Table 11

contains the functional description of all C505A-4E/C505CA-4E pins which

are required for OTP memory programming.

Table 11
Pin Definitions and Functions in Programming Mode

Symbol

Pin Number

I/O
*)

Function

RESET

Reset
This input must be at static "1" (active) level during the whole
programming mode.

PMSEL0
PMSEL1

5
7

I
I

Programming mode selection pins
These pins are used to select the different access modes in
programming mode. PMSEL1,0 must satisfy a setup time to the
rising edge of PALE. When the logic level of PMSEL1,0 is
changed, PALE must be at low level.

PSEL

Basic programming mode select
This input is used for the basic programming mode selection
and must be switched according

Figure 28

PRD

Programming mode read strobe
This input is used for read access control for OTP memory read,
Version Register read, and lock bit read operations.

PALE

Programming address latch enable
PALE is used to latch the high address lines. The high address
lines must satisfy a setup and hold time to/from the falling edge
of PALE. PALE must be at low level when the logic level of
PMSEL1,0 is changed.

XTAL2

XTAL2
Output of the inverting oscillator amplifier.

XTAL1

XTAL1
Input to the oscillator amplifier.

Circuit ground potential
must be applied in programming mode.

Power supply terminal
must be applied in programming mode.

*) I = Input

O = Output

PMSEL1

PMSEL0

Access Mode

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory byte

C505/C505C/C505A/C505CA

Data Sheet

12.00

P2.0-7

18-25

Address lines
P2.0-7 are used as multiplexed address input lines A0-A7 and
A8-A14. A8-A14 must be latched with PALE.

PSEN

Program store enable
This input must be at static "0" level during the whole
programming mode.

PROG

Programming mode write strobe
This input is used in programming mode as a write strobe for
OTP memory program, and lock bit write operations During
basic programming mode selection a low level must be applied
to PROG.

EA/V

External Access / Programming voltage
This pin must be at 11.5V (V

) voltage level during

programming of an OTP memory byte or lock bit. During an
OTP memory read operation this pin must be at V

high level.

This pin is also used for basic programming mode selection. At
basic programming mode selection a low level must be applied
to EA/V

D7-0

30-37

I/O

Data lines 0-7
During programming mode, data bytes are transferred via the
bidirectional port 0 data lines.

N.C.

1-3, 6, 11-13,
28, 38-44

Not Connected
These pins should not be connected in programming mode.

*) I = Input

O = Output

Table 11
Pin Definitions and Functions in Programming Mode (cont'd)

Symbol

Pin Number

I/O
*)

Function

C505/C505C/C505A/C505CA

Data Sheet

12.00

Lock Bits Programming / Read

The C505A-4E/C505CA-4E has two programmable lock bits which, when programmed according
to

Table 13

, provide four levels of protection for the on-chip OTP code memory. The state of the

lock bits can also be read.

Table 12
Access Modes Selection

Access Mode

EA/

PROG

PRD

PMSEL

Address

(Port 2)

Data

(Port 0)

Program OTP memory byte

A0-7

A8-14

D0-7

Read OTP memory byte

Program OTP lock bits

D1,D0 see

Table 13

Read OTP lock bits

Read OTP version byte

Byte addr.

of sign. byte

D0-7

Table 13
Lock Bit Protection Types

Lock Bits at D1,D0

Protection
Level

Protection Type

Level 0

The OTP lock feature is disabled. During normal operation of
the C505A-4E/C505CA-4E, the state of the EA pin is not
latched on reset.

Level 1

During normal operation of the C505A-4E/C505CA-4E, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the ROM/OTP verification mode 2 for
protection level 1. Further programming of the OTP memory is
disabled (reprogramming security).

Level 2

Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.

Level 3

Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C505A-4E/
C505CA-4E is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During absolute maximum rating overload conditions
(

) the voltage on

pins with respect to ground (

) must not

exceed the values defined by the absolute maximum ratings.

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Storage temperature

150

° C

Voltage on V

pins with respect

to ground (

)

0.5

6.5

Voltage on any pin with respect
to ground (

)

0.5

+ 0.5

Input current on any pin during
overload condition

Absolute sum of all input currents
during overload condition

| 100 mA |

Power dissipation

DISS

C505/C505C/C505A/C505CA

Data Sheet

12.00

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C505 and partly its
demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column "Symbol":

CC (Controller Characteristics):

The logic of the C505 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the C505.

Operating Conditions

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Supply voltage

4.25

5.5

Active mode,
f

osc max

= 20 MHz

5.5

PowerDown mode

Ground voltage

Reference voltage

Ambient temperature

SAB-C505 T

SAF-C505 T

-40

SAH-C505 T

-40

110

SAK-C505 T

-40

125

Analog reference
voltage

AREF

+ 0.1

Analog ground voltage

AGND

0.1

+ 0.2

Analog input voltage

AIN

AGND

-0.2

AREF

+0.2

XTAL clock

osc

20
(with 50% duty
cycle)

MHz

1) For the extended temperature range -40 °C to 110 °C (SAH) and -40 °C to 125 °C (SAK), the

devices C505-2R, C505-L, C505C-2R and C505C-L have the max. operating frequency of
16MHz with 50% clock duty cycle.

C505/C505C/C505A/C505CA

Data Sheet

12.00

DC Characteristics

(Operating Conditions apply)

Notes see

Page 60

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Input low voltages
all except EA, RESET
EA pin
RESET pin

IL1

IL2

0.5
0.5
0.5

0.2

- 0.1

0.2

- 0.3

0.2

+ 0.1

V
V
V

Input high voltages
all except XTAL1, RESET
XTAL1 pin
RESET pin

IH1

IH2

0.2

+ 0.9

0.7

0.6

+ 0.5

V
V
V

Output low voltages
Ports 1, 2, 3, 4
Port 0, ALE, PSEN

OL1

0.45
0.45

V
V

= 1.6 mA

= 3.2 mA

Output high voltages
Ports 1, 2, 3, 4

Port 0 in external bus mode,
ALE, PSEN

OH2

2.4
0.9

V
V
V
V

= 80

= 10

= 800

= 80

Logic 0 input current
Ports 1, 2, 3, 4

= 0.45 V

Logical 1-to-0 transition current
Ports 1, 2, 3, 4

650

= 2 V

Input leakage current
Port 0, AN0-7 (Port 1), EA

0.45 <

Input high current to RESET

100

14)

0.6 V

Pin capacitance

= 1 MHz,

= 25

Overload current

3) 4)

Programming voltage

10.9

12.1

11.5 V ± 5%

Supply current at EA/V

C505/C505C/C505A/C505CA

Data Sheet

12.00

Power Supply Currents

Notes see

Page 60

Parameter

Symbol

Limit Values

Unit Test Condition

typ.

12)

max.

13)

C505 /
C505C

Active Mode

12 MHz
20 MHz

19.3
31.3

27.0

Idle Mode

12 MHz
20 MHz

10.3
16.2

13.0
21.0

Active Mode with
slow-down enabled

12 MHz

20 MHz

3.9
4.8

5.5
7.5

Idle Mode with
slow-down enabled

12 MHz

20 MHz

3.2
4.0

5.0
7.0

10)

Power down mode

= 2..5.5 V

11)

C505A-4E
/C505CA-4E

Active Mode

16 MHz

20 MHz

28.7
35.2

30.7
37.6

Idle Mode

16 MHz
20 MHz

14.9
17.7

15.9
18.9

Active Mode with
slow-down enabled

16 MHz

20 MHz

9.9

12.3

12.8
15.6

Idle Mode with
slow-down enabled

16 MHz

20 MHz

5.1
6.3

5.6
6.8

10)

Power down mode

5.6

= 2..5.5 V

11)

C505A-4R /
C505CA-4R
/C505A-2R /
C505CA-2R
/C505A-L /
C505CA-L

Active Mode

16 MHz
20 MHz

22.8
27.6

29.2
35.3

Idle Mode

16 MHz
20 MHz

12.7
15.0

16.3
19.3

Active Mode with
slow-down enabled

16 MHz

20 MHz

6.6
7.3

8.2
9.3

Idle Mode with
slow-down enabled

16 MHz

20 MHz

5.0
5.3

5.9
6.5

10)

Power down mode

5.3

= 2..5.5 V

11)

C505/C505C/C505A/C505CA

Data Sheet

12.00

Note:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

2) Capacitive loading on ports 0 and 2 may cause the

on ALE and PSEN to momentarily fall below the

0.9

specification when the address lines are stabilizing.

3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e.

+ 0.5 V or

- 0.5 V). The absolute sum of input currents on all port

pins may not exceed 50 mA. The supply voltage

and

must remain within the specified limits.

4) Not 100% tested, guaranteed by design characterization.

5) Only valid for C505A-4E and C505CA-4E.

6) Only valid for C505A-4E and C505CA-4E in programming mode.

(active mode) is measured with:

XTAL1 driven with

= 5 ns, 50% duty cycle ,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

EA = Port 0 = RESET =

; all other pins are disconnected.

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with

= 5 ns, 50% duty cycle,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; Port0 =

; all other pins are disconnected; the microcontroller is put into idle mode by

software;

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;
XTAL1 driven with

= 5 ns, 50% duty cycle,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; all other pins are disconnected; the microcontroller is put into slow-down mode by

software;

10)

(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;
XTAL1 driven with

= 5 ns, 50% duty cycle,

+ 0.5 V,

0.5 V; XTAL2 = N.C.;

RESET = EA =

; Port0 =

; all other pins are disconnected; the microcontroller is put into idle mode

with slow-down enabled by software;

11)

(power-down mode) is measured under following conditions:

Port 0 = EA =

; RESET =

; XTAL2 = N.C.; XTAL1 =

;

AGND

;

AREF

;

all other pins are disconnected.

12) The typical

values are periodically measured at

= +25 °C but not 100% tested.

13) The maximum

values are measured under worst case conditions (

= 0 °C or -40 °C and

= 5.5 V)

14) The values are valid for C505CA-4R, C505CA-2R, C505CA-L, C505A-4R, C505A-2R and C505A-L only.

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 29
I

Diagram of C505 and C505C

C505/C505C : Power Supply Current Calculation Formulas

Note:

osc

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

DD typ

DD max

1.5

OSC

+ 1.3

1.5

OSC

+ 9.0

Idle mode

DD typ

DD max

0.74

OSC

+ 1.4

1.0

OSC

+ 1.0

Active mode with
slow-down enabled

DD typ

DD max

0.11

OSC

+ 2.6

0.25

OSC

+ 2.5

Idle mode with
slow-down enabled

DD typ

DD max

0.1

OSC

+ 2.0

0.25

OSC

+ 2.0

[mA]

max

typ

OSC

[MHz]

C505

C505C

Idle

Idl

e M

ode

tiv

Idle Mode+S

low-down

Active

Mode

+Slow

-down

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 30
I

Diagram of C505A-4E and C505CA-4E

C505A-4E/C505CA-4E : Power Supply Current Calculation Formulas

Note:

osc

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

DD typ

DD max

1.63

OSC

+ 2.6

1.74

OSC

+ 2.8

Idle mode

DD typ

DD max

0.69

OSC

+ 3.9

0.74

OSC

+ 4.1

Active mode with
slow-down enabled

DD typ

DD max

0.6

OSC

+ 0.3

0.7

OSC

+ 1.6

Idle mode with
slow-down enabled

DD typ

DD max

0.3

OSC

+ 0.3

0.3

OSC

+ 0.8

[mA]

max

typ

OSC

[MHz]

C505A-4E

C505CA-4E

Idle

tiv

Idle Mode+

Slow-dow

Act

ive

Mod

e+S

low

-dow

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 31
I

Diagram of C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L

C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L :
Power Supply Current Calculation Formulas

Note:

osc

is the oscillator frequency in MHz.

values are given in mA.

Parameter

Symbol

Formula

Active mode

DD typ

DD max

1.19

OSC

+ 3.77

1.54

OSC

+ 4.47

Idle mode

DD typ

DD max

0.57

OSC

+ 3.55

0.75

OSC

+ 4.26

Active mode with
slow-down enabled

DD typ

DD max

0.18

OSC

+ 3.74

0.28

OSC

+ 3.67

Idle mode with
slow-down enabled

DD typ

DD max

0.07

OSC

+ 3.91

0.14

OSC

+ 3.64

[mA]

max

typ

OSC

[MHz]

C505A-4R
C505A-2R

C505A-L

C505CA-4R
C505CA-2R

C505CA-L

tiv

Idle

Activ

e Mo

de+S

low-d

own

Idle Mode+Slow-down

C505/C505C/C505A/C505CA

Data Sheet

12.00

A/D Converter Characteristics of C505 and C505C

(Operating Conditions apply)

Notes see next page.

Clock calculation table :

Further timing conditions : t

ADC

min = 800 ns

= 1 / f

OSC

= t

CLP

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

0.2

AREF

0.2

Sample time

64 x

32 x

16 x

8 x

Prescaler

Conversion cycle time

ADCC

320 x

160 x

80 x

40 x

Prescaler

Total unadjusted error

LSB

+0.5V

AIN

-0.5V

Internal resistance of
reference voltage source

AREF

ADC

/ 500

- 1

ADC

in [ns]

5) 6)

Internal resistance of
analog source

ASRC

/ 500

- 1

in [ns]

2) 6)

ADC input capacitance

AIN

Clock Prescaler
Ratio

ADCL1, 0

ADC

ADCC

1 1

32 x t

320 x t

1 0

16 x t

160 x t

0 1

8 x t

80 x t

0 0

4 x t

8 x t

40 x t

C505/C505C/C505A/C505CA

Data Sheet

12.00

Note:

1) V

AIN

may exeed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be 00

or FF

, respectively.

2) During the sample time the input capacitance

AIN

must be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time t

, the time for determining the digital result. Values for the

conversion clock t

ADC

depend on programming and can be taken from the table on the previous page.

4) T

(max.) is tested at

125

C ;

5.5 V; V

AREF

+ 0.1 V and V

AGND

. It is

guaranteed by design characterization for all other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload
currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is
permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

C505/C505C/C505A/C505CA

Data Sheet

12.00

A/D Converter Characteristics of C505A and C505CA

(Operating Conditions apply)

Notes see next page.

Clock calculation table :

Further timing conditions : t

ADC

min = 500 ns

= 1 / f

OSC

= t

CLP

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage

AIN

AGND

AREF

Sample time

64 x

32 x

16 x

8 x

Prescaler

Conversion cycle time

ADCC

384 x

192 x

96 x

48 x

Prescaler

Total unadjusted error

LSB

+0.5V

AIN

-0.5V

LSB

AIN

+0.5V

- 0.5 V

AIN

Internal resistance of
reference voltage source

AREF

ADC

/ 250

- 0.25

ADC

in [ns]

5) 6)

Internal resistance of
analog source

ASRC

/ 500

- 0.25

in [ns]

2) 6)

ADC input capacitance

AIN

Clock Prescaler
Ratio

ADCL1, 0

ADC

ADCC

1 1

32 x t

384 x t

1 0

16 x t

192 x t

0 1

8 x t

96 x t

0 0

4 x t

8 x t

48 x t

C505/C505C/C505A/C505CA

Data Sheet

12.00

Note:

1) V

AIN

may exeed V

AGND

or V

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

2) During the sample time the input capacitance

AIN

must be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t

After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time t

, the time for determining the digital result and the time for the

calibration. Values for the conversion clock t

ADC

depend on programming and can be taken from the table on

the previous page.

4) T

is tested at V

AREF

= 5.0 V, V

AGND

= 0 V,

= 4.9 V. It is guaranteed by design characterization for all

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload
currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is
permissible.

5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal

6) Not 100% tested, but guaranteed by design characterization.

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)

(Operating Conditions apply)

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 16 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLP - 15

Address setup to ALE

AVLL

TCL

Hmin

-15

Address hold after ALE

LLAX

TCL

Hmin

-15

ALE to valid instruction in

LLIV

2 CLP - 50

ALE to PSEN

LLPL

TCL

Lmin

-15

PSEN pulse width

PLPH

CLP+
TCL

Hmin

-15

PSEN to valid instruction in

PLIV

CLP+
TCL

Hmin

- 50

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

TCL

Lmin

-10

Address valid after PSEN

PXAV

TCL

Lmin

- 5

Address to valid instruction in

AVIV

2 CLP +
TCL

Hmin

-55

Address float to PSEN

AZPL

-5

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont'd)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

16-MHz clock

Duty Cycle

0.4 to 0.6

Variable Clock

1/CLP= 2 MHz to 16 MHz

min.

max.

min.

max.

RD pulse width

RLRH

158

3 CLP - 30

WR pulse width

WLWH

158

3 CLP - 30

Address hold after ALE

LLAX2

CLP - 15

RD to valid data in

RLDV

100

2 CLP+
TCL

Hmin

- 50

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP - 12

ALE to valid data in

LLDV

200

4 CLP - 50

Address to valid data in

AVDV

200

4 CLP +
TCL

Hmin

-75

ALE to WR or RD

LLWL

103

CLP +
TCL

Lmin

- 15

CLP+
TCL

Lmin

+ 15

Address valid to WR

AVWL

2 CLP - 30

WR or RD high to ALE high

WHLH

TCL

Hmin

- 15

TCL

Hmin

+ 15

Data valid to WR transition

QVWX

TCL

Lmin

- 20

Data setup before WR

QVWH

163

3 CLP +
TCL

Lmin

- 50

Data hold after WR

WHQX

TCL

Hmin

- 20

Address float after RD

RLAZ

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont'd)

Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of

the oscillator clock from 0.4 to 0.6.

External Clock Drive Characteristics

Parameter

Symbol

CPU Clock = 16 MHz
Duty Cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 16 MHz

Unit

min.

max.

min.

max.

Oscillator period

CLP

62.5

500

High time

TCL

CLP - TCL

Low time

TCL

CLP - TCL

Rise time

Fall time

Oscillator duty cycle

0.4

0.6

25 / CLP

1 - 25 / CLP

Clock cycle

TCL

37.5

CLP * DC

min

CLP * DC

max

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics (20 MHz, 0.5 Duty Cycle)

(Operating Conditions apply)

(

for port 0, ALE and PSEN outputs = 100 pF;

for all other outputs = 80 pF)

Program Memory Characteristics

Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

Parameter

Symbol

Limit Values

Unit

20 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 20 MHz

min.

max.

min.

max.

ALE pulse width

LHLL

CLP - 15

Address setup to ALE

AVLL

CLP/2 - 15

Address hold after ALE

LLAX

CLP/2 - 15

ALE to valid instruction in

LLIV

2 CLP - 45

ALE to PSEN

LLPL

CLP/2 - 15

PSEN pulse width

PLPH

3/2 CLP
- 15

PSEN to valid instruction in

PLIV

3/2 CLP
- 50

Input instruction hold after PSEN

PXIX

Input instruction float after PSEN

PXIZ

CLP/2 - 5

Address valid after PSEN

PXAV

CLP/2 - 5

Address to valid instruction in

AVIV

5/2 CLP
- 60

Address float to PSEN

AZPL

- 5

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics (20 MHz, 0.5 Duty Cycle, cont'd)

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Unit

20 MHz clock

0.5 Duty Cycle

Variable Clock

1/CLP = 2 MHz to 20 MHz

min.

max.

min.

max.

RD pulse width

RLRH

120

3 CLP - 30

WR pulse width

WLWH

120

3 CLP - 30

Address hold after ALE

LLAX2

CLP - 15

RD to valid data in

RLDV

5/2 CLP- 50

Data hold after RD

RHDX

Data float after RD

RHDZ

CLP - 12

ALE to valid data in

LLDV

150

4 CLP - 50

Address to valid data in

AVDV

150

9/2 CLP - 75

ALE to WR or RD

LLWL

3/2 CLP - 15

3/2 CLP + 15 ns

Address valid to WR

AVWL

2 CLP - 30

WR or RD high to ALE high

WHLH

CLP/2 - 15

CLP/2 + 15

Data valid to WR transition

QVWX

CLP/2 - 20

Data setup before WR

QVWH

125

7/2 CLP - 50

Data hold after WR

WHQX

CLP/2 - 20

Address float after RD

RLAZ

External Clock Drive Characteristics

Parameter

Symbol

Limit Values

Unit

Variable Clock

Freq. = 2 MHz to 20 MHz

min.

max.

Oscillator period

CLP

500

High time

TCL

CLP-TCL

Low time

TCL

CLP-TCL

Rise time

Fall time

Oscillator duty cycle

0.5

C505/C505C/C505A/C505CA

Data Sheet

12.00

AC Characteristics of Programming Mode (C505A-4E and C505CA-4E only)

= 5 V

10 %;

= 11.5 V

5 %;

= 25 °C

10 °C

Parameter

Symbol

Limit Values

Unit

min.

max.

PALE pulse width

PAW

PMSEL setup to PALE rising edge

PMS

Address setup to PALE, PROG, or PRD
falling edge

PAS

Address hold after PALE, PROG, or PRD
falling edge

PAH

Address, data setup to PROG or PRD

PCS

100

Address, data hold after PROG or PRD

PCH

PMSEL setup to PROG or PRD

PMS

PMSEL hold after PROG or PRD

PMH

PROG pulse width

PWW

100

PRD pulse width

PRW

100

Address to valid data out

PAD

PRD to valid data out

PRD

Data hold after PRD

PDH

Data float after PRD

PDF

PROG high between two consecutive PROG
low pulses

PWH1

PRD high between two consecutive PRD low
pulses

PWH2

100

XTAL clock period

CLKP

83.3

500

C505/C505C/C505A/C505CA

Data Sheet

12.00

Figure 42
AC Testing: Input, Output Waveforms

Figure 43
AC Testing : Float Waveforms

Figure 44
Recommended Oscillator Circuits for Crystal Oscillator

0.45 V

0.2

-0.1

+0.9

0.2

Test Points

MCT00039

-0.5 V

AC Inputs during testing are driven at

- 0.5 V for a logic '1' and 0.45 V for a logic '0'.

Timing measurements are made at

IHmin

for a logic '1' and

ILmax

for a logic '0'.

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded

level occurs.

20 mA

MCS03311

2 - 20

MHz

XTAL2

XTAL1

XTAL2

N.C.

External Oscillator
Signal

Crystal Oscillator Mode

Driving from External Source

Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance)

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