Edition 2001-05

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany

Infineon Technologies AG 2001.

Attention please!

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Due to technical requirements components may contain dangerous substances. For information on the types in
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Controller Area Network (CAN): License of Robert Bosch GmbH

C164CI

Revision History:

2001-05

V2.0

Previous Version:

1999-08
1998-02

(Preliminary)

04.97

(Advance Information)

Page

Subjects (major changes since last revision)

These changes refer to the last two versions. Version 1998-02 covers OTP and ROM derivatives, while version
1999-08 ist the most recent one.

All

Converted to Infineon layout

Operating frequency up to 25 MHz

et al.

References to Flash removed

Timer Unit with three timers

On-chip XRAM described

Derivative table updated

Supply voltage is 5 V

Functionality of reduced CAPCOM6 corrected

Timer description improved

Sections "Oscillator Watchdog" and "Power Management" added

POCON reset values adjusted

Parameter section reworked

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Data Sheet

V2.0, 2001-05

C164CI

16-Bit Single-Chip Microcontroller
C166 Family

C164CI/SI, C164CL/SL

· High Performance 16-bit CPU with 4-Stage Pipeline

80 ns Instruction Cycle Time at 25 MHz CPU Clock
400 ns Multiplication (16

× 16 bit), 800 ns Division (32 / 16 bit)

Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area

· 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns
· 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

· Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),

via prescaler or via direct clock input

· On-Chip Memory Modules

2 KBytes On-Chip Internal RAM (IRAM)
2 KBytes On-Chip Extension RAM (XRAM)
up to 64 KBytes On-Chip Program Mask ROM or OTP Memory

· On-Chip Peripheral Modules

8-Channel 10-bit A/D Converter with Programmable Conversion Time

down to 7.8

µs

8-Channel General Purpose Capture/Compare Unit (CAPCOM2)
Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6)

(3/6 Capture/Compare Channels and 1 Compare Channel)

Multi-Functional General Purpose Timer Unit with 3 Timers
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects

(Full CAN/Basic CAN)

On-Chip Real Time Clock

· Up to 4 MBytes External Address Space for Code and Data

Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

Four Optional Programmable Chip-Select Signals

· Idle, Sleep, and Power Down Modes with Flexible Power Management
· Programmable Watchdog Timer and Oscillator Watchdog
· Up to 59 General Purpose I/O Lines,

partly with Selectable Input Thresholds and Hysteresis

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

· Supported by a Large Range of Development Tools like C-Compilers,

Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards

· On-Chip Bootstrap Loader
· 80-Pin MQFP Package, 0.65 mm pitch

This document describes several derivatives of the C164 group.

Table 1

enumerates

these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.

For simplicity all versions are referred to by the term C164CI throughout this document.

Table 1

C164CI Derivative Synopsis

Derivative

This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices
starting with and including design step DA.

Program
Memory

CAPCOM6

CAN Interf.

Operating
Frequency

SAK-C164CI-8R[25]M
SAF-C164CI-8R[25]M

64 KByte ROM

Full function

CAN1

20 MHz,
[25 MHz]

SAK-C164SI-8R[25]M
SAF-C164SI-8R[25]M

64 KByte ROM

Full function

---

20 MHz,
[25 MHz]

SAK-C164CL-8R[25]M
SAF-C164CL-8R[25]M

64 KByte ROM

Reduced fct. CAN1

20 MHz,
[25 MHz]

SAK-C164SL-8R[25]M
SAF-C164SL-8R[25]M

64 KByte ROM

Reduced fct. ---

20 MHz,
[25 MHz]

SAK-C164CL-6R[25]M
SAF-C164CL-6R[25]M

48 KByte ROM

Reduced fct. CAN1

20 MHz,
[25 MHz]

SAK-C164SL-6R[25]M
SAF-C164SL-6R[25]M

48 KByte ROM

Reduced fct. ---

20 MHz,
[25 MHz]

SAK-C164CI-L[25]M
SAF-C164CI-L[25]M

---

Full function

CAN1

20 MHz,
[25 MHz]

SAK-C164CI-8EM
SAF-C164CI-8EM

64 KByte OTP

Full function

CAN1

20 MHz

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:

· the derivative itself, i.e. its function set, the temperature range, and the supply voltage
· the package and the type of delivery.

For the available ordering codes for the C164CI please refer to the "Product Catalog
Microcontrollers", which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Introduction

The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS
microcontrollers are especially suited for cost sensitive applications. They combine high
CPU performance (up to 12.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM or OTP, internal RAM, and
extension RAM.

Figure 1

Logic Symbol

MCL04869

XTAL1

XTAL2

Port 0
16 Bit

Port 1
16 Bit

Port 3
9 Bit

Port 4
6 Bit

Port 8
4 Bit

Port 5
8 Bit

RSTIN

RSTOUT

NMI

ALE

WR/WRL

AREF

AGND

C164CI

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Pin Configuration
(top view)

Figure 2

*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.

Table 2

on the pages below lists the possible assignments.

The marked input signals are available only in devices with a full-function CAPCOM6.
They are not available in devices with a reduced-function CAPCOM6.

MCP04870

AREF

P5.4/AN4/T2EUD

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

*/P4.5/A20

*/P4.6/A21

R/W

ALE

Vpp/EA

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

P0H.2/AD10

P0H.0/AD8

P5.3/AN3

P8.3/CC19IO

RSTOU

RSTIN

P1H.7/A15/CC27IO

59
58

P1L.6/A6/COUT63

57
56

XTAL1

XTAL2

54
53

P1L.5/A5/COUT62

P1L.4/A4/CC62

51
50

P1L.3/A3/COUT61
P1L.2/A2/CC61

P1L.1/A1/COUT60

48
47

P1L.0/A0/CC60
P0H.7/AD15

P0H.6/AD14

45
44
43

P0H.3/AD11

42
41

P5.5/AN5/T4EUD

P3.4/T3EUD

P3.6/T3IN

P3.8/MRST
P3.9/MTSR

P3.10/TxD0

P3.13/SCLK

P3.12/BHE/WRH

P3.15/CLKOUT/FOUT

P4.0/A16/CS3

P0H.4/AD12

P0H.5/AD13

P5.6/AN6/T2IN
P5.7/AN7/T4IN

P4.1/A17/CS2
P4.2/A18/CS1

P4.3/A19/CS0

P0H.1/AD9

P1L.7/A7/CTRAP

P1H.0/A8/CC6POS0/EX0IN

P5.2/AN2

P5.1/AN1

P5.0/AN0

P8.2/CC18IO

P8.1/CC17IO

P8.0/C

C16IO

P1H.5/A13/CC25IO

P1H.4/A12/CC24IO

P1H.3/A11/EXIN/T7IN

P1H.2/A10/

6PO

/EX2IN

P1H.1/A9/

CC6PO

/EX1IN

P1H.6/A14/CC26IO

P3.11/RxD0

C164CI

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Table 2

Pin Definitions and Functions

Symbol Pin

No.

Input
Outp.

Function

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6

P5.7

76
77
78
79
2
3
4

I
I
I
I
I
I
I

Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4,

T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

AN5,

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

AN6,

T2IN

GPT1 Timer T2 Input for
Count/Gate/Reload/Capture

AN7,

T4IN

GPT1 Timer T4 Input for
Count/Gate/Reload/Capture

P3.4
P3.6
P3.8
P3.9
P3.10
P3.11
P3.12

P3.13
P3.15

8
9
10
11
12
13
14

15
16

I
I
I/O
I/O
O
I/O
O
O
I/O
O
O

Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
The following Port 3 pins also serve for alternate functions:
T3EUD

GPT1 Timer T3 External Up/Down Control Input

T3IN

GPT1 Timer T3 Count/Gate Input

MRST

SSC Master-Receive/Slave-Transmit Inp./Outp.

MTSR

SSC Master-Transmit/Slave-Receive Outp./Inp.

TxD0

ASC0 Clock/Data Output (Async./Sync.)

RxD0

ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

BHE

External Memory High Byte Enable Signal,

WRH

External Memory High Byte Write Strobe

SCLK

SSC Master Clock Output / Slave Clock Input.

CLKOUT

System Clock Output (= CPU Clock),

FOUT

Programmable Frequency Output

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

P4.0

P4.1

P4.2

P4.3

P4.5

P4.6

O
O
O
O
O
O
O
O
O
I
O
O

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

A16

Least Significant Segment Address Line,

CS3

Chip Select 3 Output

A17

Segment Address Line,

CS2

Chip Select 2 Output

A18

Segment Address Line,

CS1

Chip Select 1 Output

A19

Segment Address Line,

CS0

Chip Select 0 Output

A20

Segment Address Line,

CAN1_RxD CAN 1 Receive Data Input
A21

Most Significant Segment Address Line,

CAN1_TxD CAN 1 Transmit Data Output

External Memory Read Strobe. RD is activated for every
external instruction or data read access.

WR/
WRL

External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a
16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.

ALE

Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.

Table 2

Pin Definitions and Functions (cont'd)

Symbol Pin

No.

Input
Outp.

Function

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

EA/

External Access Enable pin.
A low level at this pin during and after Reset forces the
C164CI to latch the configuration from PORT0 and pin RD,
and to begin instruction execution out of external memory.
A high level forces the C164CI to latch the configuration
from pins RD and ALE, and to begin instruction execution out
of the internal program memory.
"ROMless" versions must have this pin tied to `0'.

Note: This pin also accepts the programming voltage for the

OTP derivatives.

PORT0
P0L.0-7

P0H.0-7

29-
36
37-39,
42-46

PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

D0 D7

P0H.0 P0H.7:

I/O

D8 D15

Multiplexed bus modes:
Data Path Width:

8-bit

16-bit

P0L.0 P0L.7:

AD0 AD7

P0H.0 P0H.7:

A8 A15

AD8 AD15

Table 2

Pin Definitions and Functions (cont'd)

Symbol Pin

No.

Input
Outp.

Function

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

PORT1
P1L.0-7

P1H.0-7

P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7

P1H.0

P1H.1

P1H.2

P1H.3

P1H.4
P1H.5
P1H.6
P1H.7

47-52,
57-59
59,
62-68

47
48
49
50
51
52
57
58

65
66
67
68

I/O
O
I/O
O
I/O
O
O
I

I
I
I
I
I
I
I

I/O
I/O
I/O
I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alt. functions:
CC60

CAPCOM6: Input / Output of Channel 0

COUT60

CAPCOM6: Output of Channel 0

CC61

CAPCOM6: Input / Output of Channel 1

COUT61

CAPCOM6: Output of Channel 1

CC62

CAPCOM6: Input / Output of Channel 2

COUT62

CAPCOM6: Output of Channel 2

COUT63

Output of 10-bit Compare Channel

CTRAP

CAPCOM6: Trap Input

CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the compare outputs of the
CAPCOM6 unit to the logic level defined by software.
CC6POS0 CAPCOM6: Position 0 Input, **)
EX0IN

Fast External Interrupt 0 Input

CC6POS1 CAPCOM6: Position 1 Input, **)
EX1IN

Fast External Interrupt 1 Input

CC6POS2 CAPCOM6: Position 2 Input, **)
EX2IN

Fast External Interrupt 2 Input

EX3IN

Fast External Interrupt 3 Input,

T7IN

CAPCOM2: Timer T7 Count Input

CC24IO

CAPCOM2: CC24 Capture Inp./Compare Outp.

CC25IO

CAPCOM2: CC25 Capture Inp./Compare Outp.

CC26IO

CAPCOM2: CC26 Capture Inp./Compare Outp.

CC27IO

CAPCOM2: CC27 Capture Inp./Compare Outp.

Note: The marked (**) input signals are available only in

devices with a full function CAPCOM6.

Table 2

Pin Definitions and Functions (cont'd)

Symbol Pin

No.

Input
Outp.

Function

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

XTAL2
XTAL1

54
55

O
I

XTAL2:

Output of the oscillator amplifier circuit.

XTAL1:

Input to the oscillator amplifier and input to
the internal clock generator

To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

RSTIN

I/O

Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C164CI.
An internal pullup resistor permits power-on reset using only
a capacitor connected to

A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.

RST
OUT

Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C164CI to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

Table 2

Pin Definitions and Functions (cont'd)

Symbol Pin

No.

Input
Outp.

Function

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

· Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared

automatically after a reset.

· The reset indication flags always indicate a long hardware reset.
· The PORT0 configuration is treated as if it were a hardware reset. In particular, the

bootstrap loader may be activated when P0L.4 is low.

· Pin RSTIN may only be connected to external reset devices with an open drain output

driver.

· A short hardware reset is extended to the duration of the internal reset sequence.

P8.0

P8.1

P8.2

P8.3

I/O
I
I/O
O
I/O
I
I/O
O

Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCOM2 and serial interface lines.

CC16IO

CAPCOM2: CC16 Capture Inp./Compare Outp.,

CAN1_RxD CAN 1 Receive Data Input
CC17IO

CAPCOM2: CC17 Capture Inp./Compare Outp.,

CAN1_TxD CAN 1 Transmit Data Output
CC18IO

CAPCOM2: CC18 Capture Inp./Compare Outp.,

CAN1_RxD CAN 1 Receive Data Input
CC19IO

CAPCOM2: CC19 Capture Inp./Compare Outp.,

CAN1_TxD CAN 1 Transmit Data Output

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

7, 21,
40, 53,
61

Digital Supply Voltage:
+5 V during normal operation and idle mode.
2.5 V during power down mode.

6, 20,
41, 56,
60

Digital Ground.

The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.

Table 2

Pin Definitions and Functions (cont'd)

Symbol Pin

No.

Input
Outp.

Function

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Functional Description

The architecture of the C164CI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C164CI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

Figure 3

Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see

Figure 3

The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during
initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules
that are disabled consume neither address space nor port pins.

C166-Core

CPU

Interrupt Bus

XTAL

MCB04323_4ci

Osc / PLL

RTC

WDT

Interrupt Controller 16-Level

Priority

PEC

External Instr. / Data

GPT1

SSC

BRGen

(SPI)

ASC0

BRGen

(USART)

ADC

10-Bit

Channels

CCOM2

CCOM6

T12

T13

EBC

XBUS Control

External Bus

Control

IRAM

l P

Internal

RAM

2 KByte

ProgMem

ROM: 48/64

OTP: 64

KByte

Data

CAN

Rev 2.0B active

Instr. / Data

Port 0

XRAM

2 KByte

rt 1

Port 5

Port 3

Port 8

rt 4

-C

-B

it D

)

Peripheral Data Bus

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Memory Organization

The memory space of the C164CI is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.

The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip
mask-programmable ROM (not in the ROM-less derivative, of course) for code or
constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to
segment 0 or segment 1.
The OTP memory can be programmed by the CPU itself (in system, e.g. during booting)
or directly via an external interface (e.g. before assembly). The programming time is
approx. 100

µs per word. An external programming voltage

= 11.5 V must be

supplied for this purpose (via pin EA/

2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
..., RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like external memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum speed.

In order to meet the needs of designs where more memory is required than is provided
on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the
microcontroller.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:

16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to different resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. The C164CI offers the possibility to switch the CS outputs to an
unlatched mode. In this mode the internal filter logic is switched off and the CS signals
are directly generated from the address. The unlatched CS mode is enabled by setting
CSCFG (SYSCON.6).

For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an
address space of 4 MBytes is used.

Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4,

the CAN lines override the segment address lines and the segment address
output on Port 4 is therefore limited to 4 bits i.e. address lines A19 ... A16.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C164CI's instructions can be executed
in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and
rotate instructions are always processed during one machine cycle independent of the
number of bits to be shifted. All multiple-cycle instructions have been optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16

× 16 bit multiplication

in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-
called `Jump Cache', reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.

Figure 4

CPU Block Diagram

MCB02147

CPU

STKOV

STKUN

Instr. Reg.

Instr. Ptr.

Exec. Unit

4-Stage

Pipeline

MDH

MDL

PSW

SYSCON

Context Ptr.

Mul/Div-HW

R15

General

Purpose

Registers

Bit-Mask Gen

Barrel - Shifter

ALU

(16-bit)

Data Page Ptr.

Code Seg. Ptr.

Internal

RAM

R15

ROM

BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4

ADDRSEL 4

ADDRSEL 3

ADDRSEL 2

ADDRSEL 1

C164CI/SI

C164CL/SL

Data Sheet

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The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.

A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient C164CI instruction set which includes
the following instruction classes:

Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

C164CI/SI

C164CL/SL

Data Sheet

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Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of
internal program execution), the C164CI is capable of reacting very fast to the
occurrence of non-deterministic events.

The architecture of the C164CI supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
`stolen' from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related register, each source can be programmed to one of sixteen interrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the `TRAP' instruction in combination with
an individual trap (interrupt) number.

Table 3

shows all of the possible C164CI interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Table 3

C164CI Interrupt Nodes

Source of Interrupt or
PEC Service Request

Request
Flag

Enable
Flag

Interrupt
Vector

Vector
Location

Trap
Number

Fast External Interrupt 0 CC8IR

CC8IE

CC8INT

00'0060

Fast External Interrupt 1 CC9IR

CC9IE

CC9INT

00'0064

Fast External Interrupt 2 CC10IR

CC10IE

CC10INT

00'0068

Fast External Interrupt 3 CC11IR

CC11IE

CC11INT

00'006C

GPT1 Timer 2

T2IR

T2IE

T2INT

00'0088

GPT1 Timer 3

T3IR

T3IE

T3INT

00'008C

GPT1 Timer 4

T4IR

T4IE

T4INT

00'0090

A/D Conversion
Complete

ADCIR

ADCIE

ADCINT

00'00A0

A/D Overrun Error

ADEIR

ADEIE

ADEINT

00'00A4

ASC0 Transmit

S0TIR

S0TIE

S0TINT

00'00A8

ASC0 Transmit Buffer

S0TBIR

S0TBIE

S0TBINT

00'011C

ASC0 Receive

S0RIR

S0RIE

S0RINT

00'00AC

ASC0 Error

S0EIR

S0EIE

S0EINT

00'00B0

SSC Transmit

SCTIR

SCTIE

SCTINT

00'00B4

SSC Receive

SCRIR

SCRIE

SCRINT

00'00B8

SSC Error

SCEIR

SCEIE

SCEINT

00'00BC

CAPCOM Register 16

CC16IR

CC16IE

CC16INT

00'00C0

CAPCOM Register 17

CC17IR

CC17IE

CC17INT

00'00C4

CAPCOM Register 18

CC18IR

CC18IE

CC18INT

00'00C8

CAPCOM Register 19

CC19IR

CC19IE

CC19INT

00'00CC

CAPCOM Register 24

CC24IR

CC24IE

CC24INT

00'00E0

CAPCOM Register 25

CC25IR

CC25IE

CC25INT

00'00E4

CAPCOM Register 26

CC26IR

CC26IE

CC26INT

00'00E8

CAPCOM Register 27

CC27IR

CC27IE

CC27INT

00'00EC

CAPCOM Timer 7

T7IR

T7IE

T7INT

00'00F4

CAPCOM Timer 8

T8IR

T8IE

T8INT

00'00F8

CAPCOM6 Interrupt

CC6IR

CC6IE

CC6INT

00'00FC

CAN Interface 1

XP0IR

XP0IE

XP0INT

00'0100

PLL/OWD and RTC

XP3IR

XP3IE

XP3INT

00'010C

C164CI/SI

C164CL/SL

Data Sheet

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The C164CI also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.

Table 4

shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4

Hardware Trap Summary

Exception Condition

Trap
Flag

Trap
Vector

Vector
Location

Trap
Number

Trap
Priority

Reset Functions:
Hardware Reset
Software Reset
W-dog Timer Overflow

RESET
RESET
RESET

00'0000

III
III
III

Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow

NMI
STKOF
STKUF

NMITRAP
STOTRAP
STUTRAP

00'0008

00'0010

00'0018

II
II
II

Class B Hardware Traps:
Undefined Opcode
Protected Instruction

Fault

Illegal Word Operand

Access

Illegal Instruction

Access

Illegal External Bus

Access

UNDOPC
PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP
BTRAP

BTRAP

00'0028

I
I

Reserved

[2C

]

[0B

]

Software Traps
TRAP Instruction

Any
[00'0000

00'01FC

]

in steps
of 4

Any
[00

]

Current
CPU
Priority

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

The Capture/Compare Unit CAPCOM2

The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering the capture function, or
as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (`capture'd) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.

Table 5

Compare Modes (CAPCOM2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;
several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;
several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;
only one compare interrupt per timer period is generated

Mode 3

Pin set `1' on match; pin reset `0' on compare time overflow;
only one compare event per timer period is generated

Double
Register Mode

Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24

Registers CC17 & CC25

Registers CC18 & CC26

Registers CC19 & CC27

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Data Sheet

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The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one 10-bit compare channel.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions. The compare channel can
generate a single PWM output signal and is further used to modulate the capture/
compare output signals.
In capture mode the contents of compare timer 12 is stored in the capture registers upon
a signal transition at pins CCx.

Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled CPU clock.

Figure 5

CAPCOM6 Block Diagram

For motor control applications both subunits may generate versatile multichannel PWM
signals which are basically either controlled by compare timer 12 or by a typical hall
sensor pattern at the interrupt inputs (block commutation).

Note: Multichannel signal generation is provided only in devices with a full CAPCOM6.

Control

CC Channel 0

CC60

CC Channel 1

CC61

CC Channel 2

CC62

MCB04109

Prescaler

Offset Register

T12OF

Compare

Timer T12

16-Bit

Period Register

T12P

Mode

Select Register

CC6MSEL

Trap Register

Port

Control

Logic

Control Register

CTCON

Compare Register

CMP13

Prescaler

Compare

Timer T13

10-Bit

Period Register

T13P

Block

Commutation

Control

CC6MCON.H

CC60
COUT60

CC61
COUT61

CC62
COUT62

CTRAP

CC6POS0
CC6POS1
CC6POS2

CPU

COUT63

The timer registers (T12, T13) are not directly accessible.
The period and offset registers are loading a value into the timer registers.
The shaded blocks are available in the full function module only.

C164CI/SI

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Data Sheet

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General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates three 16-bit timers. Each timer may operate independently in
a number of different modes, or may be concatenated with another timer.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the `gate' level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL.

C164CI/SI

C164CL/SL

Data Sheet

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Real Time Clock

The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks,
a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible
via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip
oscillator frequency divided by 32 via a separate clock driver (

RTC

OSC

/32) and is

therefore independent from the selected clock generation mode of the C164CI. All timers
count up.

The RTC module can be used for different purposes:

· System clock to determine the current time and date
· Cyclic time based interrupt
· 48-bit timer for long term measurements

Figure 7

RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

MCD04432

T14REL

T14

8:1

RTC

RTCL

RTCH

Interrupt
Request

Reload

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Data Sheet

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A/D Converter

For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels
and a sample and hold circuit has been integrated on-chip. It uses the method of
successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable and can so be adjusted to the external circuitry.

Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.

For applications which require less than 8 analog input channels, the remaining channel
inputs can be used as digital input port pins.

The A/D converter of the C164CI supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels (standard or extension) are sequentially sampled and converted. In
the Auto Scan Continuous mode, the number of prespecified channels is repeatedly
sampled and converted. In addition, the conversion of a specific channel can be inserted
(injected) into a running sequence without disturbing this sequence. This is called
Channel Injection Mode.

The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.

After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.

These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.

In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).

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Serial Channels

Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 Kbit/s and
half-duplex synchronous communication at up to 3.1 Mbit/s (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 Mbit/s
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception and error handling
3 separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.

C164CI/SI

C164CL/SL

Data Sheet

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CAN-Module

The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.

The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/
s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus
transceiver. The interface pins are assigned via software.

Note: When the CAN interface is assigned to Port 4, the respective segment address

lines on Port 4 cannot be used. This will limit the external address space.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip's start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20

µs and 336 ms can be

monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).

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Data Sheet

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Parallel Ports

The C164CI provides up to 59 I/O lines which are organized into five input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of three I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs.

The input threshold of Port 3, Port 4, and Port 8 is selectable (TTL or CMOS like), where
the special CMOS like input threshold reduces noise sensitivity due to the input
hysteresis. The input threshold may be selected individually for each byte of the
respective ports.

All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17 ... A16 and
the optional chip select signals in systems where segmentation is enabled to access
more than 64 KBytes of memory.
Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of
the CAPCOM units and/or serve as external interrupt inputs.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output CLKOUT (or the programmable
frequency output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.

The edge characteristics (transition time) and driver characteristics (output current) of
the C164CI's port drivers can be selected via the Port Output Control registers
(POCONx).

C164CI/SI

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Data Sheet

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Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.

In direct drive mode the PLL base frequency is used directly (

CPU

= 2 ... 5 MHz).

In prescaler mode the PLL base frequency is divided by 2 (

CPU

= 1 ... 2.5 MHz).

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = `1') the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.

Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.

Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Power Management

The C164CI provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):

· Power Saving Modes switch the C164CI into a special operating mode (control via

instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.

· Clock Generation Management controls the distribution and the frequency of

internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C164CI run at a CPU clock frequency of

OSC

/1 ... 32 (half

for prescaler operation) which drastically reduces the consumed power. The PLL can
be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.

· Peripheral Management permits temporary disabling of peripheral modules (control

via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.

The on-chip RTC supports intermittend operation of the C164CI by generating cyclic
wakeup signals. This offers full performance to quickly react on action requests while the
intermittend sleep phases greatly reduce the average power consumption of the system.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Instruction Set Summary

Table 6

lists the instructions of the C164CI in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the "C166 Family Instruction Set Manual".

This document also provides a detailled description of each instruction.

Table 6

Instruction Set Summary

Mnemonic

Description

Bytes

ADD(B)

Add word (byte) operands

2 / 4

ADDC(B)

Add word (byte) operands with Carry

2 / 4

SUB(B)

Subtract word (byte) operands

2 / 4

SUBC(B)

Subtract word (byte) operands with Carry

2 / 4

MUL(U)

(Un)Signed multiply direct GPR by direct GPR (16-16-bit)

DIV(U)

(Un)Signed divide register MDL by direct GPR (16-/16-bit)

DIVL(U)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)

CPL(B)

Complement direct word (byte) GPR

NEG(B)

Negate direct word (byte) GPR

AND(B)

Bitwise AND, (word/byte operands)

2 / 4

OR(B)

Bitwise OR, (word/byte operands)

2 / 4

XOR(B)

Bitwise XOR, (word/byte operands)

2 / 4

BCLR

Clear direct bit

BSET

Set direct bit

BMOV(N)

Move (negated) direct bit to direct bit

BAND, BOR,
BXOR

AND/OR/XOR direct bit with direct bit

BCMP

Compare direct bit to direct bit

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data

CMP(B)

Compare word (byte) operands

2 / 4

CMPD1/2

Compare word data to GPR and decrement GPR by 1/2

2 / 4

CMPI1/2

Compare word data to GPR and increment GPR by 1/2

2 / 4

PRIOR

Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR

SHL / SHR

Shift left/right direct word GPR

ROL / ROR

Rotate left/right direct word GPR

ASHR

Arithmetic (sign bit) shift right direct word GPR

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

MOV(B)

Move word (byte) data

2 / 4

MOVBS

Move byte operand to word operand with sign extension

2 / 4

MOVBZ

2 / 4

JMPA, JMPI,
JMPR

Jump absolute/indirect/relative if condition is met

JMPS

Jump absolute to a code segment

J(N)B

Jump relative if direct bit is (not) set

JBC

Jump relative and clear bit if direct bit is set

JNBS

Jump relative and set bit if direct bit is not set

CALLA, CALLI,
CALLR

Call absolute/indirect/relative subroutine if condition is met

CALLS

Call absolute subroutine in any code segment

PCALL

Push direct word register onto system stack and call
absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

PUSH, POP

Push/pop direct word register onto/from system stack

SCXT

Push direct word register onto system stack und update
register with word operand

RET

Return from intra-segment subroutine

RETS

Return from inter-segment subroutine

RETP

Return from intra-segment subroutine and pop direct
word register from system stack

RETI

Return from interrupt service subroutine

SRST

Software Reset

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode (supposes NMI-pin being low)

SRVWDT

Service Watchdog Timer

DISWDT

Disable Watchdog Timer

EINIT

Signify End-of-Initialization on RSTOUT-pin

ATOMIC

Begin ATOMIC sequence

EXTR

Begin EXTended Register sequence

EXTP(R)

Begin EXTended Page (and Register) sequence

2 / 4

EXTS(R)

Begin EXTended Segment (and Register) sequence

2 / 4

NOP

Null operation

Table 6

Instruction Set Summary (cont'd)

Mnemonic

Description

Bytes

Move byte operand to word operand with zero extension

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Special Function Registers Overview

Table 7

lists all SFRs which are implemented in the C164CI in alphabetical order.

Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical
Address". Registers within on-chip X-peripherals are marked with the letter "X" in column
"Physical Address".

An SFR can be specified via its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).

Table 7

C164CI Registers, Ordered by Name

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

ADCIC

b FF98

A/D Converter End of Conversion
Interrupt Control Register

0000

ADCON

b FFA0

A/D Converter Control Register

0000

ADDAT

FEA0

A/D Converter Result Register

0000

ADDAT2

F0A0

E 50

A/D Converter 2 Result Register

0000

ADDRSEL1

FE18

Address Select Register 1

0000

ADDRSEL2

FE1A

Address Select Register 2

0000

ADDRSEL3

FE1C

Address Select Register 3

0000

ADDRSEL4

FE1E

Address Select Register 4

0000

ADEIC

b FF9A

A/D Converter Overrun Error Interrupt
Control Register

0000

BUSCON0 b FF0C

Bus Configuration Register 0

0000

BUSCON1 b FF14

Bus Configuration Register 1

0000

BUSCON2 b FF16

Bus Configuration Register 2

0000

BUSCON3 b FF18

Bus Configuration Register 3

0000

BUSCON4 b FF1A

Bus Configuration Register 4

0000

C1BTR

EF04

X ---

CAN1 Bit Timing Register

UUUU

C1CSR

EF00

X ---

CAN1 Control / Status Register

XX01

C1GMS

EF06

X ---

CAN1 Global Mask Short

UFUU

C1LARn

EFn4

X ---

CAN Lower Arbitration Register (msg. n)

UUUU

C1LGML

EF0A

X ---

CAN Lower Global Mask Long

UUUU

C1LMLM

EF0E

X ---

CAN Lower Mask of Last Message

UUUU

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

C1MCFGn

EFn6

X ---

CAN Message Configuration Register
(msg. n)

C1MCRn

EFn0

X ---

CAN Message Control Register (msg. n)

UUUU

C1PCIR

EF02

X ---

CAN1 Port Control / Interrupt Register

XXXX

C1UARn

EFn2

X ---

CAN Upper Arbitration Register (msg. n)

UUUU

C1UGML

EF08

X ---

CAN Upper Global Mask Long

UUUU

C1UMLM

EF0C

X ---

CAN Upper Mask of Last Message

UUUU

CC10IC

b FF8C

External Interrupt 2 Control Register

0000

CC11IC

b FF8E

External Interrupt 3 Control Register

0000

CC16

FE60

CAPCOM Register 16

0000

CC16IC

b F160

E B0

CAPCOM Reg. 16 Interrupt Ctrl. Reg.

0000

CC17

FE62

CAPCOM Register 17

0000

CC17IC

b F162

E B1

CAPCOM Reg. 17 Interrupt Ctrl. Reg.

0000

CC18

FE64

CAPCOM Register 18

0000

CC18IC

b F164

E B2

CAPCOM Reg. 18 Interrupt Ctrl. Reg.

0000

CC19

FE66

CAPCOM Register 19

0000

CC19IC

b F166

E B3

CAPCOM Reg. 19 Interrupt Ctrl. Reg.

0000

CC20

FE68

CAPCOM Register 20

0000

CC20IC

b F168

E B4

CAPCOM Reg. 20 Interrupt Ctrl. Reg.

0000

CC21

FE6A

CAPCOM Register 21

0000

CC21IC

b F16A

E B5

CAPCOM Reg. 21 Interrupt Ctrl. Reg.

0000

CC22

FE6C

CAPCOM Register 22

0000

CC22IC

b F16C

E B6

CAPCOM Reg. 22 Interrupt Ctrl. Reg.

0000

CC23

FE6E

CAPCOM Register 23

0000

CC23IC

b F16E

E B7

CAPCOM Reg. 23 Interrupt Ctrl. Reg.

0000

CC24

FE70

CAPCOM Register 24

0000

CC24IC

b F170

E B8

CAPCOM Reg. 24 Interrupt Ctrl. Reg.

0000

CC25

FE72

CAPCOM Register 25

0000

CC25IC

b F172

E B9

CAPCOM Reg. 25 Interrupt Ctrl. Reg.

0000

CC26

FE74

CAPCOM Register 26

0000

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

CC26IC

b F174

E BA

CAPCOM Reg. 26 Interrupt Ctrl. Reg.

0000

CC27

FE76

CAPCOM Register 27

0000

CC27IC

b F176

E BB

CAPCOM Reg. 27 Interrupt Ctrl. Reg.

0000

CC28

FE78

CAPCOM Register 28

0000

CC28IC

b F178

E BC

CAPCOM Reg. 28 Interrupt Ctrl. Reg.

0000

CC29

FE7A

CAPCOM Register 29

0000

CC29IC

b F184

E C2

CAPCOM Reg. 29 Interrupt Ctrl. Reg.

0000

CC30

FE7C

CAPCOM Register 30

0000

CC30IC

b F18C

E C6

CAPCOM Reg. 30 Interrupt Ctrl. Reg.

0000

CC31

FE7E

CAPCOM Register 31

0000

CC31IC

b F194

E CA

CAPCOM Reg. 31 Interrupt Ctrl. Reg.

0000

CC60

FE30

CAPCOM 6 Register 0

0000

CC61

FE32

CAPCOM 6 Register 1

0000

CC62

FE34

CAPCOM 6 Register 2

0000

CC6EIC

b F188

E C4

CAPCOM 6 Emergency Interrrupt
Control Register

0000

CC6CIC

b F17E

E BF

CAPCOM 6 Interrupt Control Register

0000

CC6MCON b FF32

CAPCOM 6 Mode Control Register

00FF

CC6MIC

b FF36

CAPCOM 6 Mode Interrupt Ctrl. Reg.

0000

CC6MSEL

F036

E 1B

CAPCOM 6 Mode Select Register

0000

CC8IC

b FF88

External Interrupt 0 Control Register

0000

CC9IC

b FF8A

External Interrupt 1 Control Register

0000

CCM4

b FF22

CAPCOM Mode Control Register 4

0000

CCM5

b FF24

CAPCOM Mode Control Register 5

0000

CCM6

b FF26

CAPCOM Mode Control Register 6

0000

CCM7

b FF28

CAPCOM Mode Control Register 7

0000

CMP13

FE36

CAPCOM 6 Timer 13 Compare Reg.

0000

FE10

CPU Context Pointer Register

FC00

CSP

FE08

CPU Code Segment Pointer Register
(8 bits, not directly writeable)

0000

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

CTCON

b FF30

CAPCOM 6 Compare Timer Ctrl. Reg.

1010

DP0H

b F102

E 81

P0H Direction Control Register

DP0L

b F100

E 80

P0L Direction Control Register

DP1H

b F106

E 83

P1H Direction Control Register

DP1L

b F104

E 82

P1L Direction Control Register

DP3

b FFC6

Port 3 Direction Control Register

0000

DP4

b FFCA

Port 4 Direction Control Register

DP8

b FFD6

Port 8 Direction Control Register

DPP0

FE00

CPU Data Page Pointer 0 Reg. (10 bits)

0000

DPP1

FE02

CPU Data Page Pointer 1 Reg. (10 bits)

0001

DPP2

FE04

CPU Data Page Pointer 2 Reg. (10 bits)

0002

DPP3

FE06

CPU Data Page Pointer 3 Reg. (10 bits)

0003

EXICON

b F1C0

E E0

External Interrupt Control Register

0000

EXISEL

b F1DA

E ED

External Interrupt Source Select Reg.

0000

FOCON

b FFAA

Frequency Output Control Register

0000

IDCHIP

F07C

E 3E

Identifier

XXXX

IDMANUF

F07E

E 3F

Identifier

1820

IDMEM

F07A

E 3D

Identifier

XXXX

IDPROG

F078

E 3C

Identifier

XXXX

IDMEM2

F076

E 3B

Identifier

XXXX

ISNC

b F1DE

E EF

Interrupt Subnode Control Register

0000

MDC

b FF0E

CPU Multiply Divide Control Register

0000

MDH

FE0C

CPU Multiply Divide Reg. High Word

0000

MDL

FE0E

CPU Multiply Divide Reg. Low Word

0000

ODP3

b F1C6

E E3

Port 3 Open Drain Control Register

0000

ODP4

b F1CA

E E5

Port 4 Open Drain Control Register

ODP8

b F1D6

E EB

Port 8 Open Drain Control Register

ONES

b FF1E

Constant Value 1's Register (read only)

FFFF

OPAD

EDC2

X ---

OTP Progr. Interface Address Register

0000

OPCTRL

EDC0

X ---

OTP Progr. Interface Control Register

0007

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

OPDAT

EDC4

X ---

OTP Progr. Interface Data Register

0000

P0H

b FF02

Port 0 High Reg. (Upper half of PORT0)

P0L

b FF00

Port 0 Low Reg. (Lower half of PORT0)

P1H

b FF06

Port 1 High Reg. (Upper half of PORT1)

P1L

b FF04

Port 1 Low Reg. (Lower half of PORT1)

b FFC4

Port 3 Register

0000

b FFC8

Port 4 Register (7 bits)

b FFA2

Port 5 Register (read only)

XXXX

P5DIDIS

b FFA4

Port 5 Digital Input Disable Register

0000

b FFD4

Port 8 Register (8 bits)

PECC0

FEC0

PEC Channel 0 Control Register

0000

PECC1

FEC2

PEC Channel 1 Control Register

0000

PECC2

FEC4

PEC Channel 2 Control Register

0000

PECC3

FEC6

PEC Channel 3 Control Register

0000

PECC4

FEC8

PEC Channel 4 Control Register

0000

PECC5

FECA

PEC Channel 5 Control Register

0000

PECC6

FECC

PEC Channel 6 Control Register

0000

PECC7

FECE

PEC Channel 7 Control Register

0000

PICON

b F1C4

E E2

Port Input Threshold Control Register

0000

POCON0H

F082

E 41

Port P0H Output Control Register

0011

POCON0L

F080

E 40

Port P0L Output Control Register

0011

POCON1H

F086

E 43

Port P1H Output Control Register

0011

POCON1L

F084

E 42

Port P1L Output Control Register

0011

POCON20

F0AA

E 55

Dedicated Pin Output Control Register

0000

POCON3

F08A

E 45

Port P3 Output Control Register

2222

POCON4

F08C

E 46

Port P4 Output Control Register

0010

POCON8

F092

E 49

Port P8 Output Control Register

0022

PSW

b FF10

CPU Program Status Word

0000

RP0H

b F108

E 84

System Startup Config. Reg. (Rd. only)

RSTCON

b F1E0

m ---

Reset Control Register

00XX

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

RTCH

F0D6

E 6B

RTC High Register

RTCL

F0D4

E 6A

RTC Low Register

S0BG

FEB4

Serial Channel 0 Baud Rate Generator
Reload Register

0000

S0CON

b FFB0

Serial Channel 0 Control Register

0000

S0EIC

b FF70

Serial Channel 0 Error Interrupt Ctrl.
Reg.

0000

S0RBUF

FEB2

Serial Channel 0 Receive Buffer Reg.
(read only)

XXXX

S0RIC

b FF6E

Serial Channel 0 Receive Interrupt
Control Register

0000

S0TBIC

b F19C

E CE

Serial Channel 0 Transmit Buffer
Interrupt Control Register

0000

S0TBUF

FEB0

Serial Channel 0 Transmit Buffer Reg.
(write only)

0000

S0TIC

b FF6C

Serial Channel 0 Transmit Interrupt
Control Register

0000

FE12

CPU System Stack Pointer Register

FC00

SSCBR

F0B4

E 5A

SSC Baudrate Register

0000

SSCCON

b FFB2

SSC Control Register

0000

SSCEIC

b FF76

SSC Error Interrupt Control Register

0000

SSCRB

F0B2

E 59

SSC Receive Buffer

XXXX

SSCRIC

b FF74

SSC Receive Interrupt Control Register

0000

SSCTB

F0B0

E 58

SSC Transmit Buffer

0000

SSCTIC

b FF72

SSC Transmit Interrupt Control Register

0000

STKOV

FE14

CPU Stack Overflow Pointer Register

FA00

STKUN

FE16

CPU Stack Underflow Pointer Register

FC00

SYSCON

b FF12

CPU System Configuration Register

0xx0

SYSCON1 b F1DC

E EE

CPU System Configuration Register 1

0000

SYSCON2 b F1D0

E E8

CPU System Configuration Register 2

0000

SYSCON3 b F1D4

E EA

CPU System Configuration Register 3

0000

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

T12IC

b F190

E C8

CAPCOM 6 Timer 12 Interrupt Ctrl. Reg.

0000

T12OF

F034

E 1A

CAPCOM 6 Timer 12 Offset Register

0000

T12P

F030

E 18

CAPCOM 6 Timer 12 Period Register

0000

T13IC

b F198

E CC

CAPCOM 6 Timer 13 Interrupt Ctrl. Reg.

0000

T13P

F032

E 19

CAPCOM 6 Timer 13 Period Register

0000

T14

F0D2

E 69

RTC Timer 14 Register

T14REL

F0D0

E 68

RTC Timer 14 Reload Register

FE40

GPT1 Timer 2 Register

0000

T2CON

b FF40

GPT1 Timer 2 Control Register

0000

T2IC

b FF60

GPT1 Timer 2 Interrupt Control Register

0000

FE42

GPT1 Timer 3 Register

0000

T3CON

b FF42

GPT1 Timer 3 Control Register

0000

T3IC

b FF62

GPT1 Timer 3 Interrupt Control Register

0000

FE44

GPT1 Timer 4 Register

0000

T4CON

b FF44

GPT1 Timer 4 Control Register

0000

T4IC

b FF64

GPT1 Timer 4 Interrupt Control Register

0000

F050

E 28

CAPCOM Timer 7 Register

0000

T78CON

b FF20

CAPCOM Timer 7 and 8 Ctrl. Reg.

0000

T7IC

b F17A

E BD

CAPCOM Timer 7 Interrupt Ctrl. Reg.

0000

T7REL

F054

E 2A

CAPCOM Timer 7 Reload Register

0000

F052

E 29

CAPCOM Timer 8 Register

0000

T8IC

b F17C

E BE

CAPCOM Timer 8 Interrupt Ctrl. Reg.

0000

T8REL

F056

E 2B

CAPCOM Timer 8 Reload Register

0000

TFR

b FFAC

Trap Flag Register

0000

TRCON

b FF34

CAPCOM 6 Trap Enable Ctrl. Reg.

00XX

WDT

FEAE

Watchdog Timer Register (read only)

0000

WDTCON

FFAE

Watchdog Timer Control Register

00xx

XP0IC

b F186

E C3

CAN1 Module Interrupt Control Register

0000

XP1IC

b F18E

E C7

Unassigned Interrupt Control Reg.

0000

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Note: The three registers of the OTP programming interface are, of course, only

implemented in the OTP versions of the C164CI.

XP3IC

b F19E

E CF

PLL/RTC Interrupt Control Register

0000

ZEROS

b FF1C

Constant Value 0's Register (read only)

0000

The system configuration is selected during reset.

The reset value depends on the indicated reset source.

Table 7

C164CI Registers, Ordered by Name (cont'd)

Name

Physical
Address

8-Bit
Addr.

Description

Reset

Value

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Absolute Maximum Ratings

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (

) the

voltage on

pins with respect to ground (

) must not exceed the values

defined by the absolute maximum ratings.

Table 8

Absolute Maximum Rating Parameters

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Storage temperature

-65

150

°C

Junction temperature

-40

150

°C

under bias

Voltage on

pins with

respect to ground (

)

-0.5

6.5

Voltage on any pin with
respect to ground (

)

-0.5

+ 0.5 V

Input current on any pin
during overload condition

-10

Absolute sum of all input
currents during overload
condition

|100|

Power dissipation

DISS

1.5

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct
operation of the C164CI. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.

Table 9

Operating Condition Parameters

Parameter

Symbol

Limit Values

Unit Notes

min.

max.

Digital supply voltage

4.75

5.5

Active mode,

CPUmax

= 25 MHz

2.5

Output voltages and output currents will be reduced when

leaves the range defined for active mode.

5.5

PowerDown mode

Digital ground voltage

Reference voltage

Overload current

±5

Per pin

2)3)

Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e.

+ 0.5 V or

- 0.5 V). The absolute sum of input overload

currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc.

Not 100% tested, guaranteed by design and characterization.

Absolute sum of overload
currents

External Load
Capacitance

100

Pin drivers in
default mode

4)5)

The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (

The current ROM-version of the C164CI is equipped with port drivers, which provide reduced driving capability
and reduced control. Please refer to the actual errata sheet for details.

Ambient temperature

°C

SAB-C164CI ...

-40

°C

SAF-C164CI ...

-40

125

°C

SAK-C164CI ...

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C164CI
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column "Symbol":

CC (Controller Characteristics):
The logic of the C164CI will provide signals with the respective characteristics.

SR (System Requirement):
The external system must provide signals with the respective characteristics to the
C164CI.

DC Characteristics
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

max.

Input low voltage (TTL,
all except XTAL1)

SR -0.5

0.2

- 0.1

Input low voltage XTAL1

IL2

SR -0.5

0.3

Input low voltage
(Special Threshold)

ILS

SR -0.5

2.0

Input high voltage (TTL,
all except RSTIN, XTAL1)

SR 0.2

+ 0.9

0.5

Input high voltage RSTIN
(when operated as input)

IH1

SR 0.6

0.5

Input high voltage XTAL1

IH2

SR 0.7

0.5

Input high voltage
(Special Threshold)

IHS

SR 0.8

- 0.2

0.5

Input Hysteresis
(Special Threshold)

HYS

400

Series resistance
= 0

Output low voltage

1.0

OLmax

0.45

OLnom

3)4)

Output high voltage

1.0

OHmax

0.45

OHnom

3)4)

Input leakage current (Port 5)

OZ1

±200

0 V <

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Input leakage current (all other)

OZ2

±500

0.45 V <

RSTIN inactive current

RSTH

-10

µA

IH1

RSTIN active current

RSTL

-100

µA

RD/WR inact. current

RWH

-40

µA

OUT

= 2.4 V

RD/WR active current

RWL

-500

µA

OUT

OLmax

ALE inactive current

ALEL

µA

OUT

OLmax

ALE active current

ALEH

500

µA

OUT

= 2.4 V

Port 4 inactive current

P4H

-40

µA

OUT

= 2.4 V

Port 4 active current

P4L

-500

µA

OUT

OL1max

PORT0 configuration current

10)

P0H

-10

µA

IHmin

P0L

-100

µA

ILmax

XTAL1 input current

±20

µA

0 V <

Pin capacitance

11)

(digital inputs/outputs)

= 1 MHz

= 25

°C

Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications also refer to the specification of the overload current

For pin RSTIN this specification is only valid in bidirectional reset mode.

The maximum deliverable output current of a port driver depends on the selected output driver mode, see

Table 10

Current Limits for Port Output Drivers

. The limit for pin groups must be respected.

As a rule, with decreasing output current the output levels approach the respective supply level (

). However, only the levels for nominal output currents are guaranteed.

This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.

These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 k

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is valid during Reset and during Adapt-mode. The Port 4 current values are only valid for
pins P4.3-0, which can act as CS outputs.

10)

This specification is valid during Reset if required for configuration, and during Adapt-mode.

11)

Not 100% tested, guaranteed by design and characterization.

DC Characteristics (cont'd)
(Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

max.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Table 10

Current Limits for Port Output Drivers

Port Output Driver
Mode

Maximum Output Current
(

OLmax

, -

OHmax

)

Nominal Output Current
(

OLnom

, -

OHnom

)

Strong driver

10 mA

2.5 mA

Medium driver

4.0 mA

1.0 mA

Weak driver

0.5 mA

0.1 mA

An output current above |

OXnom

| may be drawn from up to three pins at the same time.

For any group of 16 neighboring port output pins the total output current in each direction (

and

)

must remain below 50 mA.

The current ROM-version of the C164CI (step Ax) is equipped with port drivers, which provide reduced driving
capability and reduced control. Please refer to the actual errata sheet for details.

Power Consumption C164CI (ROM)
(Operating Conditions apply)

Parameter

Sym-
bol

Limit Values

Unit Test

Conditions

min.

max.

Power supply current (active)
with all peripherals active

1 +
2.5

CPU

RSTIN =

CPU

in [MHz]

The supply current is a function of the operating frequency. This dependency is illustrated in

Figure 9

These parameters are tested at

DDmax

and maximum CPU clock with all outputs disconnected and all inputs

Idle mode supply current
with all peripherals active

IDX

1 +
1.1

CPU

RSTIN =

IH1

CPU

in [MHz]

Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32

IDO

This parameter is determined mainly by the current consumed by the oscillator (see

Figure 8

). This current,

however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical
circuitry and may change in case of a not optimized external oscillator circuitry.

500 +
50

OSC

µA

RSTIN =

IH1

OSC

in [MHz]

Sleep and Power-down mode
supply current with RTC running

PDR

200 +
25

OSC

µA

DDmax

OSC

in [MHz]

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at

- 0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

Sleep and Power-down mode
supply current with RTC disabled

PDO

µA

DDmax

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Power Consumption C164CI (OTP)
(Operating Conditions apply)

Parameter

Sym-
bol

Limit Values

Unit Test

Conditions

min.

max.

Power supply current (active)
with all peripherals active

10 +
3.5

CPU

RSTIN =

CPU

in [MHz]

Idle mode supply current
with all peripherals active

IDX

5 +
1.25

CPU

RSTIN =

IH1

CPU

in [MHz]

Idle mode supply current
with all peripherals deactivated,
PLL off, SDD factor = 32

IDO

500 +
50

OSC

µA

RSTIN =

IH1

OSC

in [MHz]

Sleep and Power-down mode
supply current with RTC running

PDR

200 +
25

OSC

µA

DDmax

OSC

in [MHz]

Sleep and Power-down mode
supply current with RTC disabled

PDO

µA

DDmax

The supply current is a function of the operating frequency. This dependency is illustrated in

Figure 10

These parameters are tested at

DDmax

and maximum CPU clock with all outputs disconnected and all inputs

This parameter is determined mainly by the current consumed by the oscillator (see

Figure 8

). This current,

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at

- 0.1 V to

REF

= 0 V, all outputs (including pins configured as outputs) disconnected.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics
Definition of Internal Timing

The internal operation of the C164CI is controlled by the internal CPU clock

CPU

. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.

The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called "TCL" (see

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock signal

CPU

can be generated from the oscillator clock signal

OSC

via

different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate

CPU

. This influence must

be regarded when calculating the timings for the C164CI.

Note: The example for PLL operation shown in

Figure 11

refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

MCT04338

OSC

CPU

Phase Locked Loop Operation

TCL

OSC

CPU

Direct Clock Drive

OSC

CPU

Prescaler Operation

TCL

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.

Table 11

associates the combinations of these three bits with the respective clock

generation mode.

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001

) the CPU clock is derived from

the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of

CPU

is half the frequency of

OSC

and the high and low time of

CPU

(i.e.

the duration of an individual TCL) is defined by the period of the input clock

OSC

The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of

OSC

for any TCL.

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see

Table 11

). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.

CPU

OSC

× F). With every F'th transition of

OSC

the PLL circuit synchronizes the CPU

clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.

Table 11

C164CI Clock Generation Modes

CLKCFG

(RP0H.7-5)

Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.

CPU Frequency

CPU

OSC

× F

External Clock
Input Range

The external clock input range refers to a CPU clock range of 10 ... 25 MHz.

Notes

1 1 1

OSC

× 4

2.5 to 6.25 MHz

Default configuration

1 1 0

OSC

× 3

3.33 to 8.33 MHz

1 0 1

OSC

× 2

5 to 12.5 MHz

1 0 0

OSC

× 5

2 to 5 MHz

0 1 1

OSC

× 1

1 to 25 MHz

Direct drive

The maximum frequency depends on the duty cycle of the external clock signal.

0 1 0

OSC

× 1.5

6.66 to 16.66 MHz

0 0 1

OSC

/ 2

2 to 50 MHz

CPU clock via prescaler

0 0 0

OSC

× 2.5

4 to 10 MHz

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Due to this adaptation to the input clock the frequency of

CPU

is constantly adjusted so

it is locked to

OSC

. The slight variation causes a jitter of

CPU

which also effects the

duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and

Figure 12

For a period of

× TCL the minimum value is computed using the corresponding

deviation D

(

× TCL)

min

× TCL

NOM

- D

; D

[ns] =

±(13.3 +

× 6.3)/

CPU

[MHz],

where

= number of consecutive TCLs and 1

40.

So for a period of 3 TCLs @ 25 MHz (i.e.

= 3): D

= (13.3 +

× 6.3)/25 = 1.288 ns,

and (3TCL)

min

= 3TCL

NOM

- 1.288 ns = 58.7 ns (@

CPU

= 25 MHz).

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see

Figure 12

Approximated Maximum Accumulated PLL Jitter

MCD04455

Max. jitter

±1

±10

±20

±30

±26.5

This approximated formula is valid for
1

40 and 10 MHz f

CPU

25 MHz.

10 MHz

16 MHz

20 MHz

25 MHz

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Direct Drive

When direct drive is configured (CLKCFG = 011

) the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of

CPU

directly follows the frequency of

OSC

so the high and low time of

CPU

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

OSC

The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:

TCL

min

= 1/

OSC

× DC

min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of

OSC

is compensated

so the duration of 2TCL is always 1/

OSC

. The minimum value TCL

min

therefore has to

be used only once for timings that require an odd number of TCLs (1, 3, ...). Timings that
require an even number of TCLs (2, 4, ...) may use the formula 2TCL = 1/

OSC

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics
External Clock Drive XTAL1
(Operating Conditions apply)

Figure 13

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).

Table 12

External Clock Drive Characteristics

Parameter

Symbol

Direct Drive

1:1

Prescaler

2:1

PLL

1:N

Unit

min.

max.

min.

max.

min.

max.

Oscillator period

OSC

SR 40

The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.

500

High time

The clock input signal must reach the defined levels

IL2

and

IH2

SR 20

The minimum high and low time refers to a duty cycle of 50%. The maximum operating freqency (

CPU

) in direct

drive mode depends on the duty cycle of the clock input signal.

Low time

SR 20

Rise time

Fall time

MCT02534

IH2

0.5

OSC

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

A/D Converter Characteristics
(Operating Conditions apply)

Table 13

A/D Converter Characteristics

Parameter

Symbol

Limit Values

Unit Test

Conditions

min.

max.

Analog reference supply

AREF

SR 4.0

+ 0.1 V

TUE is tested at

AREF

= 5.0 V,

AGND

= 0 V,

= 4.9 V. It is guaranteed by design for all other voltages

within the defined voltage range.
If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.

AREF

= +0.2 V) the maximum TUE is increased to

±3 LSB. This range is not 100% tested.

The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see

specification) does not exceed 10 mA.
During the reset calibration sequence the maximum TUE may be

±4 LSB.

Analog reference ground

AGND

- 0.1

+ 0.2 V

Analog input voltage range

AIN

AGND

AREF

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in

these cases will be X000

or X3FF

, respectively.

Basic clock frequency

0.5

6.25

MHz

The limit values for

must not be exceeded when selecting the CPU frequency and the ADCTC setting.

Conversion time

+ 2

CPU

= 1 /

CPU

This parameter includes the sample time

, the time for determining the digital result and the time to load the

result register with the conversion result.
Values for the basic clock

depend on programming and can be taken from

Table 14

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

Calibration time after reset

CAL

3328

During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.

Total unadjusted error

TUE

±2

LSB

Internal resistance of
reference voltage source

AREF

/ 60

- 0.25

in [ns]

6)7)

During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.

Not 100% tested, guaranteed by design and characterization.

Internal resistance of analog
source

ASRC

/ 450

- 0.25

in [ns]

7)8)

ADC input capacitance

AIN

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Sample time and conversion time of the C164CI's A/D Converter are programmable.

Table 14

should be used to calculate the above timings.

The limit values for

must not be exceeded when selecting ADCTC.

Converter Timing Example:

Assumptions:

CPU

= 25 MHz (i.e.

CPU

= 40 ns), ADCTC = `00', ADSTC = `00'.

Basic clock

CPU

/4 = 6.25 MHz, i.e.

= 160 ns.

Sample time

× 8 = 1280 ns.

Conversion time

+ 40

+ 2

CPU

= (1280 + 6400 + 80) ns = 7.8

µs.

During the sample time the input capacitance

AIN

can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within

After the end of the sample time

, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time

depend on programming and can be taken from

Table 14

A/D Converter Computation Table

ADCON.15|14
(ADCTC)

A/D Converter
Basic Clock

ADCON.13|12
(ADSTC)

Sample time

CPU

/ 4

× 8

CPU

/ 2

× 16

CPU

/ 16

× 32

CPU

/ 8

× 64

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Testing Waveforms

Figure 14

Input Output Waveforms

Figure 15

Float Waveforms

MCA04414

2.4 V

0.45 V

1.8 V

0.8 V

1.8 V

0.8 V

Test Points

AC inputs during testing are driven at 2.4 V for a logic '1' and 0.45 V for a logic '0'.
Timing measurements are made at

min for a logic '1' and

max for a logic '0'.

MCA00763

- 0.1 V

+ 0.1 V

- 0.1 V

Reference

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded

Timing

Points

Load

level occurs (

= 20 mA).

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.

Note: Please respect the maximum operating frequency of the respective derivative.

AC Characteristics

Table 15

Memory Cycle Variables

Description

Symbol

Values

ALE Extension

TCL

× <ALECTL>

Memory Cycle Time Waitstates

2TCL

× (15 - <MCTC>)

Memory Tristate Time

2TCL

× (1 - <MTTC>)

Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

TCL - 10
+

Address setup to ALE

4 +

TCL - 16
+

Address hold after ALE

10 +

TCL - 10
+

ALE falling edge to RD,
WR (with RW-delay)

10 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

Address float after RD,
WR (with RW-delay)

Address float after RD,
WR (no RW-delay)

TCL + 6

RD, WR low time
(with RW-delay)

30 +

2TCL - 10
+

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

RD, WR low time
(no RW-delay)

50 +

3TCL - 10
+

RD to valid data in
(with RW-delay)

20 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

40 +

3TCL - 20
+

ALE low to valid data in

40 +

3TCL - 20
+

Address to valid data in

50 + 2

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD

26 +

2TCL - 14
+

Data valid to WR

20 +

2TCL - 20
+

Data hold after WR

26 +

2TCL - 14
+

ALE rising edge after RD,
WR

26 +

2TCL - 14
+

Address hold after RD,
WR

26 +

2TCL - 14
+

ALE falling edge to CS

-4 -

10 -

-4 -

10 -

CS low to Valid Data In

40
+

3TCL - 20
+

+ 2

CS hold after RD, WR

46 +

3TCL - 14
+

ALE fall. edge to RdCS,
WrCS (with RW delay)

16 +

TCL - 4
+

Multiplexed Bus (cont'd)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

ALE fall. edge to RdCS,
WrCS (no RW delay)

-4 +

-4
+

Address float after RdCS,
WrCS (with RW delay)

Address float after RdCS,
WrCS (no RW delay)

TCL

RdCS to Valid Data In
(with RW delay)

16 +

2TCL - 24
+

RdCS to Valid Data In
(no RW delay)

36 +

3TCL - 24
+

RdCS, WrCS Low Time
(with RW delay)

30 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW delay)

50 +

3TCL - 10
+

Data valid to WrCS

26 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS

20 +

2TCL - 20
+

Address hold after
RdCS, WrCS

20 +

2TCL - 20
+

Data hold after WrCS

20 +

2TCL - 20
+

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).

Multiplexed Bus (cont'd)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2

(120 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics

Demultiplexed Bus
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

ALE high time

10 +

TCL - 10
+

Address setup to ALE

4 +

TCL - 16
+

ALE falling edge to RD,
WR (with RW-delay)

10 +

TCL - 10
+

ALE falling edge to RD,
WR (no RW-delay)

-10 +

-10
+

RD, WR low time
(with RW-delay)

30 +

2TCL - 10
+

RD, WR low time
(no RW-delay)

50 +

3TCL - 10
+

RD to valid data in
(with RW-delay)

20 +

2TCL - 20
+

RD to valid data in
(no RW-delay)

40 +

3TCL - 20
+

ALE low to valid data in

40 +

3TCL - 20
+

Address to valid data in

50 +
2

4TCL - 30
+

Data hold after RD
rising edge

Data float after RD rising
edge (with RW-delay

)

26 +
2

2TCL - 14
+

Data float after RD rising
edge (no RW-delay

)

10 +
2

TCL - 10
+

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Data valid to WR

20 +

2TCL - 20
+

Data hold after WR

10 +

TCL - 10
+

ALE rising edge after RD,
WR

-10 +

Address hold after WR

0 +

ALE falling edge to CS

-4 -

10 -

-4 -

10 -

CS low to Valid Data In

40 +

3TCL - 20
+

+ 2

CS hold after RD, WR

6 +

TCL - 14
+

ALE falling edge to RdCS,
WrCS (with RW-delay)

16 +

TCL - 4
+

ALE falling edge to RdCS,
WrCS (no RW-delay)

-4 +

-4
+

RdCS to Valid Data In
(with RW-delay)

16 +

2TCL - 24
+

RdCS to Valid Data In
(no RW-delay)

36 +

3TCL

- 24

RdCS, WrCS Low Time
(with RW-delay)

30 +

2TCL - 10
+

RdCS, WrCS Low Time
(no RW-delay)

50 +

3TCL - 10
+

Data valid to WrCS

26 +

2TCL - 14
+

Data hold after RdCS

Data float after RdCS
(with RW-delay)

20 +

2TCL - 20
+

Demultiplexed Bus (cont'd)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Data float after RdCS
(no RW-delay)

0 +

TCL - 20
+

Address hold after
RdCS, WrCS

-6 +

Data hold after WrCS

6 +

TCL - 14 +

RW-delay and

refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.

These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).

Demultiplexed Bus (cont'd)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2

(80 ns at 25 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

AC Characteristics

Figure 24

CLKOUT Timing

Notes

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.

The next external bus cycle may start here.

CLKOUT
(Operating Conditions apply)

Parameter

Symbol

Max. CPU Clock

= 25 MHz

Variable CPU Clock

1 / 2TCL = 1 to 25 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

2TCL

CLKOUT high time

TCL - 6

CLKOUT low time

TCL - 10

CLKOUT rise time

CLKOUT fall time

CLKOUT rising edge to
ALE falling edge

0 +

10 +

0 +

10 +

CLKOUT

ALE

MUX/Tristate

Running cycle

Command

RD, WR

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

External XRAM Access

If XPER-Share mode is enabled the on-chip XRAM of the C164CI can be accessed
(during hold states) by an external master like an asynchronous SRAM.

Figure 25

External Access to the XRAM

Table 16

XRAM Access Timing (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit

min.

max.

Address setup time before RD/WR falling edge

SR 4

Address hold time after RD/WR rising edge

SR 0

Data turn on delay after RD falling edge

CC 2

Data output valid delay after address latched

Data turn off delay after RD rising edge

CC 0

Write data setup time before WR rising edge

i
t
e

SR 10

Write data hold time after WR rising edge

SR 1

WR pulse width

SR 18

WR signal recovery time

Read Data

MCT04423

(RD, WR)

Write Data

Command

Address

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAF-C164CI-LM

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAF-C164CI-LM