C 1 6 5
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r
N e v e r s t o p t h i n k i n g .
M i c r o c o n t r o l l e r s
D a t a S h e e t , V 2 . 0 , D e c . 2 0 0 0
Edition 2000-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 Mnchen, Germany
Infineon Technologies AG 2000.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices please contact your nearest
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Due to technical requirements components may contain dangerous substances. For information on the types in
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M i c r o c o n t r o l l e r s
D a t a S h e e t , V 2 . 0 , D e c . 2 0 0 0
N e v e r s t o p t h i n k i n g .
C 1 6 5
1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l e r
C165
Revision History:
2000-12
V2.0
Previous Version:
1998-12
Update 0.5
technology
01.96
3 Volt Addendum
07.95
25 MHz Addendum
09.94
Data Sheet
Page
Subjects (major changes since last revision)
All
Converted to Infineon layout
2
ROM derivatives removed, 25-MHz derivatives and 3 V derivatives
included
6
ff
Pin numbers for TQFP added
14
Address window arbitration and master/slave mode introduced
32
New standard layout for section "Absolute Maximum Ratings"
33
Section "Operating Conditions" added
34
f
Parameter "RSTIN pullup" replaced by "RSTIN current"
36
f
DC Characteristics for reduced supply voltage added
38
f
Separate specification for power consumption with greatly improved values
40
ff
Description of clock generation improved
45
,
55
,
65
Timing adapted to 25 MHz
48
,
58
,
66
Timing for reduced supply voltage added
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Data Sheet
1
V2.0, 2000-12
C165
16-Bit Single-Chip Microcontroller
C166 Family
C165
High Performance 16-bit CPU with 4-Stage Pipeline
80 ns Instruction Cycle Time at 25 MHz CPU Clock
400 ns Multiplication (16
16 bit), 800 ns Division (32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area
16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
Clock Generation via prescaler or via direct clock input
On-Chip Memory Modules
2 KBytes On-Chip Internal RAM (IRAM)
On-Chip Peripheral Modules
Two Multi-Functional General Purpose Timer Units with 5 Timers
Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
Up to 16 MBytes External Address Space for Code and Data
Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
Five Programmable Chip-Select Signals
Hold- and Hold-Acknowledge Bus Arbitration Support
Idle and Power Down Modes
Programmable Watchdog Timer
Up to 77 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Power Supply: the C165 can operate from a 5 V or a 3 V power supply
Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
On-Chip Bootstrap Loader
100-Pin MQFP Package (0.65 mm pitch)
100-Pin TQFP Package (0.5 mm pitch)
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