Электронный компонент: SAFC165UTAH-LF

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C 1 6 5 U T A H

E m b e d d e d C 1 6 6 w i t h U S B ,
I O M - 2 a n d H D L C S u p p o r t

V e r s i o n 1 . 3

D a t a S h e e t , D S 2 , F e b . 2 0 0 1

W i r e d
C o m m u n i c a t i o n s

N e v e r s t o p t h i n k i n g .

Edition 2001-02-23

Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 M�nchen, Germany

�

Infineon Technologies AG 2001.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

W i r e d
C o m m u n i c a t i o n s

C 1 6 5 U T A H

E m b e d d e d C 1 6 6 w i t h U S B ,
I O M - 2 a n d H D L C S u p p o r t

V e r s i o n 1 . 3

D a t a S h e e t , D S 2 , F e b . 2 0 0 1

N e v e r s t o p t h i n k i n g .

For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com

C165UTAH

Revision History:

2001-02-23

DS 2

Previous Version:

Data Sheet, 10.00, DS1

1)

1)

All previous distributed versions are preliminary. They have been replaced by this version.

Page

Subjects (major changes since last revision)

91

Correction of the PEC Control Register:
The correct channel numbers are PEC channels 0 and 2.
The name of the corresponding register is PECXC2 and not PECXC1.

330

Correction: AS2 in was removed

529

Correction of the Parameter t14.
Improved formatting (text, figures, tables)

C165UTAH

Page

Data Sheet

2001-02-23

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.3

Pinning Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.4

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.4.1

ISDN NT and PBX Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1

C165UTAH Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2

C165UTAH Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . 19

3

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1

Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2

On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3

Clock Generation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4

On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5

Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1

Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2

External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.3

Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5

Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1

Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2

Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3

Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4

CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5

PEC - Extension of Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6

DMA - External PEC (EPEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.1

EPEC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.2

EPEC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3

EPEC Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.4

EPEC Transfer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.5

Implementation of EPEC Interrupt Generation Unit . . . . . . . . . . . . . . . . . 101

7

Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7.1

Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.2

Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.3

Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

7.4

Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . 115

7.5

Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . . 118

7.6

Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.7

PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Document Outline

• 1 Overview
  • 1.1 Key Features
  • 1.2 Logic Symbol
  • 1.3 Pinning Diagram
  • 1.4 Typical Applications
    • 1.4.1 ISDN NT and PBX Applications
• 2 Pin Descriptions
  • 2.1 C165UTAH Pin Diagram
  • 2.2 C165UTAH Pin Definitions and Functions
• 3 Architectural Overview
  • 3.1 Basic CPU Concepts and Optimizations
  • 3.2 On-Chip System Resources
  • 3.3 Clock Generation Concept
  • 3.4 On-Chip Peripheral Blocks
  • 3.5 Protected Bits
• 4 Memory Organization
  • 4.1 Internal RAM and SFR Area
  • 4.2 External Memory Space
  • 4.3 Crossing Memory Boundaries
• 5 Central Processor Unit
  • 5.1 Instruction Pipelining
  • 5.2 Bit-Handling and Bit-Protection
  • 5.3 Instruction State Times
  • 5.4 CPU Special Function Registers
  • 5.5 PEC - Extension of Functionality
• 6 DMA - External PEC (EPEC)
  • 6.1 EPEC Functionality
  • 6.2 EPEC Implementation
  • 6.3 EPEC Register Description
  • 6.4 EPEC Transfer Example
  • 6.5 Implementation of EPEC Interrupt Generation Unit
• 7 Interrupt and Trap Functions
  • 7.1 Interrupt System Structure
  • 7.2 Interrupt Control Registers
  • 7.3 Operation of the PEC Channels
  • 7.4 Prioritization of Interrupt and PEC Service Requests
  • 7.5 Saving the Status during Interrupt Service
  • 7.6 Interrupt Response Times
  • 7.7 PEC Response Times
  • 7.8 External Interrupts
    • 7.8.1 Fast External Interrupts
    • 7.8.2 External Interrupt Source Control
    • 7.8.3 Interrupt Subnode Control
    • 7.8.4 The Interrupt Control Register
  • 7.9 Trap Functions
• 8 Parallel Ports
  • 8.1 PORT0
    • 8.1.1 Alternate Functions of PORT0
  • 8.2 PORT1
    • 8.2.1 Alternate Functions of PORT1
  • 8.3 PORT2
    • 8.3.1 Alternate Functions of PORT2
  • 8.4 PORT3
    • 8.4.1 Alternate Functions of PORT3
  • 8.5 PORT4
    • 8.5.1 Alternate Functions of PORT4
  • 8.6 PORT6
    • 8.6.1 Alternate Functions of PORT6
  • 8.7 PORT7
• 9 Dedicated Pins
• 10 External Bus Interface
  • 10.1 External Bus Modes
  • 10.2 Programmable Bus Characteristics
  • 10.3 READY Controlled Bus Cycles
  • 10.4 Controlling the External Bus Controller
  • 10.5 EBC Idle State
  • 10.6 External Bus Arbitration
  • 10.7 XBUS Interface
  • 10.8 Initialization of the C165UTAH�s X-peripherals
• 11 General Purpose Timer Unit
  • 11.1 Kernel Description
    • 11.1.1 Functional Description of Timer Block 1
      • 11.1.1.1 Core Timer T3
      • 11.1.1.2 Auxiliary Timers T2 and T4
      • 11.1.1.3 Timer Concatenation
    • 11.1.2 Functional Description of Timer Block 2
      • 11.1.2.1 Core Timer T6
      • 11.1.2.2 Auxiliary Timer T5
      • 11.1.2.3 Timer Concatenation
    • 11.1.3 GPT Register Set
• 12 Asynchronous/Synchr. Serial Interface
  • 12.1 Functional Description
    • 12.1.1 Features
    • 12.1.2 Overview
    • 12.1.3 Register Description
    • 12.1.4 General Operation
    • 12.1.5 Asynchronous Operation
      • 12.1.5.1 Asynchronous Data Frames
      • 12.1.5.2 Asynchronous Transmission
      • 12.1.5.3 Asynchronous Reception
      • 12.1.5.4 IrDA Mode
      • 12.1.5.5 RXD/TXD Data Path Selection in Asynchronous Modes
    • 12.1.6 Synchronous Operation
      • 12.1.6.1 Synchronous Transmission
      • 12.1.6.2 Synchronous Reception
      • 12.1.6.3 Synchronous Timing
    • 12.1.7 Baudrate Generation
      • 12.1.7.1 Baudrates in Asynchronous Mode
      • 12.1.7.2 Baudrates in Synchronous Mode
    • 12.1.8 Autobaud Detection
      • 12.1.8.1 General Operation
      • 12.1.8.2 Serial Frames for Autobaud Detection
      • 12.1.8.3 Baudrate Selection and Calculation
      • 12.1.8.4 Overwriting Registers on Successful Autobaud Detection
    • 12.1.9 Hardware Error Detection Capabilities
    • 12.1.10 Interrupts
• 13 Real Time Clock (RTC)
  • 13.1 Introduction
    • 13.1.1 Features
    • 13.1.2 Overview
  • 13.2 Function Description
    • 13.2.1 RTC Block Diagram
    • 13.2.2 RTC Control
    • 13.2.3 System Clock Operation
    • 13.2.4 Cyclic Interrupt Generation
    • 13.2.5 Alarm Interrupt Generation
    • 13.2.6 48-bit Timer Operation
    • 13.2.7 Defining the RTC Time Base
    • 13.2.8 Increased RTC Accuracy through Software Correction
    • 13.2.9 Hardware dependend RTC Accuracy
    • 13.2.10 Interrupt Sub Node RTCISNC
    • 13.2.11 RTC Disable Functionality
    • 13.2.12 Register Definition of RTC module
• 14 High-Speed Synchronous Serial Interface
  • 14.1 Full-Duplex Operation
  • 14.2 Half Duplex Operation
  • 14.3 Baud Rate Generation
  • 14.4 Error Detection Mechanisms
  • 14.5 SSC Interrupt Control
• 15 USB Interface Controller
  • 15.1 USB Features
  • 15.2 USB Protocol
  • 15.3 USB Endpoints
  • 15.4 USB Interface Controller (USBD) Architecture
  • 15.5 Endpoint Info Block
  • 15.6 USB Microprocessor Registers
  • 15.7 Programmers Guidlines: Using USB and EPEC
    • 15.7.1 Writing the configuration-value
    • 15.7.2 In-Transfer (Transmit)
    • 15.7.3 Out-Transfer (Receive)
    • 15.7.4 Reading out Setup-Packets
    • 15.7.5 Special case: Setup-Transfer
    • 15.7.6 Setting of configuration and alternate settings of interfaces
    • 15.7.7 Stalling Endpoints
    • 15.7.8 Start of Frame
    • 15.7.9 Suspend and Suspendoff
    • 15.7.10 Device disconnecting
• 16 IOM-2 Interface Controller
  • 16.1 IOM-2 and PCM Frame Structure
    • 16.1.1 Definitions
      • 16.1.1.1 Frame Structure
      • 16.1.1.2 HDLC Channels on the IOM-2: B1, B2, D1, D2
    • 16.1.2 PCM Mode
    • 16.1.3 Terminal Mode
    • 16.1.4 Linecard Mode
  • 16.2 IOM-2 Handler
  • 16.3 IOM-2 Monitor Handler
    • 16.3.1 Handshake Procedure
    • 16.3.2 Abort Procedure
    • 16.3.3 MONITOR Interrupt Logic
  • 16.4 C/I Channel Handler
    • 16.4.1 C/I0 - Command/Indication 0
    • 16.4.2 C/I1 - Command/Indication 1
    • 16.4.3 CIC Interrupt Logic
    • 16.4.4 D-Channel Access Control
      • 16.4.4.1 TIC Bus D-Channel Access Control for HDLC-2 Controller
  • 16.5 Controller Data Access Handler
    • 16.5.1 Description
    • 16.5.2 Looping and Shifting Data
    • 16.5.3 Monitoring Data
    • 16.5.4 Synchronous Transfer
  • 16.6 Bus Activation / Deactivation (Power Down)
    • 16.6.1 Deactivation Request, Downstream (C165UTAH) to Upstream
    • 16.6.2 Deactivation, Upstream to Downstream (C165UTAH)
    • 16.6.3 Activation Request, Downstream (C165UTAH) to Upstream
    • 16.6.4 Activation, Upstream to Downstream (C165UTAH)
  • 16.7 HDLC Controller
    • 16.7.1 Message Transfer Modes
      • 16.7.1.1 Non-Auto Mode (MDS2-0 = �01x�)
      • 16.7.1.2 Transparent Mode 0 (MDS2-0 = �110�).
      • 16.7.1.3 Transparent Mode 1 (MDS2-0 = �111�).
      • 16.7.1.4 Transparent Mode 2 (MDS2-0 = �101�).
      • 16.7.1.5 Extended Transparent Mode (MDS2-0 = �100�).
    • 16.7.2 Data Reception
      • 16.7.2.1 General Description
      • 16.7.2.2 Possible Error Conditions during Reception of Frames
      • 16.7.2.3 Receive Frame Structure
    • 16.7.3 Data Transmission
      • 16.7.3.1 General Description
      • 16.7.3.2 Possible Error Conditions during Transmission of Frames
      • 16.7.3.3 Transmit Frame Structure
    • 16.7.4 General Access to IOM-2 Channels
    • 16.7.5 Extended Transparent Mode
      • 16.7.5.1 Transmitter
      • 16.7.5.2 Receiver
    • 16.7.6 HDLC Controller Interrupts
      • 16.7.6.1 General HDLC Interrupt
      • 16.7.6.2 HDLC Transmit/Receive FIFO Interrupt
      • 16.7.6.3 Interrupt Generation
  • 16.8 IOM-2/HDLC Controller Register Set
    • 16.8.1 Register Description Format
    • 16.8.2 Register Table ordered by Address
    • 16.8.3 Detailed Register Description ordered by Address
    • 16.8.4 HDLC-Channel Registers
• 17 Watchdog Timer (WDT)
  • 17.1 Operation of the Watchdog Timer
• 18 Bootstrap Loader
• 19 System Reset
  • 19.1 System Startup Configuration
• 20 PowerReductionModes
  • 20.1 Idle Mode
  • 20.2 Power Down Mode
  • 20.3 Status of Output Pins during Idle and Power Down Mode
  • 20.4 Extended Power Management
    • 20.4.1 Sleep Mode
• 21 System Control Unit (CSCU)
  • 21.1 Introduction
  • 21.2 Operational Overview
    • 21.2.1 Overview of CSCU submodules
  • 21.3 XBUS Peripheral Configuration Block
  • 21.4 System Control Block
    • 21.4.1 Register Write Protection
    • 21.4.2 Clock Output Frequency Control
  • 21.5 Peripheral Management Module
  • 21.6 Identification Registers
    • 21.6.1 Introduction
    • 21.6.2 ID Register Description
• 22 System Programming
  • 22.1 Stack Operations
  • 22.2 Register Banking
  • 22.3 Procedure Call Entry and Exit
  • 22.4 Table Searching
  • 22.5 Peripheral Control and Interface
  • 22.6 Floating Point Support
  • 22.7 Trap/Interrupt Entry and Exit
  • 22.8 Unseparable Instruction Sequences
  • 22.9 Overriding the DPP Addressing Mechanism
  • 22.10 Pits, Traps and Mines
• 23 Register Set
  • 23.1 Register Description Format
  • 23.2 CPU General Purpose Registers (GPRs)
  • 23.3 Special Function Registers ordered by Address
  • 23.4 Special Function Registers ordered by Name
  • 23.5 Special Notes
• 24 Instruction Set Summary
• 25 AC/DC Characteristics
  • 25.1 Absolute Maximum Ratings
  • 25.2 Recommended Operating Conditions
  • 25.3 DC Characteristics
  • 25.4 USB Full-speed (12 Mbit/s) Driver Characteristics
  • 25.5 Failsafe operation
  • 25.6 Testing Waveforms
  • 25.7 AC Characteristics
    • 25.7.1 Definition of Internal Timing
    • 25.7.2 System Reset
    • 25.7.3 External Clock Drive XTAL1
    • 25.7.4 IOM-2 Interface Timing
    • 25.7.5 JTAG Interface Timing
  • 25.8 Asynchronous Bus Timing
    • 25.8.1 Memory Cycle Variables
      • 25.8.1.1 AC Characteristics, Multiplexed Bus
      • 25.8.1.2 AC Characteristics, Demultiplexed Bus
      • 25.8.1.3 AC Characteristics, CLKOUT and READY
• 26 Package Outline