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Edition 2004-11
Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Infineon Technologies AG 2004.

Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information
For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (

www.infineon.com

Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

XC161-32

Derivatives

Table of Contents

Data Sheet

V1.0, 2004-11

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2

External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4

Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.5

On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.6

Capture/Compare Units (CAPCOM1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.7

General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.8

Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.9

A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.10

Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 42

3.11

High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 43

3.12

TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.13

IIC Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.14

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.15

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.16

Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.17

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.18

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.1

General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2

DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.3

Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4

AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.1

Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4.2

External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.4.3

Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.4.4

External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table of Contents

XC161

16-Bit Single-Chip Microcontroller with C166SV2 Core
XC166 Family

Data Sheet

V1.0, 2004-11

Summary of Features

High Performance 16-bit CPU with 5-Stage Pipeline
25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
1-Cycle Multiplication (16

× 16 bit), Background Division (32 / 16 bit) in 21 Cycles

1-Cycle Multiply-and-Accumulate (MAC) Instructions
Enhanced Boolean Bit Manipulation Facilities
Zero-Cycle Jump Execution
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Fast Context Switching Support with Two Additional Local Register Banks
16 Mbytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)

16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns

8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space

Clock Generation via on-chip PLL (factors 1:0.15 ... 1:10), or
via Prescaler (factors 1:1 ... 60:1)

On-Chip Memory Modules
2 Kbytes On-Chip Dual-Port RAM (DPRAM)
4 Kbytes On-Chip Data SRAM (DSRAM)
6 Kbytes On-Chip Program/Data SRAM (PSRAM)
256 Kbytes On-Chip Program Memory (Flash Memory)

On-Chip Peripheral Modules
12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and

Conversion Time (down to 2.55

µs or 2.15 µs)

Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
Multi-Functional General Purpose Timer Unit with 5 Timers
Two Synchronous/Asynchronous Serial Channels (USARTs)
Two High-Speed-Synchronous Serial Channels
On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects

(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality

IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
On-Chip Real Time Clock, Driven by Dedicated Oscillator

Idle, Sleep, and Power Down Modes with Flexible Power Management

Programmable Watchdog Timer and Oscillator Watchdog

XC161-32

Derivatives

Summary of Features

Data Sheet

V1.0, 2004-11

Up to 12 Mbytes External Address Space for Code and Data
Programmable External Bus Characteristics for Different Address Ranges
Multiplexed or Demultiplexed External Address/Data Buses
Selectable Address Bus Width
16-Bit or 8-Bit Data Bus Width
Five Programmable Chip-Select Signals
Hold- and Hold-Acknowledge Bus Arbitration Support

Up to 99 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis

On-Chip Bootstrap Loader

Supported by a Large Range of Development Tools like C-Compilers, Macro-
Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators,
Logic Analyzer Disassemblers, Programming Boards

On-Chip Debug Support via JTAG Interface

144-Pin TQFP Package, 0.5 mm (19.7 mil) pitch

Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
·

the derivative itself, i.e. its function set, the temperature range, and the supply voltage

the package and the type of delivery.

For the available ordering codes for the XC161 please refer to the "Product Catalog
Microcontrollers", which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

This document describes several derivatives of the XC161 group.

Table 1

enumerates

these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term XC161 throughout this document.

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

General Device Information

2.1

Introduction

The XC161 derivatives are high-performance members of the Infineon XC166 Family of
full featured single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 40 million instructions per second)
with high peripheral functionality and enhanced IO-capabilities. They also provide clock
generation via PLL and various on-chip memory modules such as program Flash,
program RAM, and data RAM.

Figure 1

Logic Symbol

MCA05554

XC161

XTAL1
XTAL2
XTAL3
XTAL4
NMI
RSTIN
RSTOUT
EA
READY
ALE
RD
WR/WRL
Port 5
12 bit

Port 20
6 bit

PORT0
16 bit

PORT1
16 bit

Port 2
8 bit

Port 3
15 bit

Port 4
8 bit

Port 6
8 bit

Port 7
4 bit

Port 9
6 bit

AGND

AREF

DDI/P

SSI/P

JTAG

5 bit

TRST

Debug

2 bit

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

2.2

Pin Configuration and Definition

The pins of the XC161 are described in detail in

Table 2

, including all their alternate

functions.

Figure 2

summarizes all pins in a condensed way, showing their location on

the 4 sides of the package. E*) and C*) mark pins to be used as alternate external
interrupt inputs, C*) marks pins that can have CAN interface lines assigned to them.

Figure 2

Pin Configuration (top view)

MCP05390

TDO

TMS

P3.12/BHE/WRH/E*)

P3.13/SCLK0/E*)

P3.15/CLKOUT/FO

DDI

P5.5/AN5

P5.4/AN4

P5.3/AN3

P5.2/AN2

P5.1/AN1

P5.0/AN0

P9.5/SCL2/CC21IO

P9.4/SDA2/CC20IO

P9.3/SCL1/CC19IO/C*)

P9.2/SDA1/CC18IO/C*)

P9.1/SCL0/CC17IO/C*)

P9.0/SDA0/CC16IO/C*)

P7.7/CC31IO/C*)

P7.6/CC30IO/C*)

P7.5/CC29IO/C*)

P7.4/CC28IO/C*)

P6.7/BREQ/CC7IO

P6.6/HLDA/CC6IO

P6.5/HOLD/CC5IO

P6.4/CS4/CC4IO

P6.3/CS3/CC3IO

P6.2/CS2/CC2IO

P6.1/CS1/CC1IO

P6.0/CS0/CC0IO

NMI

P20.12/RSTOUT

N.C.

DDP

SSP

DDP

SSP

DDP

SSP

P4.0/A16

SSI

P4.1/A17

P4.2/A18

P4.3/A19

P4.4/A20/C*)

P4.5/A21/C*)

P4.6/A22/C*)

P4.7/A23/C*)

DDP

SSP

P20.0/RD

P20.1/WR/WRL

P20.2/READY

P20.4/ALE

P20.5/EA

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

DDP

SSP

P0H.0/AD8

P0H.1/AD9

N.C.

T
I
N

L
4

L
3

L
1

L
2

1
H.

/
A

1
5/

CC27

I
O

1
H.

/
A

1
4/

CC26

I
O

1
H.

/
A

1
3/

CC25

I
O

1
H.

/
A

1
2/

CC24

I
O

1
H

.
3

/
A1

1
/
SC

L
K

1
/
E
*
)

.
2

/
A

1
0
/
MT

1
H.

/
A

9
/
M

T
1

1
H

.
0

/
A8

/
C

2
3
I
O

/
E*

)

1
L.

7
/
C

2
I
O

1
L.

.
7

/
A

1
5

.
6

/
A

1
4

.
5

/
A

1
3

.
4

/
A

1
2

.
3

/
A

1
1

.
2

/
A

1
0

2
.
15/

CC15I

/
E

X
7

I
N/

T
7

I
N

5
.6

5
.7

P
5

2
/
A

1
2
/
T6

P
5

3
/
A

1
3
/
T5

5
.
14/

/
T
4E

5
.
15/

/
T
2E

UD V

2
.8

8
IO

X
0

I
N

2
.9

9
IO

X
1

I
N

2
.
1
0
/
CC10I

/
E

X
2

I
N

2
.
1
1
/
CC11I

/
E

X
3

I
N

2
.
1
2
/
CC12I

/
E

X
4

I
N

2
.
1
3
/
CC13I

/
E

X
5

I
N

2
.
1
4
/
CC14I

/
E

X
6

I
N

DDP

3
.0

0
I
N

/
T

x
D

1
/E

*
)

3
.1

6
O

/
R

x
D

1
/
E

*
)

.
2
/
C

I
N

3
.3

3
O

3
.4

3
E

.
5
/
T
4

I
N

.
6
/
T
3

I
N

.
7
/
T
2

I
N

.
8
/
M

T
0

.
9
/
M

T
S

.
1
0

/
T

x
D

0
/
E

*
)

.
1
1
/
R

x
D

0
/
E

*
)

XC161

108
107
106
105

104
103
102
101
100

99
98
97
96
95
94
93
92
91
90

89
88
87
86
85
84
83
82
81
80
79
78
77
76
75

74
73

48 49

63 64

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

Table 2

Pin Definitions and Functions

Sym-
bol

Pin
Num.

Input
Outp.

Function

P20.12 3

For details, please refer to the description of

P20

NMI

Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC161 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
I/O
O/I

I/O
O
I/O

Port 6 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 6 is selectable (standard
or special).
The Port 6 pins also serve for alternate functions:
CS0

Chip Select 0 Output,

CC0IO

CAPCOM1: CC0 Capture Inp./Compare Output

CS1

Chip Select 1 Output,

CC1IO

CAPCOM1: CC1 Capture Inp./Compare Output

CS2

Chip Select 2 Output,

CC2IO

CAPCOM1: CC2 Capture Inp./Compare Output

CS3

Chip Select 3 Output,

CC3IO

CAPCOM1: CC3 Capture Inp./Compare Output

CS4

Chip Select 4 Output,

CC4IO

CAPCOM1: CC4 Capture Inp./Compare Output

HOLD

External Master Hold Request Input,

CC5IO

CAPCOM1: CC5 Capture Inp./Compare Output

HLDA

Hold Acknowledge Output (master mode) or
Input (slave mode),

CC6IO

CAPCOM1: CC6 Capture Inp./Compare Output

BREQ

Bus Request Output,

CC7IO

CAPCOM1: CC7 Capture Inp./Compare Output

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P7.4

P7.5

P7.6

P7.7

I/O
I
I
I/O
O
I
I/O
I
I
I/O
O
I

Port 7 is a 4-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 7 is selectable (standard
or special).
Port 7 pins provide inputs/outputs for CAPCOM2 and serial
interface lines.

CC28IO

CAPCOM2: CC28 Capture Inp./Compare Outp.,

CAN2_RxD CAN Node 2 Receive Data Input,
EX7IN

Fast External Interrupt 7 Input (alternate pin B)

CC29IO

CAPCOM2: CC29 Capture Inp./Compare Outp.,

CAN2_TxD CAN Node 2 Transmit Data Output,
EX6IN

Fast External Interrupt 6 Input (alternate pin B)

CC30IO

CAPCOM2: CC30 Capture Inp./Compare Outp.,

CAN1_RxD CAN Node 1 Receive Data Input,
EX7IN

Fast External Interrupt 7 Input (alternate pin A)

CC31IO

CAPCOM2: CC31 Capture Inp./Compare Outp.,

CAN1_TxD CAN Node 1 Transmit Data Output,
EX6IN

Fast External Interrupt 6 Input (alternate pin A)

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

I/O
I
I/O
I/O
O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O

Port 9 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 9 is selectable (standard
or special).
The following Port 9 pins also serve for alternate functions:

CC16IO

CAPCOM2: CC16 Capture Inp./Compare Outp.,

CAN2_RxD CAN Node 2 Receive Data Input,
SDA0

IIC Bus Data Line 0

CC17IO

CAPCOM2: CC17 Capture Inp./Compare Outp.,

CAN2_TxD CAN Node 2 Transmit Data Output,
SCL0

IIC Bus Clock Line 0

CC18IO

CAPCOM2: CC18 Capture Inp./Compare Outp.,

CAN1_RxD CAN Node 1 Receive Data Input,
SDA1

IIC Bus Data Line 1

CC19IO

CAPCOM2: CC19 Capture Inp./Compare Outp.,

CAN1_TxD CAN Node 1 Transmit Data Output,
SCL1

IIC Bus Clock Line 1

CC20IO

CAPCOM2: CC20 Capture Inp./Compare Outp.,

SDA2

IIC Bus Data Line 2

CC21IO

CAPCOM2: CC21 Capture Inp./Compare Outp.,

SCL2

IIC Bus Clock Line 2

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.12
P5.13
P5.14
P5.15

29
30
31
32
33
34
39
40
43
44
45
46

I
I
I
I
I
I
I
I
I
I
I
I

Port 5 is a 12-bit input-only port.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as timer inputs:
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN12,

T6IN

GPT2 Timer T6 Count/Gate Input

AN13,

T5IN

GPT2 Timer T5 Count/Gate Input

AN14,

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.

AN15,

T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp.

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I

Port 2 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 2 is selectable (standard
or special).
The following Port 2 pins also serve for alternate functions:
CC8IO

CAPCOM1: CC8 Capture Inp./Compare Output,

EX0IN

Fast External Interrupt 0 Input (default pin)

CC9IO

CAPCOM1: CC9 Capture Inp./Compare Output,

EX1IN

Fast External Interrupt 1 Input (default pin)

CC10IO

CAPCOM1: CC10 Capture Inp./Compare Outp.,

EX2IN

Fast External Interrupt 2 Input (default pin)

CC11IO

CAPCOM1: CC11 Capture Inp./Compare Outp.,

EX3IN

Fast External Interrupt 3 Input (default pin)

CC12IO

CAPCOM1: CC12 Capture Inp./Compare Outp.,

EX4IN

Fast External Interrupt 4 Input (default pin)

CC13IO

CAPCOM1: CC13 Capture Inp./Compare Outp.,

EX5IN

Fast External Interrupt 5 Input (default pin)

CC14IO

CAPCOM1: CC14 Capture Inp./Compare Outp.,

EX6IN

Fast External Interrupt 6 Input (default pin)

CC15IO

CAPCOM1: CC15 Capture Inp./Compare Outp.,

EX7IN

Fast External Interrupt 7 Input (default pin),

T7IN

CAPCOM2: Timer T7 Count Input

TRST

Test-System Reset Input. A high-level at this pin activates
the XC161's debug system.
Note: For normal system operation, pin TRST should be

held low.

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P3.0

P3.1

P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10

P3.11

P3.12

P3.13

P3.15

61
62
63
64
65
66
67
68
69

I
O
I
O
I/O
I
I
O
I
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O

Port 3 is a 15-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
T0IN

CAPCOM1 Timer T0 Count Input,

TxD1

ASC1 Clock/Data Output (Async./Sync),

EX1IN

Fast External Interrupt 1 Input (alternate pin B)

T6OUT

GPT2 Timer T6 Toggle Latch Output,

RxD1

ASC1 Data Input (Async.) or Inp./Outp. (Sync.),

EX1IN

Fast External Interrupt 1 Input (alternate pin A)

CAPIN

GPT2 Register CAPREL Capture Input

T3OUT

GPT1 Timer T3 Toggle Latch Output

T3EUD

GPT1 Timer T3 External Up/Down Control Input

T4IN

GPT1 Timer T4 Count/Gate/Reload/Capture Inp

T3IN

GPT1 Timer T3 Count/Gate Input

T2IN

GPT1 Timer T2 Count/Gate/Reload/Capture Inp

MRST0

SSC0 Master-Receive/Slave-Transmit In/Out.

MTSR0

SSC0 Master-Transmit/Slave-Receive Out/In.

TxD0

ASC0 Clock/Data Output (Async./Sync.),

EX2IN

Fast External Interrupt 2 Input (alternate pin B)

RxD0

ASC0 Data Input (Async.) or Inp./Outp. (Sync.),

EX2IN

Fast External Interrupt 2 Input (alternate pin A)

BHE

External Memory High Byte Enable Signal,

WRH

External Memory High Byte Write Strobe,

EX3IN

Fast External Interrupt 3 Input (alternate pin B)

SCLK0

SSC0 Master Clock Output/Slave Clock Input.,

EX3IN

Fast External Interrupt 3 Input (alternate pin A)

CLKOUT

Master Clock Output,

FOUT

Programmable Frequency Output

TCK

Debug System: JTAG Clock Input

TDI

Debug System: JTAG Data In

TDO

Debug System: JTAG Data Out

TMS

Debug System: JTAG Test Mode Selection

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P4.0
P4.1
P4.2
P4.3
P4.4

P4.5

P4.6

P4.7

80
81
82
83
84

O
O
O
O
O
I
I
O
I
I
O
O
I
O
I
O
I

Port 4 is an 8-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 4 is selectable (standard
or special).
Port 4 can be used to output the segment address lines, the
optional chip select lines, and for serial interface lines:

A16

Least Significant Segment Address Line

A17

Segment Address Line

A18

Segment Address Line

A19

Segment Address Line

A20

Segment Address Line,

CAN2_RxD CAN Node 2 Receive Data Input,
EX5IN

Fast External Interrupt 5 Input (alternate pin B)

A21

Segment Address Line,

CAN1_RxD CAN Node 1 Receive Data Input,
EX4IN

Fast External Interrupt 4 Input (alternate pin B)

A22

Segment Address Line,

CAN1_TxD CAN Node 1 Transmit Data Output,
EX5IN

Fast External Interrupt 5 Input (alternate pin A)

A23

Most Significant Segment Address Line,

CAN1_RxD CAN Node 1 Receive Data Input,
CAN2_TxD CAN Node 2 Transmit Data Output,
EX4IN

Fast External Interrupt 4 Input (alternate pin A)

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

P20

P20.0

P20.1

P20.2

P20.4

P20.5

P20.12

Port 20 is a 6-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD

External Memory Read Strobe, activated for
every external instruction or data read access.

WR/WRL

External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.

READY

READY Input. When the READY function is
enabled, memory cycle time waitstates can be
forced via this pin during an external access.

ALE

Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.

External Access Enable pin.
A low-level at this pin during and after Reset
forces the XC161 to latch the configuration from
PORT0 and pin RD, and to begin instruction
execution out of external memory.
A high-level forces the XC161 to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. "ROMless" versions must
have this pin tied to `0'.

RSTOUT

Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.

Note: Port 20 pins may input configuration values (see EA).

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

PORT0

P0L.0 -
P0L.7,
P0H.0,
P0H.1,
P0H.2 -
P0H.7

95 -
102,
105,
106,
111 -
116

PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
8-bit data bus: P0H = I/O, P0L = D7 - D0
16-bit data bus: P0H = D15 - D8, P0L = D7 - D0
Multiplexed bus modes:
8-bit data bus: P0H = A15 - A8, P0L = AD7 - AD0
16-bit data bus: P0H = AD15 - AD8, P0L = AD7 - AD0
Note: At the end of an external reset (EA = 0) PORT0 also

may input configuration values.

PORT1

P1L.0 -
P1L.6
P1L.7
P1H.0

P1H.1
P1H.2
P1H.3

P1H.4
P1H.5
P1H.6
P1H.7

117 -
123
124
127

128
129
130

131
132
133
134

I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. Each pin can be programmed for input (output
driver in high-impedance state) or output.
PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes (also after switching from a
demultiplexed to a multiplexed bus mode).
The following PORT1 pins also serve for alt. functions:
(A0-6)

Address output only

CC22IO

CAPCOM2: CC22 Capture Inp./Compare Outp.

CC23IO

CAPCOM2: CC23 Capture Inp./Compare Outp.,

EX0IN

Fast External Interrupt 0 Input (alternate pin B)

MRST1

SSC1 Master-Receive/Slave-Transmit In/Outp.

MTSR1

SSC1 Master-Transmit/Slave-Receive Out/Inp.

SCLK1

SSC1 Master Clock Output/Slave Clock Input,

EX0IN

Fast External Interrupt 0 Input (alternate pin A)

CC24IO

CAPCOM2: CC24 Capture Inp./Compare Outp.

CC25IO

CAPCOM2: CC25 Capture Inp./Compare Outp.

CC26IO

CAPCOM2: CC26 Capture Inp./Compare Outp.

CC27IO

CAPCOM2: CC27 Capture Inp./Compare Outp.

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

General Device Information

Data Sheet

V1.0, 2004-11

XTAL2
XTAL1

137
138

O
I

XTAL2:

Output of the main oscillator amplifier circuit

XTAL1:

Input to the main oscillator amplifier and input to
the internal clock generator

To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

XTAL3
XTAL4

140
141

I
O

XTAL3:

Input to the auxiliary (32-kHz) oscillator amplifier

XTAL4:

Output of the auxiliary (32-kHz) oscillator
amplifier circuit

To clock the device from an external source, drive XTAL3,
while leaving XTAL4 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.

RSTIN 142

Reset Input with Schmitt-Trigger characteristics. A low-level
at this pin while the oscillator is running resets the XC161.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the

hardware configuration signals settle.
External circuitry must guarantee low-level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.

BRK
OUT

143

Debug System: Break Out

BRKIN 144

Debug System: Break In

1, 2,
107 -
110

No connection.
It is recommended not to connect these pins to the PCB.

AREF

Reference voltage for the A/D converter.

AGND

Reference ground for the A/D converter.

DDI

48, 78,
135

Digital Core Supply Voltage (On-Chip Modules):
+2.5 V during normal operation and idle mode.
Please refer to the

Operating Conditions

Table 2

Pin Definitions and Functions (cont'd)

Sym-
bol

Pin
Num.

Input
Outp.

Function

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

Functional Description

The architecture of the XC161 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see

Figure 3

This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC161.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC161.

Figure 3

Block Diagram

GPT

C166SV2 - Core

DPRAM

CPU

BRGen BRGen BRGen BRGen

ASC0

USART

ASC1

USART

SSC0

SPI

SSC1

SPI

ADC

8-Bit/

10-Bit
12 Ch

CC1

IIC

BRGen

Twin

CAN

A B

RTC

WDT

Interrupt & PEC

EBC

LXBus Control

External Bus

Control

DSRAM

ProgMem

Flash

256 Kbytes

PSRAM

Osc / PLL

Clock Generator

OCDS

Debug Support

Interrupt Bus

e
ri

p
h
e

l
D

a
t
a

u
s

CC2

P 20 P 9 P 7 Port 6

Port 5

Port 4

Port 3

Port 2

PORT1

PORT0

MCB04323_X132

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.1

Memory Subsystem and Organization

The memory space of the XC161 is configured in a Von Neumann architecture, which
means that all internal and external resources, such as code memory, data memory,
registers and I/O ports, are organized within the same linear address space. This
common memory space includes 16 Mbytes and is arranged as 256 segments of
64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
The entire memory space can be accessed bytewise or wordwise. Portions of the
on-chip DPRAM and the register spaces (E/SFR) have additionally been made directly
bitaddressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
accesses to the program memories, such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
accesses to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected via the high-speed system bus to exchange
data. This is required if operands are read from program memory, code or data is written
to the PSRAM, code is fetched from external memory, or data is read from or written to
external resources, including peripherals on the LXBus (such as TwinCAN). The system
bus allows concurrent two-way communication for maximum transfer performance.
256 Kbytes of on-chip Flash memory store code or constant data. The on-chip Flash
memory is organized as four 8-Kbyte sectors, one 32-Kbyte sector, and three 64-Kbyte
sectors. Each sector can be separately write protected

, erased and programmed (in

blocks of 128 Bytes). The complete Flash area can be read-protected. A password
sequence temporarily unlocks protected areas. The Flash module combines very fast
64-bit one-cycle read accesses with protected and efficient writing algorithms for
programming and erasing. Thus, program execution out of the internal Flash results in
maximum performance. Dynamic error correction provides extremely high read data
security for all read accesses.
Programming typically takes 2 ms per 128-byte block (5 ms max.), erasing a sector
typically takes 200 ms (500 ms max.).
6 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is therefore optimized for code fetches.
4 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user
data. The DSRAM is accessed via the DMU and is therefore optimized for data
accesses.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user
defined variables, for the system stack, general purpose register banks. A register bank

1) Each two 8-Kbyte sectors are combined for write-protection purposes.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7)
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2

× 512 bytes) of the address space are reserved for the Special Function

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see

Table 3

) of external RAM and/or ROM can

be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.

Table 3

XC161 Memory Map

1) Accesses to the shaded areas generate external bus accesses.

Address Area

Start Loc. End Loc.

Area Size

2) The areas marked with "<" are slightly smaller than indicated, see column "Notes".

Notes

Flash register space

FF'F000

FF'FFFF

4 Kbytes

3) Not defined register locations return a trap code.

Reserved (Acc. trap)

F8'0000

FF'EFFF

< 0.5 Mbytes Minus Flash regs

Reserved for PSRAM

E0'1800

F7'FFFF

< 1.5 Mbytes Minus PSRAM

Program SRAM

E0'0000

E0'17FF

6 Kbytes

Maximum

Reserved for pr. mem.

C4'0000

DF'FFFF

< 2 Mbytes

Minus Flash

Program Flash

C0'0000

C3'FFFF

256 Kbytes

Reserved

BF'0000

BF'FFFF

64 Kbytes

External memory area

40'0000

BE'FFFF

< 8 Mbytes

Minus res. seg.

External IO area

4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

20'0800

3F'FFFF

< 2 Mbytes

Minus TwinCAN

TwinCAN registers

20'0000

20'07FF

2 Kbytes

External memory area

01'0000

1F'FFFF

< 2 Mbytes

Minus segment 0

Data RAMs and SFRs

00'8000

00'FFFF

32 Kbytes

Partly used

External memory area

00'0000

00'7FFF

32 Kbytes

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.2

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes

, which

are as follows:
·

16 ... 24-bit Addresses, 16-bit Data, Demultiplexed

16 ... 24-bit Addresses, 16-bit Data, Multiplexed

16 ... 24-bit Addresses, 8-bit Data, Multiplexed

16 ... 24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is
input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both
addresses and data use PORT0 for input/output. The high order address (segment) lines
use Port 4. The number of active segment address lines is selectable, restricting the
external address space to 8 Mbytes ... 64 Kbytes. This is required when interface lines
are assigned to Port 4.
Up to 5 external CS signals (4 windows plus default) can be generated in order to save
external glue logic. External modules can directly be connected to the common
address/data bus and their individual select lines.
Access to very slow memories or modules with varying access times is supported via a
particular `Ready' function. The active level of the control input signal is selectable.
A HOLD/HLDA protocol is available for bus arbitration and allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software. After
enabling, pins P6.7 ... P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the
EBC. In Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin
HLDA is switched to input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface have been made
programmable (via registers TCONCSx/FCONCSx) to allow the user the adaption of a
wide range of different types of memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via registers
ADDRSELx) which control the access to different resources with different bus
characteristics. These address windows are arranged hierarchically where window 4
overrides window 3, and window 2 overrides window 1. All accesses to locations not
covered by these 4 address windows are controlled by TCONCS0/FCONCS0. The
currently active window can generate a chip select signal.
The external bus timing is related to the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.

1) Bus modes are switched dynamically if several address windows with different mode settings are used.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.3

Central Processing Unit (CPU)

The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.

Figure 4

CPU Block Diagram

Based on these hardware provisions, most of the XC161's instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift

D P R A M

C P U

IP IP

R 0

R 1

G P R s

R 1 4

R 1 5

R 0

R 1

G P R s

R 1 4

R 1 5

IFU

Injection/

E xception

H andler

AD U

M A C

m ca 0 4 9 1 7 _ x .v s d

C P U C O N 1

C P U C O N 2

C S P

R e tu rn

S ta c k

F IF O

B ra n c h

U n it

P re fe tch

U n it

V E C S E G

T F R

+ /-

ID X 0

ID X 1

Q X 0

Q X 1

Q R 0

Q R 1

D P P 0

D P P 1

D P P 2

D P P 3

S P S E G

S P

S T K O V

S T K U N

+ /-

M R W

M C W

M S W

M A L

+ /-

M A H

M u ltip ly

U n it

A LU

D ivisio n U n it

M u ltip ly U n it

B it-M a sk-G e n .

B a rre l-S h ifte r

+ /-

M D C

P S W

M D H

Z E R O S

M D L

O N E S

R 0

R 1

G P R s

R 1 4

R 1 5

C P

W B

B u ffe r

2 -S ta g e

P re fe tc h

P ip e lin e

5 -S ta g e

P ip e lin e

R 0

R 1

G P R s

R 1 4

R 1 5

P M U

D M U

D S R A M

E B C

P eripherals

P S R A M

Flash/R O M

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,
while the remaining 15 cycles are executed in the background. Another pipeline
optimization, the branch target prediction, allows eliminating the execution time of
branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. One of these register banks is physically allocated within the
on-chip DPRAM area. A Context Pointer (CP) register determines the base address of
the active register bank to be accessed by the CPU at any time. The number of register
banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC161 instruction set which includes
the following instruction classes:
·

Standard Arithmetic Instructions

DSP-Oriented Arithmetic Instructions

Logical Instructions

Boolean Bit Manipulation Instructions

Compare and Loop Control Instructions

Shift and Rotate Instructions

Prioritize Instruction

Data Movement Instructions

System Stack Instructions

Jump and Call Instructions

Return Instructions

System Control Instructions

Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.4

Interrupt System

With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC161 is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC161 supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
`stolen' from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC161 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its
related register, each node can be programmed to one of sixteen interrupt priority levels.
Once having been accepted by the CPU, an interrupt service can only be interrupted by
a higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the `TRAP' instruction in combination with
an individual trap (interrupt) number.

Table 4

shows all of the possible XC161 interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may

be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

Table 4

XC161 Interrupt Nodes

Source of Interrupt or PEC
Service Request

Control
Register

Vector
Location

Trap
Number

CAPCOM Register 0

CC1_CC0IC

xx'0040

/ 16

CAPCOM Register 1

CC1_CC1IC

xx'0044

/ 17

CAPCOM Register 2

CC1_CC2IC

xx'0048

/ 18

CAPCOM Register 3

CC1_CC3IC

xx'004C

/ 19

CAPCOM Register 4

CC1_CC4IC

xx'0050

/ 20

CAPCOM Register 5

CC1_CC5IC

xx'0054

/ 21

CAPCOM Register 6

CC1_CC6IC

xx'0058

/ 22

CAPCOM Register 7

CC1_CC7IC

xx'005C

/ 23

CAPCOM Register 8

CC1_CC8IC

xx'0060

/ 24

CAPCOM Register 9

CC1_CC9IC

xx'0064

/ 25

CAPCOM Register 10

CC1_CC10IC

xx'0068

/ 26

CAPCOM Register 11

CC1_CC11IC

xx'006C

/ 27

CAPCOM Register 12

CC1_CC12IC

xx'0070

/ 28

CAPCOM Register 13

CC1_CC13IC

xx'0074

/ 29

CAPCOM Register 14

CC1_CC14IC

xx'0078

/ 30

CAPCOM Register 15

CC1_CC15IC

xx'007C

/ 31

CAPCOM Register 16

CC2_CC16IC

xx'00C0

/ 48

CAPCOM Register 17

CC2_CC17IC

xx'00C4

/ 49

CAPCOM Register 18

CC2_CC18IC

xx'00C8

/ 50

CAPCOM Register 19

CC2_CC19IC

xx'00CC

/ 51

CAPCOM Register 20

CC2_CC20IC

xx'00D0

/ 52

CAPCOM Register 21

CC2_CC21IC

xx'00D4

/ 53

CAPCOM Register 22

CC2_CC22IC

xx'00D8

/ 54

CAPCOM Register 23

CC2_CC23IC

xx'00DC

/ 55

CAPCOM Register 24

CC2_CC24IC

xx'00E0

/ 56

CAPCOM Register 25

CC2_CC25IC

xx'00E4

/ 57

CAPCOM Register 26

CC2_CC26IC

xx'00E8

/ 58

CAPCOM Register 27

CC2_CC27IC

xx'00EC

/ 59

CAPCOM Register 28

CC2_CC28IC

xx'00F0

/ 60

CAPCOM Register 29

CC2_CC29IC

xx'0110

/ 68

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

CAPCOM Register 30

CC2_CC30IC

xx'0114

/ 69

CAPCOM Register 31

CC2_CC31IC

xx'0118

/ 70

CAPCOM Timer 0

CC1_T0IC

xx'0080

/ 32

CAPCOM Timer 1

CC1_T1IC

xx'0084

/ 33

CAPCOM Timer 7

CC2_T7IC

xx'00F4

/ 61

CAPCOM Timer 8

CC2_T8IC

xx'00F8

/ 62

GPT1 Timer 2

GPT12E_T2IC

xx'0088

/ 34

GPT1 Timer 3

GPT12E_T3IC

xx'008C

/ 35

GPT1 Timer 4

GPT12E_T4IC

xx'0090

/ 36

GPT2 Timer 5

GPT12E_T5IC

xx'0094

/ 37

GPT2 Timer 6

GPT12E_T6IC

xx'0098

/ 38

GPT2 CAPREL Reg.

GPT12E_CRIC xx'009C

/ 39

A/D Conversion Compl.

ADC_CIC

xx'00A0

/ 40

A/D Overrun Error

ADC_EIC

xx'00A4

/ 41

ASC0 Transmit

ASC0_TIC

xx'00A8

/ 42

ASC0 Transmit Buffer

ASC0_TBIC

xx'011C

/ 71

ASC0 Receive

ASC0_RIC

xx'00AC

/ 43

ASC0 Error

ASC0_EIC

xx'00B0

/ 44

ASC0 Autobaud

ASC0_ABIC

xx'017C

/ 95

SSC0 Transmit

SSC0_TIC

xx'00B4

/ 45

SSC0 Receive

SSC0_RIC

xx'00B8

/ 46

SSC0 Error

SSC0_EIC

xx'00BC

/ 47

IIC Data Transfer Event

IIC_DTIC

xx'0100

/ 64

IIC Protocol Event

IIC_PEIC

xx'0104

/ 65

PLL/OWD

PLLIC

xx'010C

/ 67

ASC1 Transmit

ASC1_TIC

xx'0120

/ 72

ASC1 Transmit Buffer

ASC1_TBIC

xx'0178

/ 94

ASC1 Receive

ASC1_RIC

xx'0124

/ 73

ASC1 Error

ASC1_EIC

xx'0128

/ 74

ASC1 Autobaud

ASC1_ABIC

xx'0108

/ 66

Table 4

XC161 Interrupt Nodes (cont'd)

Source of Interrupt or PEC
Service Request

Control
Register

Vector
Location

Trap
Number

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

End of PEC Subch.

EOPIC

xx'0130

/ 76

SSC1 Transmit

SSC1_TIC

xx'0144

/ 81

SSC1 Receive

SSC1_RIC

xx'0148

/ 82

SSC1 Error

SSC1_EIC

xx'014C

/ 83

CAN0

CAN_0IC

xx'0150

/ 84

CAN1

CAN_1IC

xx'0154

/ 85

CAN2

CAN_2IC

xx'0158

/ 86

CAN3

CAN_3IC

xx'015C

/ 87

CAN4

CAN_4IC

xx'0164

/ 89

CAN5

CAN_5IC

xx'0168

/ 90

CAN6

CAN_6IC

xx'016C

/ 91

CAN7

CAN_7IC

xx'0170

/ 92

RTC

RTC_IC

xx'0174

/ 93

Unassigned node

xx'012C

/ 75

Unassigned node

xx'0134

/ 77

Unassigned node

xx'0138

/ 78

Unassigned node

xx'013C

/ 79

Unassigned node

xx'0140

/ 80

Unassigned node

xx'00FC

/ 63

Unassigned node

xx'0160

/ 88

1) Register VECSEG defines the segment where the vector table is located to.

Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.

Table 4

XC161 Interrupt Nodes (cont'd)

Source of Interrupt or PEC
Service Request

Control
Register

Vector
Location

Trap
Number

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

The XC161 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurrence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.

Table 5

shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 5

Hardware Trap Summary

Exception Condition

Trap
Flag

Trap
Vector

Vector
Location

1) Register VECSEG defines the segment where the vector table is located to.

Trap
Number

Trap
Priority

Reset Functions:
·

Hardware Reset

Software Reset

W-dog Timer Overflow

RESET
RESET
RESET

xx'0000

III
III
III

Class A Hardware Traps:
·

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

Software Break

NMI
STKOF
STKUF
SOFTBRK

NMITRAP
STOTRAP
STUTRAP
SBRKTRAP

xx'0008

xx'0010

xx'0018

xx'0020

II
II
II
II

Class B Hardware Traps:
·

Undefined Opcode

PMI Access Error

Protected Instruction
Fault

Illegal Word Operand
Access

UNDOPC
PACER
PRTFLT

ILLOPA

BTRAP
BTRAP
BTRAP

BTRAP

xx'0028

I
I
I

Reserved

[2C

- 3C

] [0B

]

Software Traps
·

TRAP Instruction

Any
[xx'0000

xx'01FC

]

in steps of
4

Any
[00

]

Current
CPU
Priority

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.5

On-Chip Debug Support (OCDS)

The On-Chip Debug Support system provides a broad range of debug and emulation
features built into the XC161. The user software running on the XC161 can thus be
debugged within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface,
consisting of the IEEE-1149-conforming JTAG port and a break interface. The debugger
controls the OCDS via a set of dedicated registers accessible via the JTAG interface.
Additionally, the OCDS system can be controlled by the CPU, e.g. by a monitor program.
An injection interface allows the execution of OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported as well as the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU-halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the JTAG interface or via the external bus interface for
increased performance.
The debug interface uses a set of 6 interface signals (4 JTAG lines, 2 break lines) to
communicate with external circuitry. These interface signals use dedicated pins.
Complete system emulation is supported by the New Emulation Technology (NET)
interface. Via this full-featured emulation interface (including internal buses, control,
status, and pad signals) the XC161 chip can be connected to a NET carrier chip.
The use of the XC161 production chip together with the carrier chip provides superior
emulation behavior, because the emulation system shows exactly the same functionality
as the production chip (use of the identical silicon).

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.6

Capture/Compare Units (CAPCOM1/2)

The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function.
All registers of each module have each one port pin associated with it which serves as
an input pin for triggering the capture function, or as an output pin to indicate the
occurrence of a compare event.

Table 6

Compare Modes (CAPCOM1/2)

Compare Modes

Function

Mode 0

Interrupt-only compare mode;
several compare interrupts per timer period are possible

Mode 1

Pin toggles on each compare match;
several compare events per timer period are possible

Mode 2

Interrupt-only compare mode;
only one compare interrupt per timer period is generated

Mode 3

Pin set `1' on match; pin reset `0' on compare timer overflow;
only one compare event per timer period is generated

Double Register
Mode

Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible

Single Event Mode

Generates single edges or pulses;
can be used with any compare mode

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (`captured') into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.7

General Purpose Timer (GPT12E) Unit

The GPT12E unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the `gate' level on an external input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected
to the incremental position sensor signals A and B via their respective inputs TxIN and
TxEUD. Direction and count signals are internally derived from these two input signals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite
state transitions of T3OTL with the low and high times of a PWM signal, this signal can
be constantly generated without software intervention.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

Figure 6

Block Diagram of GPT1

With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The

MCA05563

Aux. Timer T2

Mode

Control

Capture

U/D

Basic Clock

GPT

T3CON.BPS1

T3OTL

T3OUT

Toggle
Latch

T2IN

T2EUD

Reload

Core Timer T3

Mode

Control

T3IN

T3EUD

U/D

Interrupt
Request
(T3IRQ)

Mode

Control

U/D

Aux. Timer T4

T4EUD

T4IN

Reload

Capture

Interrupt
Request
(T4IRQ)

Interrupt
Request
(T2IRQ)

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD).
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the
CAPCOM1/2 timers, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared
after the capture procedure. This allows the XC161 to measure absolute time differences
or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.8

Real Time Clock

The Real Time Clock (RTC) module of the XC161 is directly clocked via a separate clock
driver either with the on-chip auxiliary oscillator frequency (

RTC

OSCa

) or with the

prescaled on-chip main oscillator frequency (

RTC

OSCm

/32). It is therefore independent

from the selected clock generation mode of the XC161.
The RTC basically consists of a chain of divider blocks:
·

a selectable 8:1 divider (on - off)

the reloadable 16-bit timer T14

the 32-bit RTC timer block (accessible via registers RTCH and RTCL), made of:
a reloadable 10-bit timer
a reloadable 6-bit timer
a reloadable 6-bit timer
a reloadable 10-bit timer

All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.

Figure 8

RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

CNT-Register

REL-Register

10 Bits

6 Bits

10 Bits

T14

MCB05568

T14-Register

Interrupt Sub Node

RTCINT

MUX

PRE

RUN

CNT
INT3

CNT
INT2

CNT
INT1

CNT
INT0

CNT

RTC

T14REL

10 Bits

6 Bits

10 Bits

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.9

A/D Converter

For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the method
of successive approximation. The sample time (for loading the capacitors) and the
conversion time is programmable (in two modes) and can thus be adjusted to the
external circuitry. The A/D converter can also operate in 8-bit conversion mode, where
the conversion time is further reduced.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversion has not been read from the result register at the time the next conversion is
complete, or the next conversion is suspended in such a case until the previous result
has been read.
For applications which require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converter of the XC161 supports four different conversion modes. In the
standard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous mode,
the analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the prespecified channels are repeatedly sampled and converted. In
addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via register P5DIDIS
(Port 5 Digital Input Disable).
The Auto-Power-Down feature of the A/D converter minimizes the power consumption
when no conversion is in progress.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.10

Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1)

The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial
communication with other microcontrollers, processors, terminals or external peripheral
components. They are upward compatible with the serial ports of the Infineon 8-bit
microcontroller families and support full-duplex asynchronous communication and half-
duplex synchronous communication. A dedicated baud rate generator with a fractional
divider precisely generates all standard baud rates without oscillator tuning. For
transmission, reception, error handling, and baudrate detection 5 separate interrupt
vectors are provided.
In asynchronous mode, 8- or 9-bit data frames (with optional parity bit) are transmitted
or received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake-up bit mode). IrDA data transmissions up to
115.2 kbit/s with fixed or programmable IrDA pulse width are supported.
In synchronous mode, bytes (8 bits) are transmitted or received synchronously to a shift
clock which is generated by the ASC0/1. The LSB is always shifted first.
In both modes, transmission and reception of data is FIFO-buffered. An autobaud
detection unit allows to detect asynchronous data frames with its baudrate and mode
with automatic initialization of the baudrate generator and the mode control bits.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.

Summary of Features
·

Full-duplex asynchronous operating modes
8- or 9-bit data frames, LSB first, one or two stop bits, parity generation/checking
Baudrate from 2.5 Mbit/s to 0.6 bit/s (@ 40 MHz)
Multiprocessor mode for automatic address/data byte detection
Support for IrDA data transmission/reception up to max. 115.2 kbit/s (@ 40 MHz)
Loop-back capability
Auto baudrate detection

Half-duplex 8-bit synchronous operating mode at 5 Mbit/s to 406.9 bit/s (@ 40 MHz)

Buffered transmitter/receiver with FIFO support (8 entries per direction)

Loop-back option available for testing purposes

Interrupt generation on transmitter buffer empty condition, last bit transmitted
condition, receive buffer full condition, error condition (frame, parity, overrun error),
start and end of an autobaud detection

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.11

High Speed Synchronous Serial Channels (SSC0/SSC1)

The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and half-
duplex synchronous communication. It may be configured so it interfaces with serially
linked peripheral components, full SPI functionality is supported.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling three separate interrupt
vectors are provided.
The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit error and receive error supervise the correct
handling of the data buffer. Phase error and baudrate error detect incorrect serial data.

Summary of Features
·

Master or Slave mode operation

Full-duplex or Half-duplex transfers

Baudrate generation from 20 Mbit/s to 305.18 bit/s (@ 40 MHz)

Flexible data format
Programmable number of data bits: 2 to 16 bits
Programmable shift direction: LSB-first or MSB-first
Programmable clock polarity: idle low or idle high
Programmable clock/data phase: data shift with leading or trailing clock edge

Loop back option available for testing purposes

Interrupt generation on transmitter buffer empty condition, receive buffer full
condition, error condition (receive, phase, baudrate, transmit error)

Three pin interface with flexible SSC pin configuration

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.12

TwinCAN Module

The integrated TwinCAN module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
Two Full-CAN nodes share the TwinCAN module's resources to optimize the CAN bus
traffic handling and to minimize the CPU load. The module provides up to 32 message
objects, which can be assigned to one of the CAN nodes and can be combined to FIFO-
structures. Each object provides separate masks for acceptance filtering.
The flexible combination of Full-CAN functionality and FIFO architecture reduces the
efforts to fulfill the real-time requirements of complex embedded control applications.
Improved CAN bus monitoring functionality as well as the number of message objects
permit precise and comfortable CAN bus traffic handling.
Gateway functionality allows automatic data exchange between two separate CAN bus
systems, which reduces CPU load and improves the real time behavior of the entire
system.
The bit timing for both CAN nodes is derived from the master clock and is programmable
up to a data rate of 1 Mbit/s. Each CAN node uses two pins of Port 4, Port 7, or Port 9 to
interface to an external bus transceiver. The interface pins are assigned via software.

Figure 9

TwinCAN Module Block Diagram

TwinCAN Module Kernel

MCB05567

TxDCA

RxDCA

TxDCB

RxDCB

CAN

Node A

CAN

Node B

Message

Object

Buffer

Clock

Control

CAN

Interrupt

Control

Address

Decoder

TwinCAN Control

Port

Control

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

Summary of Features
·

CAN functionality according to CAN specification V2.0 B active

Data transfer rate up to 1 Mbit/s

Flexible and powerful message transfer control and error handling capabilities

Full-CAN functionality and Basic CAN functionality for each message object

32 flexible message objects
Assignment to one of the two CAN nodes
Configuration as transmit object or receive object
Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm
Handling of frames with 11-bit or 29-bit identifiers
Individual programmable acceptance mask register for filtering for each object
Monitoring via a frame counter
Configuration for Remote Monitoring Mode

Up to eight individually programmable interrupt nodes can be used

CAN Analyzer Mode for bus monitoring is implemented

Note: When a CAN node has the interface lines assigned to Port 4, the segment address

output on Port 4 must be limited. CS lines can be used to increase the total amount
of addressable external memory.

3.13

IIC Bus Module

The integrated IIC Bus Module handles the transmission and reception of frames over
the two-line IIC bus in accordance with the IIC Bus specification. The IIC Module can
operate in slave mode, in master mode or in multi-master mode. It can receive and
transmit data using 7-bit or 10-bit addressing. Up to 4 send/receive data bytes can be
stored in the extended buffers.
Several physical interfaces (port pins) can be established under software control. Data
can be transferred at speeds up to 400 kbit/s.
Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also
support operation via PEC transfers.
Note: The port pins associated with the IIC interfaces must be switched to open drain

mode, as required by the IIC specification.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

3.14

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip's start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by
2/4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13

µs and 419 ms can be monitored (@ 40 MHz).

The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).

XC161-32

Derivatives

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Data Sheet

V1.0, 2004-11

3.15

Clock Generation

The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
to generate the clock signals for the XC161 with high flexibility. The master clock

the reference clock signal, and is used for TwinCAN and is output to the external system.
The CPU clock

CPU

and the system clock

SYS

are derived from the master clock either

directly (1:1) or via a 2:1 prescaler (

SYS

CPU

/ 2). See also

Section 4.4.1

The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Note: At the end of an external reset (EA = `0') the oscillator watchdog may be disabled

via hardware by (externally) pulling the RD line low upon a reset, similar to the
standard reset configuration.

3.16

Parallel Ports

The XC161 provides up to 99 I/O lines which are organized into nine input/output ports
and one input port. All port lines are bit-addressable, and all input/output lines are
individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O
ports are true bidirectional ports which are switched to high impedance state when
configured as inputs. The output drivers of some I/O ports can be configured (pin by pin)
for push/pull operation or open-drain operation via control registers. During the internal
reset, all port pins are configured as inputs (except for pin RSTOUT).
The edge characteristics (shape) and driver characteristics (output current) of the port
drivers can be selected via registers POCONx.
The input threshold of some ports is selectable (TTL or CMOS like), where the special
CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The
input threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

Table 7

Summary of the XC161's Parallel Ports

Port

Control

Alternate Functions

PORT0

Pad drivers

Address/Data lines or data lines

PORT1

Pad drivers

Address lines

Capture inputs or compare outputs,
Serial interface lines

Port 2

Pad drivers,
Open drain,
Input threshold

Capture inputs or compare outputs,
Timer control signal,
Fast external interrupt inputs

Port 3

Pad drivers,
Open drain,
Input threshold

Timer control signals, serial interface lines,
Optional bus control signal BHE/WRH,
System clock output CLKOUT (or FOUT)

Port 4

Pad drivers,
Open drain,
Input threshold

Segment address lines

CAN interface lines

Port 5

Analog input channels to the A/D converter,
Timer control signals

Port 6

Open drain,
Input threshold

Capture inputs or compare outputs,
Bus arbitration signals BREQ, HLDA, HOLD,
Optional chip select signals

Port 7

Open drain,
Input threshold

Capture inputs or compare outputs,
CAN interface lines

Port 9

Pad drivers,
Open drain,
Input threshold

Capture inputs or compare outputs
CAN interface lines

IIC bus interface lines

Port 20

Pad drivers,
Open drain

Bus control signals RD, WR/WRL, READY, ALE,
External access enable pin EA,
Reset indication output RSTOUT

1) For multiplexed bus cycles.
2) For demultiplexed bus cycles.
3) For more than 64 Kbytes of external resources.
4) Can be assigned by software.

XC161-32

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Functional Description

Data Sheet

V1.0, 2004-11

3.17

Power Management

The XC161 provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
·

Power Saving Modes switch the XC161 into a special operating mode (control via
instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.

Clock Generation Management controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC161's CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output FOUT.

Peripheral Management permits temporary disabling of peripheral modules (control
via register SYSCON3). Each peripheral can separately be disabled/enabled.

The on-chip RTC supports intermittent operation of the XC161 by generating cyclic
wake-up signals. This offers full performance to quickly react on action requests while
the intermittent sleep phases greatly reduce the average power consumption of the
system.

XC161-32

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Functional Description

Data Sheet

V1.0, 2004-11

3.18

Instruction Set Summary

Table 8

lists the instructions of the XC161 in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the "Instruction Set Manual".
This document also provides a detailed description of each instruction.

Table 8

Instruction Set Summary

Mnemonic

Description

Bytes

ADD(B)

Add word (byte) operands

2 / 4

ADDC(B)

Add word (byte) operands with Carry

2 / 4

SUB(B)

Subtract word (byte) operands

2 / 4

SUBC(B)

Subtract word (byte) operands with Carry

2 / 4

MUL(U)

(Un)Signed multiply direct GPR by direct GPR
(16-

× 16-bit)

DIV(U)

(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

DIVL(U)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

CPL(B)

Complement direct word (byte) GPR

NEG(B)

Negate direct word (byte) GPR

AND(B)

Bitwise AND, (word/byte operands)

2 / 4

(X)OR(B)

Bitwise (exclusive) OR, (word/byte operands)

2 / 4

BCLR/BSET

Clear/Set direct bit

BMOV(N)

Move (negated) direct bit to direct bit

BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit

BCMP

Compare direct bit to direct bit

BFLDH/BFLDL

Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data

CMP(B)

Compare word (byte) operands

2 / 4

CMPD1/2

Compare word data to GPR and decrement GPR by 1/2

2 / 4

CMPI1/2

Compare word data to GPR and increment GPR by 1/2

2 / 4

PRIOR

Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR

SHL/SHR

Shift left/right direct word GPR

ROL/ROR

Rotate left/right direct word GPR

XC161-32

Derivatives

Functional Description

Data Sheet

V1.0, 2004-11

ASHR

Arithmetic (sign bit) shift right direct word GPR

MOV(B)

Move word (byte) data

2 / 4

MOVBS/Z

Move byte operand to word op. with sign/zero extension

2 / 4

JMPA/I/R

Jump absolute/indirect/relative if condition is met

JMPS

Jump absolute to a code segment

JB(C)

Jump relative if direct bit is set (and clear bit)

JNB(S)

Jump relative if direct bit is not set (and set bit)

CALLA/I/R

Call absolute/indirect/relative subroutine if condition is met 4

CALLS

Call absolute subroutine in any code segment

PCALL

Push direct word register onto system stack and call
absolute subroutine

TRAP

Call interrupt service routine via immediate trap number

PUSH/POP

Push/pop direct word register onto/from system stack

SCXT

Push direct word register onto system stack and update
register with word operand

RET(P)

Return from intra-segment subroutine
(and pop direct word register from system stack)

RETS

Return from inter-segment subroutine

RETI

Return from interrupt service subroutine

SBRK

Software Break

SRST

Software Reset

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode (supposes NMI-pin being low)

SRVWDT

Service Watchdog Timer

DISWDT/ENWDT

Disable/Enable Watchdog Timer

EINIT

Signify End-of-Initialization on RSTOUT pin

ATOMIC

Begin ATOMIC sequence

EXTR

Begin EXTended Register sequence

EXTP(R)

Begin EXTended Page (and Register) sequence

2 / 4

EXTS(R)

Begin EXTended Segment (and Register) sequence

2 / 4

NOP

Null operation

Table 8

Instruction Set Summary (cont'd)

Mnemonic

Description

Bytes

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Electrical Parameters

4.1

General Parameters

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (

DDP

) the

voltage on

DDP

pins with respect to ground (

) must not exceed the values

defined by the absolute maximum ratings.

Table 9

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit

Notes

Min.

Max.

Storage temperature

-65

150

°C

Junction temperature

-40

150

°C

under bias

Voltage on

DDI

pins with

respect to ground (

)

DDI

-0.5

3.25

Voltage on

DDP

pins with

respect to ground (

)

DDP

-0.5

6.2

Voltage on any pin with
respect to ground (

)

-0.5

DDP

0.5

Input current on any pin
during overload condition

-10

Absolute sum of all input
currents during overload
condition

|100|

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XC161. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.

Table 10

Operating Condition Parameters

Parameter

Symbol

Limit Values

Unit Notes

Min.

Max.

Digital supply voltage for
the core

DDI

2.35

2.7

Active mode,

CPU

CPUmax

= 40 MHz for devices marked ... 40F,

CPUmax

= 20 MHz for devices marked ... 20F.

Digital supply voltage for
IO pads

DDP

4.4

5.5

Active mode

2)3)

2) External circuitry must guarantee low-level at the RSTIN pin at least until both power supply voltages have

reached the operating range.

3) The specified voltage range is allowed for operation. The range limits may be reached under extreme

operating conditions. However, specified parameters, such as leakage currents, refer to the standard
operating voltage range of

DDP

= 4.75 V to 5.25 V.

Supply Voltage Difference

-0.5

DDP

DDI

4) This limitation must be fulfilled under all operating conditions including power-ramp-up, power-ramp-down,

and power-save modes.

Digital ground voltage

Reference voltage

Overload current

-5

Per IO pin

5)6)

-2

Per analog input
pin

5)6)

Overload current coupling
factor for analog inputs

OVA

1.0

× 10

-4

> 0

1.5

× 10

-3

< 0

Overload current coupling
factor for digital I/O pins

OVD

5.0

× 10

-3

> 0

1.0

× 10

-2

< 0

Absolute sum of overload
currents

External Load
Capacitance

Pin drivers in
default mode

Ambient temperature

°C

SAB-XC161...

-40

°C

SAF-XC161...

-40

125

°C

SAK-XC161...

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the XC161
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column "Symbol":
CC (Controller Characteristics):
The logic of the XC161 will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
XC161.

5) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range:

DDP

+ 0.5 V (

> 0) or

- 0.5 V (

< 0). The absolute sum of

input overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the
specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.

6) Not subject to production test - verified by design/characterization.
7) An overload current (

) through a pin injects a certain error current (

INJ

) into the adjacent pins. This error

current adds to the respective pin's leakage current (

). The amount of error current depends on the overload

current and is defined by the overload coupling factor

. The polarity of the injected error current is inverse

compared to the polarity of the overload current that produces it.
The total current through a pin is |

TOT

| = |

| + (|

). The additional error current may distort the input

voltage on analog inputs.

8) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output

current may lead to increased delays or reduced driving capability (

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

4.2

DC Parameters

Table 11

DC Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test Condition

Min.

Max.

Input low voltage TTL
(all except XTAL1,
XTAL3)

SR -0.5

0.2

DDP

- 0.1

Input low voltage for
XTAL1, XTAL3

ILC

SR -0.5

0.3

DDI

Input low voltage
(Special Threshold)

ILS

SR -0.5

0.45

DDP

Input high voltage TTL
(all except XTAL1,
XTAL3)

SR 0.2

DDP

+ 0.9

DDP

+ 0.5 V

Input high voltage
XTAL1, XTAL3

IHC

SR 0.7

DDI

+ 0.5 V

Input high voltage
(Special Threshold)

IHS

SR 0.8

DDP

- 0.2

DDP

+ 0.5 V

Input Hysteresis
(Special Threshold)

HYS

0.04

DDP

in [V],

Series resis-
tance = 0

Output low voltage

1.0

OLmax

0.45

OLnom

4)5)

Output high voltage

DDP

- 1.0

OHmax

DDP

0.45

OHnom

4)5)

Input leakage current
(Port 5)

OZ1

±300

0 V <

DDP

125 °C

±200

0 V <

DDP

85 °C

14)

Input leakage current
(all other

)

OZ2

±500

0.45 V <

DDP

Configuration pull-up
current

CPUH

10)

-10

µA

IHmin

CPUL

11)

-100

µA

ILmax

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Configuration pull-
down current

12)

CPDL

10)

µA

ILmax

CPDH

11)

120

µA

IHmin

Level inactive hold
current

13)

LHI

10)

-10

µA

OUT

= 0.5

DDP

Level active hold
current

13)

LHA

11)

-100

µA

OUT

= 0.45 V

XTAL1, XTAL3 input
current

±20

µA

0 V <

DDI

Pin capacitance

14)

(digital inputs/outputs)

1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications, also refer to the specification of the overload current

2) If XTAL3 is driven by a crystal, reaching an amplitude (peak to peak) of 0.25

DDI

is sufficient.

3) This parameter is tested for P2, P3, P4, P6, P7, P9.
4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see

Table 12

Current Limits for Port Output Drivers

. The limit for pin groups must be respected.

5) As a rule, with decreasing output current the output levels approach the respective supply level (

DDP

). However, only the levels for nominal output currents are guaranteed.

6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

7) An additional error current (

INJ

) will flow if an overload current flows through an adjacent pin. Please refer to

the definition of the overload coupling factor

8) The driver of P3.15 is designed for faster switching, because this pin can deliver the reference clock for the

bus interface (CLKOUT). The maximum leakage current for P3.15 is, therefore, increased to 1

µA.

9) This specification is valid during Reset for configuration on RD, WR, EA, PORT0.

The pull-ups on RD and WR (WRL/WRH) are also active during bus hold.

10) The maximum current may be drawn while the respective signal line remains inactive.
11) The minimum current must be drawn to drive the respective signal line active.
12) This specification is valid during Reset for configuration on ALE.

The pull-down on ALE is also active during bus hold.

13) This specification is valid during Reset for pins P6.4-0, which can act as CS outputs.

The pull-ups on CS outputs are also active during bus hold.
The pull-up on pin HLDA is active when arbitration is enabled and the EBC operates in slave mode.

14) Not subject to production test - verified by design/characterization.

Table 11

DC Characteristics (Operating Conditions apply)

(cont'd)

Parameter

Symbol

Limit Values

Unit Test Condition

Min.

Max.

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Table 12

Current Limits for Port Output Drivers

Port Output Driver
Mode

Maximum Output Current
(

OLmax

, -

OHmax

)

Nominal Output Current
(

OLnom

, -

OHnom

)

Strong driver

10 mA

2.5 mA

Medium driver

4.0 mA

1.0 mA

Weak driver

0.5 mA

0.1 mA

1) An output current above |

OXnom

| may be drawn from up to three pins at the same time.

For any group of 16 neighboring port output pins the total output current in each direction (

and

) must

remain below 50 mA.

Table 13

Power Consumption (Operating Conditions apply)

Parameter

Sym-
bol

Limit Values

Unit Test Condition

Min.

Max.

Power supply current (active)
with all peripherals active

DDI

10 +
3.0

CPU

in [MHz]

1)2)

1) During Flash programming or erase operations the supply current is increased by max. 5 mA.
2) The supply current is a function of the operating frequency. This dependency is illustrated in

Figure 10

These parameters are tested at

DDImax

and maximum CPU clock frequency with all outputs disconnected and

all inputs at

Pad supply current

DDP

3) The pad supply voltage pins (

DDP

) mainly provide the current consumed by the pin output drivers. This output

driver current is not covered by parameter

DDP

. A small amount of current is consumed even though no

outputs are driven, because the drivers' input stages are switched and also the Flash module draws some
power from the

DDP

supply.

Idle mode supply current
with all peripherals active

IDX

10 +
1.3

CPU

in [MHz]

Sleep and Power down mode
supply current caused by
leakage

PDL

128,000
× e

DDI

DDImax

in [

°C]

=
4670 / (273 +

)

Sleep and Power down mode
supply current caused by
leakage and the RTC running,
clocked by the main oscillator

PDM

0.6 +
0.02

OSC

PDL

DDI

DDImax

OSC

in [MHz]

Sleep and Power down mode
supply current caused by
leakage and the RTC running,
clocked by the auxiliary
oscillator at 32 kHz

PDA

0.1 +

PDL

DDI

DDImax

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

4) The total supply current in Sleep and Power down mode is the sum of the temperature dependent leakage

current and the frequency dependent current for RTC and main oscillator or auxiliary oscillator (if active).

5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the

junction temperature (see

Figure 12

). The junction temperature

is the same as the ambient temperature

if no current flows through the port output drivers. Otherwise, the resulting temperature difference must be
taken into account.

6) All inputs (including JTAG pins and pins configured as inputs) at 0 V to 0.1 V or at

DDP

- 0.1 V to

DDP

, all

outputs (including pins configured as outputs) disconnected. This parameter is tested at 25

°C and is valid for

25 °C.

7) This parameter is determined mainly by the current consumed by the oscillator switched to low gain mode (see

Figure 11

). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The

given values refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

4.3

Analog/Digital Converter Parameters

Table 14

A/D Converter Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit Test

Condition

Min.

Max.

Analog reference supply

AREF

SR 4.5

DDP

+ 0.1

1) TUE is tested at

AREF

DDP

+ 0.1 V,

AGND

= 0 V. It is verified by design for all other voltages within the

defined voltage range.
If the analog reference supply voltage drops below 4.5 V (and

AREF

4.0 V) or exceeds the power supply

voltage by up to 0.2 V (i.e.

AREF

DDP

+ 0.2 V) the maximum TUE is increased to

±3 LSB. This range is not

subject to production test.
The specified TUE is guaranteed only, if the absolute sum of input overload currents on Port 5 pins (see

specification) does not exceed 10 mA, and if

AREF

and

AGND

remain stable during the respective period of

time. During the reset calibration sequence the maximum TUE may be

±4 LSB.

Analog reference ground

AGND

- 0.1

+ 0.1

Analog input voltage range

AIN

AGND

AREF

AIN

may exceed

AGND

AREF

up to the absolute maximum ratings. However, the conversion result in these

cases will be X000

or X3FF

, respectively.

Basic clock frequency

0.5

MHz

Conversion time for 10-bit
result

C10P

CC 52

+ 6

SYS

Post-calibr. on

C10

CC 40

+ 6

SYS

Post-calibr. off

Conversion time for 8-bit
result

C8P

CC 44

+ 6

SYS

Post-calibr. on

CC 32

+ 6

SYS

Post-calibr. off

Calibration time after reset

CAL

CC 484

11,696

Total unadjusted error

TUE

±2

LSB

Total capacitance
of an analog input

AINT

Switched capacitance
of an analog input

AINS

Resistance of
the analog input path

AIN

Total capacitance
of the reference input

AREFT

Switched capacitance
of the reference input

AREFS

Resistance of
the reference input path

AREF

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Figure 13

Equivalent Circuitry for Analog Inputs

3) The limit values for

must not be exceeded when selecting the peripheral frequency and the ADCTC setting.

4) This parameter includes the sample time

, the time for determining the digital result and the time to load the

result register with the conversion result (

SYS

= 1/

SYS

Values for the basic clock

depend on programming and can be taken from

Table 15

When the post-calibration is switched off, the conversion time is reduced by 12 x

5) The actual duration of the reset calibration depends on the noise on the reference signal. Conversions

executed during the reset calibration increase the calibration time. The TUE for those conversions may be
increased.

6) Not subject to production test - verified by design/characterization.

The given parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) reduced values can be used for calculations. At room temperature and nominal
supply voltage the following typical values can be used:

AINTtyp

= 12 pF,

AINStyp

= 7 pF,

AINtyp

= 1.5 k

AREFTtyp

= 15 pF,

AREFStyp

= 13 pF,

AREFtyp

= 0.7 k

A/D Converter

MCS05570

Source

AIN

Ext

AINT

AINS

AIN, On

AINS

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

Sample time and conversion time of the XC161's A/D Converter are programmable. In
compatibility mode, the above timing can be calculated using

Table 15

The limit values for

must not be exceeded when selecting ADCTC.

Converter Timing Example:

Table 15

A/D Converter Computation Table

1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock

can be selected.

ADCON.15|14
(ADCTC)

A/D Converter
Basic Clock

ADCON.13|12
(ADSTC)

Sample Time

SYS

/ 4

× 8

SYS

/ 2

× 16

SYS

/ 16

× 32

SYS

/ 8

× 64

Assumptions:

SYS

= 40 MHz (i.e.

SYS

= 25 ns), ADCTC = `01', ADSTC = `00'

Basic clock

SYS

/ 2 = 20 MHz, i.e.

= 50 ns

Sample time

× 8 = 400 ns

Conversion 10-bit:
With post-calibr.

C10P

= 52

+ 6

SYS

= (2600 + 400 + 150) ns = 3.15

µs

Post-calibr. off

C10

= 40

+ 6

SYS

= (2000 + 400 + 150) ns = 2.55

µs

Conversion 8-bit:
With post-calibr.

C8P

= 44

+ 6

SYS

= (2200 + 400 + 150) ns = 2.75

µs

Post-calibr. off

= 32

+ 6

SYS

= (1600 + 400 + 150) ns = 2.15

µs

XC161-32

Derivatives

Electrical Parameters

Data Sheet

V1.0, 2004-11

4.4

AC Parameters

4.4.1

Definition of Internal Timing

The internal operation of the XC161 is controlled by the internal master clock

The master clock signal

can be generated from the oscillator clock signal

OSC

via

different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate

This influence must be regarded when calculating the timings for the XC161.

Figure 14

Generation Mechanisms for the Master Clock

Note: The example for PLL operation shown in

Figure 14

refers to a PLL factor of 1:4,

the example for prescaler operation refers to a divider factor of 2:1.

The used mechanism to generate the master clock is selected by register PLLCON.

MCT05555

Phase Locked Loop Operation (1:N)

OSC

Direct Clock Drive (1:1)

Prescaler Operation (N:1)

OSC

TCM

XC161-32

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Data Sheet

V1.0, 2004-11

CPU and EBC are clocked with the CPU clock signal

CPU

. The CPU clock can have the

same frequency as the master clock (

CPU

) or can be the master clock divided by

two:

CPU

/ 2. This factor is selected by bit CPSYS in register SYSCON1.

The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called "TCP".
The other peripherals are supplied with the system clock signal

SYS

which has the same

frequency as the CPU clock signal

CPU

Bypass Operation
When bypass operation is configured (PLLCTRL = 0x

) the master clock is derived from

the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:

OSC

/ ((PLLIDIV+1)

× (PLLODIV+1)).

If both divider factors are selected as `1' (PLLIDIV = PLLODIV = `0') the frequency of

directly follows the frequency of

OSC

so the high and low time of

is defined by the duty

cycle of the input clock

OSC

The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:

OSC

/ ((3 + 1)

× (14 + 1)) =

OSC

/ 60.

Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11

) the on-chip phase locked loop is

enabled and provides the master clock. The PLL multiplies the input frequency by the
factor F (

OSC

× F) which results from the input divider, the multiplication factor, and

the output divider (F = PLLMUL+1 / (PLLIDIV+1

× PLLODIV+1)). The PLL circuit

synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of

is constantly adjusted so it

is locked to

OSC

. The slight variation causes a jitter of

which also affects the duration

of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because

CPU

is derived from

, the timing must be calculated using the minimum TCP possible under the respective

circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and

Figure 15

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

XC161-32

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Data Sheet

V1.0, 2004-11

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal

. Therefore,

the number of VCO cycles can be represented as K

× N, where N is the number of

consecutive

cycles (TCM).

For a period of N

× TCM the accumulated PLL jitter is defined by the deviation D

[ns] =

±(1.5 + 6.32 × N /

);

in [MHz], N = number of consecutive TCMs.

So, for a period of 3 TCMs @ 20 MHz and K = 12: D

±(1.5 + 6.32 × 3 / 20) = 2.448 ns.

This formula is applicable for K

× N < 95. For longer periods the K × N = 95 value can be

used. This steady value can be approximated by: D

Nmax

[ns] =

±(1.5 + 600 / (K ×

)).

Figure 15

Approximated Accumulated PLL Jitter

Note: The bold lines indicate the minimum accumulated jitter which can be achieved by

selecting the maximum possible output prescaler factor K.

Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:

MCD05566

±1

±2

±3

±4

±5

±6

±7

±8

Acc. jitter

K = 15

K = 12

K = 10

K = 8

K = 6 K = 5

10 MHz

20 MHz

40 MHz

XC161-32

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Data Sheet

V1.0, 2004-11

4.4.2

External Clock Drive XTAL1

Figure 16

External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal or a ceramic resonator, the

oscillator frequency is limited to a range of 4 MHz to 16 MHz.
It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimum
parameters for the oscillator operation. Please refer to the limits specified by the
crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is verified by design
only (not subject to production test).

Table 17

External Clock Drive Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

Unit

Min.

Max.

Oscillator period

OSC

250

1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.

High time

2) The clock input signal must reach the defined levels

ILC

and

IHC

Low time

Rise time

Fall time

MCT05572

OSC

0.5

DDI

ILC

IHC

XC161-32

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Data Sheet

V1.0, 2004-11

4.4.3

Testing Waveforms

Figure 17

Input Output Waveforms

Figure 18

Float Waveforms

MCD05556

0.45 V

0.8 V

2.0 V

Input Signal
(driven by tester)

Output Signal

(measured)

Hold time

Output delay

Hold time

Output timings refer to the rising edge of CLKOUT.
Input timings are calculated from the time, when the input signal reaches

, respectively.

MCA05565

Timing

Reference

Points

Load

+ 0.1 V

Load

- 0.1 V

+ 0.1 V

For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded

level occurs (

= 20 mA).

XC161-32

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Data Sheet

V1.0, 2004-11

Variable Memory Cycles
External bus cycles of the XC161 are executed in five subsequent cycle phases (AB, C,
D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module via
the READY handshake input.
This table provides a summary of the phases and the respective choices for their
duration.

Note: The bandwidth of a parameter (minimum and maximum value) covers the whole

operating range (temperature, voltage) as well as process variations. Within a
given device, however, this bandwidth is smaller than the specified range. This is
also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).

Table 19

Programmable Bus Cycle Phases (see timing diagrams)

Bus Cycle Phase

Parameter Valid Values Unit

Address setup phase, the standard duration of this
phase (1 ... 2 TCP) can be extended by 0 ... 3 TCP
if the address window is changed

1 ... 2 (5)

TCP

Command delay phase

0 ... 3

TCP

Write Data setup/MUX Tristate phase

0 ... 1

TCP

Access phase

1 ... 32

TCP

Address/Write Data hold phase

0 ... 3

TCP

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Note: The shaded parameters have been verified by characterization.

They are not subject to production test.

Table 20

External Bus Cycle Timing (Operating Conditions apply)

Parameter

Symbol

Limits

Unit

Min.

Max.

Output valid delay for:
RD, WR(L/H)

Output valid delay for:
BHE, ALE

-1

Output valid delay for:
A23 ... A16, A15 ... A0 (on PORT1)

Output valid delay for:
A15 ... A0 (on PORT0)

Output valid delay for:
CS

Output valid delay for:
D15 ... D0 (write data, MUX-mode)

Output valid delay for:
D15 ... D0 (write data, DEMUX-mode)

Output hold time for:
RD, WR(L/H)

-3

Output hold time for:
BHE, ALE

Output hold time for:
A23 ... A16, A15 ... A0 (on PORT0)

Output hold time for:
CS

-2

Output hold time for:
D15 ... D0 (write data)

Input setup time for:
READY, D15 ... D0 (read data)

Input hold time
READY, D15 ... D0 (read data)

-5

1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge

of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.

XC161-32

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Data Sheet

V1.0, 2004-11

Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage. The minimum duration
of an asynchronous READY signal to be safely synchronized must be one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next following bus cycle is READY-controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the programmed phases of the next following cycle.

XC161-32

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Data Sheet

V1.0, 2004-11

Figure 22

READY Timing

Note: If the READY input is sampled inactive at the indicated sampling point ("Not Rdy")

a READY-controlled waitstate is inserted (

RDY

sampling the READY input active at the indicated sampling point ("Ready")
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see

) before the READY input is

evaluated.

MCT05559

READY
Asynchron.

Not Rdy

READY

Data Out

D15-D0
(write)

READY
Synchronous

Not Rdy

READY

Data In

D15-D0
(read)

RD, WR

RDY

CLKOUT

XC161-32

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Data Sheet

V1.0, 2004-11

Figure 24

External Bus Arbitration, Regaining the Bus

Notes
1. This is the last chance for BREQ to trigger the indicated regain-sequence.

Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going
high. Please note that HOLD may also be deactivated without the XC161 requesting
the bus.

2. The control outputs will be resistive high (pull-up) before being driven inactive (ALE

will be low).

3. The next XC161 driven bus cycle may start here.

MCT05561

Addr, Data,
BHE

CSx, RD,
WR(L/H)

BREQ

HOLD

HLDA

CLKOUT

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