TECHNICAL DATA
269
Quad D Flip-Flop with
Common Clock and Reset
High-Speed Silicon-Gate CMOS
The IN74ACT175 is identical in pinout to the LS/ALS175,
HC/HCT175. The IN74ACT175 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of four D flip-flops with common Reset and
Clock inputs, and separate D inputs. Reset (active-low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive-going edge of the Clock input.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
A; 0.1
A @ 25
C
Outputs Source/Sink 24 mA
IN74ACT175
ORDERING INFORMATION
IN74ACT175N Plastic
IN74ACT175D SOIC
T
A
= -40
to 85
C for all
packages
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
Reset
Clock
D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
no change
X = Don't care
LOGIC DIAGRAM
PIN 16=V
CC
PIN 8 = GND
IN74ACT175
270
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Sink/Source Current, per Pin
50
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
J
Junction Temperature (PDIP)
140
C
T
A
Operating Temperature, All Package Types
-40
+85
C
I
OH
Output Current - High
-24
mA
I
OL
Output Current - Low
24
mA
t
r
, t
f
Input Rise and Fall Time
*
(except Schmitt Inputs)
V
CC
=4.5 V
V
CC
=5.5 V
0
0
10
8.0
ns/V
*
V
IN
from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
IN74ACT175
271
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limits
Symbol
Parameter
Test Conditions
V
25
C
-40
C to
85
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
V
V
IL
Maximum Low -
Level Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
V
OH
Minimum High-Level
Output Voltage
I
OUT
-50
A
4.5
5.5
4.4
5.4
4.4
5.4
V
*
V
IN
=V
IH
or V
IL
I
OH
=-24 mA
I
OH
=-24 mA
4.5
5.5
3.86
4.86
3.76
4.76
V
OL
Maximum Low-Level
Output Voltage
I
OUT
50
A
4.5
5.5
0.1
0.1
0.1
0.1
V
*
V
IN
=V
IH
or V
IL
I
OL
=24 mA
I
OL
=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
I
IN
Maximum Input
Leakage Current
V
IN
=V
CC
or GND
5.5
0.1
1.0
A
I
CCT
Additional Max.
I
CC
/Input
V
IN
=V
CC
- 2.1 V
5.5
1.5
mA
I
OLD
+Minimum Dynamic
Output Current
V
OLD
=1.65 V Max
5.5
75
mA
I
OHD
+Minimum Dynamic
Output Current
V
OHD
=3.85 V Min
5.5
-75
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
5.5
8.0
80
A
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
IN74ACT175
272
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
C
-40
C to 85
C
Unit
Min
Max
Min
Max
f
max
Maximum Clock Frequency (Figure 1)
175
145
MHz
t
PLH
Propagation Delay, Clock to Q or Q (Figure 1)
2.0
10.0
1.5
11.0
ns
t
PHL
Propagation Delay, Clock to Q or Q (Figure 1)
2.0
11.0
1.5
12.0
ns
t
PHL
, t
PLH
Propagation Delay, Reset to Q or Q (Figure 2)
2.0
9.5
1.5
10.5
ns
C
IN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25
C,V
CC
=5.0 V
C
PD
Power Dissipation Capacitance
45
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
10%, C
L
=50pF,Input t
r
=t
f
=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25
C
-40
C to 85
C
Unit
t
su
(H)
(L)
Minimum Setup Time, Data to Clock (Figure 3)
2.0
2.5
2.0
2.5
ns
t
h
Minimum Hold Time, Clock to Data (Figure 3)
1.0
1.0
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
3.0
4.0
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
3.0
3.5
ns
t
rec
Minimum Recovery Time, Reset to Clock
(Figure 2)
0
0
ns
IN74ACT175
273
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
EXPANDED LOGIC DIAGRAM
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