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Электронный компонент: IN74HC21A

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TECHNICAL DATA
1
INTEGRAL
Dual 4-Input AND Gate
The IN74HC21A is high-speed Si-gate CMOS device and is pin
compatible with pullup resistors with low power Schottky TTL
(LSTTL). The device provide the Dual 4-input AND function.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN ASSIGNMENT
IN74HC21A
ORDERING INFORMATION
IN74HC21AN
Plastic
IN74HC21AD
SOIC
IZ74HC21A Chip
T
A
= -55
to 125
C for all packages
PIN 14 =V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs
Output
A
B
D
Y
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
X = don't care
A1
C1
Y1
B1
A2
C2
D2
Y2
B2
1
2
3
5
4
6
7
V CC
14
13
12
11
10
8
9
GND
A1
B1
B2
A2
Y2
Y1
C1
C2
D2
D1
IN74HC21A
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/
C from 65
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns


This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IN74HC21A
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low -Level
Input Voltage
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IN
=V
IH
or V
IL
I
OUT
= -50
A
2.0
3.0
4.5
6.0
1.92
2.92
4.42
5.92
1.9
2.9
4.4
5.9
1.9
2.9
4.4
5.9
V
IN
=V
IH
or V
IL
I
OUT
= -2.4 m
3.0
2.48
2.34
2.2
V
IN
=V
IH
or V
IL
I
OUT
= -4 m
4.5
3.98
3.84
3.7
V
OH
Minimum High-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
= -5.2 m
6.0
5.48
5.34
5.2
V
V
IN
= V
IH
or V
IL
I
OUT
= 50
A
2.0
3.0
4.5
6.0
0.09
0.09
0.09
0.09
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
=V
IH
or V
IL
I
OUT
= 2.4 m
3.0
0.26
0.33
0.4
V
IN
=V
IH
or V
IL
I
OUT
= 4 m
4.5
0.26
0.33
0.4
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
= 5.2 m
6.0
0.26
0.33
0.4
V
I
IL
Maximum Low-Level
Input Leakage Current
V
IN
= 0 V
6.0
-0.1
-1.0
-1.0
A
I
IH
Maximum High-Level
Input Leakage Current
V
IN
= V
CC
6.0
0.1
1.0
1.0
A
I
CC
Maximum Quiescent
Supply Current
V
IN
=V
CC
or 0 V
6.0
4.0
40
160
A
IN74HC21A
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
C to
-55
C
85
C
125
C
Unit
t
PHL
, t
PLH
Maximum Propagation Delay (Figure 1)
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
t
THL
, t
TLH
Maximum Output Transition Time
(Figure 1)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
5.0
10
10
10
pF
Power Dissipation Capacitance (Per Gate)
T
A
=25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
50
pF
Figure 1. Switching Waveforms
Figure 2. Test Circuit
0.1
0.1
0.9
0.9
V
2
V
2
V
1
t
PHL
t
HL
t
PLH
t
LH
GND
V
2
V
2
V = 0.5 V
1
CC
Input
Output
0.1
0.1
0.9
0.9
t
THL
t
TLH
0 V
V
CC
PULSE
GENERATOR
DEVICE
UNDER
TEST
V
CC
V
I
V
O
C
50 pF
L
R
T
Termination resistance R
T
- should
be equal to Z
OUT
of pulse
generators
IN74HC21A
5
INTEGRAL
CHIP PAD DIAGRAM IZ74HC21A
Pad size 0.108 x 0.108 mm (Pad size is given as per passivation layer)
Thickness of chip 0.46
0,02 mm
PAD LOCATION
Pad No
Symbol
X
Y
01
1
1.1165
0.3160
02
B1
0.2405
0.1150
03
-
0.5105
0.1020
04
C1
0.6925
0.1150
05
D1
1.0065
0.1400
06
Y1
1.0065
0.3160
07
GND
1.0065
0.4840
08
Y2
1.0065
0.7040
09
A2
1.0065
0.8800
10
B2
0.6925
0.9050
11
-
0.5105
0.9180
12
C2
0.2405
0.9050
13
D2
0.1165
0.6960
14
Vcc
0.1165
0.5360
Chip marking
IN74HC21
(x=1.009; y=0.727)
1
.
1
2
0
.
0
3
1.22 0.03
01
02
03
04
05
06
07
08
09
10
11
12
13
14