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Электронный компонент: IN74HC4060AN

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IN74HC4060A
14 STAGE BINARY
COUNTER/OSCILLATOR
IN74HC4060A
The IN74HC4060A is an high speed CMOS 14-STAGE BINARY
COUNTER/OSCILLATOR fabricated with silicon gate C
2
MOS
technology. The oscillator configuration allows design of either RC or
crystal oscillator circuits. A high level on the CLEAR accomplishes the
reset function, i.e. all counter outputs are made low and the oscillator is
ORDERING INFORMATION
IN74HC4060AN Plastic
IN74HC4060ADW SOIC
T
A
= -55
to 125 C for all packages
disabled.
A negative transition on the clock input increments the counter. Ten kinds
of divided output are provided; 4 to 10 and 12 to 14 stage inclusive. The
maximum division available at Q12 is 1/16384 f oscillator.
The Clock Input (
I
) and the CLEAR input are equipped with protection
circuits against static discharge and transient excess voltage.
.
o
LOW POWER DISSIPATION:
I
CC
=4
A(MAX.) at T
A
=25C
o
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN)
o
BALANCED PROPAGATION DELAYS:
t
PLH
= t
PHL
o
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2 V to 6 V
PIN DESCRIPTION
PIN ASSIGNMENT
O
I
O
CLEAR
PIN No
SYMBOL
NAME AND FUNCTION
01, 02, 03
Q12 to Q14
Counter Outputs
07, 05, 04, 06, 14,
13, 15
Q4 to Q10
Counter Outputs
09
O
External Capacitor Connection
10
O
External Resistor Connection
11
I
Clock Input / Oscillator
12 CLEAR
Master
Reset
08 GND
Ground
(0V)
16 V
CC
Positive Supply Voltage

INPUT AND OUTPUT EQUIVALENT CIRCUIT
INPUT
GND
GND
OUTPUT
V
CC
V
CC
1
IN74HC4060A
TRUTH TABLE
I
CLEAR
FUNCTION
X H
COUNTER IS RESET TO ZERO STATE
O OUTPUT GOES TO HIGH LEVEL
O
OUTPUT GOES TO LOW LEVEL
L
COUNT UP ONE STEP
L
NO
CHANGE
X : Don't Care




LOGIC DIAGRAM
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
R
R
R
12
11
O
O
I
10
9
CLEAR
R
R
R
R
R
R
R
R
R
R
R
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
D
D
D
D
D
D
D
D
D
D
D
D
D
D
3
15
1
14
2
13
6
4
5
7
Q14
Q10
Q12
Q8
Q13
Q9
Q7
Q6
Q5
Q4

This logic diagram has not be used to estimate propagation delays
2
IN74HC4060A
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
Tstg
Storage Temperature
-65 to +150
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation
under these conditions is not implied
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
Value
Unit
V
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
OP
Operating Temperature
-55 to +125
C
V
CC
= 2.0 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
ns
t
r
, t
f
Input Rise and Fall Time
V
CC
= 6.0 V
0 to 400
ns
3
IN74HC4060A
DC ELECTRICAL CHARACTERISTICS
Test Condition
Value
T
A
= 25
C
-55
C to 125C
Symbol
Parameter
V
CC
(V)
Min Max Min Max
Unit
2.0
1.5 1.5
4.5
3.15 3.15
V
IH
High Level Input
Voltage
6.0
4.2 4.2
V
2.0
0.5 0.5
4.5
1.35 1.35
V
IL
Low Level Input
Voltage
6.0
1.8 1.8
V
2.0
I
O
= -20
A
1.9 1.9
4.5
I
O
= -20
A
4.4 4.4
6.0
I
O
= -20
A
5.9 5.9
4.5
I
O
= -4.0
A
4.18 4.10
V
OH
High Level Output
Voltage
(Q Output)
6.0
I
O
= -5.2
A
5.68 5.60
V
2.0
I
O
= 20
A
0.1 0.1
4.5
I
O
= 20
A
0.1 0.1
6.0
I
O
= 20
A
0.1 0.1
4.5
I
O
= 4.0
A
0.26 0.40
V
OL
Low Level Output
Voltage
(Q Output)
6.0
I
O
= 5.2
A
0.26 0.40
V
2.0
I
O
= -20
A
1.8 1.8
4.5
I
O
= -20
A
4.4 4.0
V
OH
High Level Output
Voltage
(
O,
O
Output)
6.0
I
O
= -20
A
5.5 5.5
V
2.0
I
O
= 20
A
0.2 0.2
4.5
I
O
= 20
A
0.5 0.5
V
OL
Low Level Output
Voltage
(
O,
O
Output)
6.0
I
O
= 20
A
0.5 0.5
V
I
I
Input Leakage Current
6.0
V
I
= V
CC
or GND
0.1
1
A
I
CC
Quiescent Supply
Current
6.0 V
I
= V
CC
or GND
4
80
A
4
IN74HC4060A
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Test Condition
Value
T
A
= 25
C
-55
C to 125C
Symbol
Parameter
V
CC
(V)
Min Max Min Max
Unit
2.0
75
110
4.5
15 22
t
TLH
, t
THL
Output Transition
Time
6.0
13 19
ns
2.0
300 450
4.5
60 90
t
PLH
, t
PHL
Propagation Delay
Time
(
I-Q4
)
6.0
51 76
ns
2.0
75
110
4.5
15 22
t
PD
Propagation Delay
Time Difference
(Qn - Qn+1)
6.0
13 19
ns
2.0
195 295
4.5
39 59
t
PHL
Propagation Delay
Time
(CLEAR - Qn)
6.0
33 50
ns
2.0
6 4
4.5
30 20
f
MAX
Maximum Clock
Frequency
6.0
35 24
MHz
2.0
75
110
4.5
15 22
t
W(H)
,
t
W(L)
Minimum Pulse Width
(
I
)
6.0
13 19
ns
2.0
75
110
4.5
15 22
t
W(H)
Minimum Pulse Width
(CLEAR)
6.0
13 19
ns
2.0
100 150
4.5
20 30
t
REM
Minimum Removal
Time
6.0
17 26
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
A
= 25
C
-55
C to 125C
Symbol
Parameter
V
CC
(V)
Min Max Min Max
Unit
C
IN
Input
Capacitance 5.0
10 10
pF
5