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Электронный компонент: IN74HC652

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IN74HC652
1
O
CTAL
3-S
TATE
B
US
T
RANSCEIVERS
AND
D
F
LIP
-F
LOPS
High-Performance Silicon-Gate CMOS
The IN74HC652 is identical in pinout to the LS/ALS652. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
These devices consists of bus transceiver circuits, D-type flip-
flop, and control circuitry arranged for multiplex transmission of
data directly from the data bus or from the internal storage
registers. Direction and Output Enable are provided to select the
read-time or stored data function. Data on the A or B Data bus,
or both, can be stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (A-to-B Clock or B-to-A
Clock) regardless of the select or enable or enable control pins.
When A-to-B Source and B-to-A Source are in the real-time
transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simulta-neously enabling Direction
and Output Enable. In this configuration each output reinforces
its input. Thus, when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will remain at
its last state.
The IN74HC652 has noninverted outputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC651N Plastic
IN74HC651DW SOIC
T
A
= -55
to 125 C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 24=V
CC
PIN 12 = GND
IN74HC652
2
MAXIMUM RATINGS
*
Symbol Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
20
mA
I
OUT
DC Output Current, per Pin
35
mA
I
CC
DC Supply Current, V
CC
and GND Pins
75
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10
Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
C from 65 to 125C
SOIC Package: : - 7 mW/
C from 65 to 125C

RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C
t
r
, t
f
Input Rise and Fall Time
(Figures2,3)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
0
0
0
1000
500
400
ns


This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND
(V
IN
or V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open. I/O pins must be connected to a properly terminated line
or bus.
IN74HC652
3
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
V
CC
Guaranteed
Limit
Symbol Parameter
Test
Conditions
V 25
C
to
-55
C
85
C
125
C
Unit
V
IH
Minimum
High-
Level Input
Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20 A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low -
Level Input
Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
20 A
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
OH
Minimum
High-
Level Output
Voltage
V
IN
=V
IH
or V
IL
I
OUT
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
I
OUT
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
V
OL
Maximum
Low-
Level Output
Voltage
V
IN
= V
IL
or V
IH
I
OUT
20 A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
=V
IH
or V
IL
I
OUT
6.0 mA
I
OUT
7.8 mA)
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
I
IN
Maximum
Input
Leakage Current
V
IN
=V
CC
or GND
(Pins 1,2,3,21,22,and
23)
6.0
0.1
1.0
1.0
A
I
OZ
Maximum
Three-
State Leakage
Current
Output in High-
Impedance State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND,
I/O Pins
6.0
0.5
5.0
10
A
I
CC
Maximum
Quiescent Supply
Current
(per Package)
V
IN
=V
CC
or GND
I
OUT
=0
A
6.0 8.0 80 160
A
IN74HC652
4
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol Parameter V
25
C
to
-55
C
85C 125
C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to
Output B (or Input B to Output A)
(Figures 2,3 and 9)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, A-to-B
Clock to Output B (or B-to-A Clock to
Output A)
(Figures 1 and 9)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, A-to-B
Source to Output B (or B-to-A Source to
Output A) (Figures 4 and 9)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay , Direction
or Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
170
34
29
215
43
37
255
51
43
ns
t
PZL
,
t
PZH
Maximum Propagation Delay , Direction
or Output Enable to Output A or B
(Figures 5,6 and 10)
2.0
4.5
6.0
180
36
31
225
45
38
270
54
46
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any
Output
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State I/O Capacitance
(Output in High-Impedance State
- 15 15 15 pF
Power Dissipation Capacitance (Per
Channel)
Typical @25
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic
power consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
60 pF
IN74HC652
5
TIMING REQUIREMENTS(Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed
Limit
Symbol Parameter V
25
C to-
55
C
85C 125C
Unit
t
su
Minimum Setup Time, Input A
to
A-to-B Clock (or Input B to B-
to-A Clock) (Figure 7)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, A-to-B
Clock to Input A (or B-to-A
Clock to
Input B) (Figure 7)
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
t
w
Minimum Pulse Width, A-to-B
Clock (or B-to-A Clock)
(Figure 7)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
t
r
, t
f
Maximum Input Rise and Fall
Times (Figures 2 and 3)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns


TIMING DIAGRAM