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Электронный компонент: IN74LV573N

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IN74LV573
1
O
CTAL
D-T
YPE
T
RANSPARENT
L
ATCH
(3-S
TATE
)
By pinning IN74LV573 are compatible with IN74HC573A and
IN74HCT573A series. Input voltage levels are compatible with
stadard CMOS levels.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Voltage supply range from 1.2 to 5.5 V
LOW input current: 1.0 ; 0.1 at = 25
Output current 8 m
Latch current: not less than150 m at = 125
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM






FUNCTION TABLE
Inputs Outputs
OE LE
D
Q
L H H H
L H L L
L L X no
change
H X X Z
H -HIGH voltage level
L - LOW voltage level
X - don't care
Z - High impedance state

ORDERING INFORMATION
IN74LV573N Plastic DIP
IN74LV573D SOIC
T
A
= -40
to 125 C
for all packages
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
9
10
V
CC
20
18
17
16
15
14
19
11
12
13
GND
OE
D0
D1
D2
Q1
Q0
Q2
D3
D4
D5
D6
Q3
Q4
Q5
Q6
Q7
LE
D7
IN74LV573
2

ABSOLUTE MAXIMUM RATINGS
Symb
ol
Parameter Rating
Uni
t
Conditions
Vcc
Supply voltage
-0.5 to +7.0
V
Iik,
Input diode current
20
mA V
I
<-0.5 V
or
V
I
>Vcc>+0.5 V
Iok
Output diode current
50
mA V
0
<-0.5 V
or
V
I
>Vcc>+0.5 V
Io
Output current bus drivers
35
mA -0.5 V<Vo<Vcc+0.5 V
Icc
DC Vcc or GND current for
types
bus driver outputs
70
mA
I
GND
GND
current
50
m
Tstg
Storage temperature range
-65 to +150
P
D
Power dissipation per package:
DIP
SO
750
500
mW
Notes:
Power dissipation value decreases for:
DIP - 12 mW
C the range from 70 to 125
SO - 8 mW
C the range from 70 to 125




RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min
Max
Unit
Conditions
Vcc Supply
voltage
1.0
5.5 V
VI Input
voltage
0
Vcc
V
V Output
voltage
0
Vcc
V
T
Operating temperature range
-40
+125
o
C
t
r
,t
f
Input rise and fall times
500
200
100
50
ns/V Vcc= 1.0
2.0
V
Vcc= 2.0
2.7
V
Vcc= 2.7
3.6
V
Vcc= 3.6
5.5 V
- The IC function down to V = 1.0 V (input levels - V
IL
=0 V, V
IH
=Vcc); DC characterisics
are guaranteed at Vcc=1.2
5.5 V.
IN74LV573
3
DC CHARACTERISTICS
Sym
Conditions
Limits
bol Parameter Vc
V
I
-40 to +25
C
+85
+125
Unit
(V)
Min Max Min Max Min Max
V
IH
HIGH level
input voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
0.9
1.4
2.0
0.7 Vcc
-
-
-
--
V
V
IL
LOW level
output
voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
V
V
OH
HIGH level
output
voltage
1.2
2.0
2.7
3.6
5.5
V
IH
or
V
IL
I
O
=-100
1.05
1.85
2.55
3.45
5.35
-
-
-
-
-
1.0
1.8
2.5
3.4
5.3
-
-
-
-
-
1.0
1.8
2.5
3.4
5.3
-
-
-
-
-
V
V
OH
HIGH level
output
voltage; BUS
driver
outputs
3.0
4.5
V
IH
or
V
IL
I
O
=-8 mA
I
O
=-16 mA
2.48
3.70
-
-
2.40
3.60
-
-
2.20
3.50
-
-
V
V
OL
LOW level
output
voltage
1.2
2.0
2.7
3.6
5.5
V
IH
or
V
IL
I
O
=100
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
V
V
OL
LOW level
voltage; BUS
driver
outputs
3.0
4.5
V
IH
or
V
IL
I
O
=8 mA
I
O
=16 mA
-
-
0.33
0.40
-
-
0.40
0.55
-
-
0.50
0.65
V
I
I
Input
leakage
current
5.5 V
or
GND
-
1.0
1.0
-
1.0
I
OZ
OFF-state
current
5.5 V
IH
or
V
IL
-
0.5
5.0
-
10.0
Icc Supply
current
5.5 V
or
GND
Io = 0
8.0
80
160
Icc Additional
supply
current per
input
2.7
3.6
V
I
= Vcc-0.6V
-
0.2
0.5
-
0.85
mA
IN74LV573
4

AC CHARACTERISICS
(C
L
=50 pF, R
L
=1 K
, t
LH
= t
HL
= 2.5 ns)
Sym Conditions
Limits
bol Parameter Vcc
-40 to +25
C
+85
C +125C
Unit
Min Max
Min Max Min Max
t
PHL/PLH
Propagation
delay Dn to
Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
150
30
23
18
15
-
-
-
-
-
160
39
29
23
19
-
-
-
-
-
170
49
36
29
24
ns
t
PHL/PLH
Propagation
delay LE to
Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
160
34
28
20
17
-
-
-
-
-
180
43
31
25
21
-
-
-
-
-
190
53
34
31
26
ns
t
PZH/PZL
3-state
output
enable time
OE to Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
140
28
22
17
14
-
-
-
-
-
160
37
28
22
18
-
-
-
-
-
170
48
35
28
23
ns
t
PHZ/PLZ
3-state
outpiut
disable time
OE to Qn
1.2
2.0
2.7
3.0
4.5
V
I
= Vcc or
GND
-
-
-
-
-
160
31
23
20
17
-
-
-
-
-
160
39
29
24
20
-
-
-
-
-
170
48
36
29
24
ns
t
W
LE pulse
width HIGH
1.2
2.0
2.7
3.0
4.5
100
29
21
17
15
-
-
-
-
-
125
34
25
20
18
-
-
-
-
-
150
41
30
24
21
-
-
-
-
-
ns
t
su
Setup
time
Dn to LE
1.2
2.0
2.7
3.0
4.5
50
15
11
8
6
-
-
-
-
-
75
17
13
10
8
-
-
-
-
-
100
20
15
12
10
-
-
-
-
-
ns
t
h
Hold
time
Dn
to LE
1.2
2.0
2.7
3.0
4.5
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
ns
C
I
Input
capacitance
5.0
=+25
7.0 - ns
C
PD
Power
dissipation
capacitance
per package
5.5
=+25
V
I
= Vcc or
GND
52 - ns
IN74LV573
5
Drawing of the chip
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1.9 mm
1.
51
mm
74LV573/574
On-chip marking
Pads allocation Table
coordinates (counted from lower left corner),
mm
Pad
number
X Y
Pad size, mm
01
0.128
0.545
0.108 x 0.108
02
0.128
0.229
0.108 x 0.108
03
0.330
0.120
0.108 x 0.108
04
0.576
0.120
0.108 x 0.108
05
0.738
0.120
0.108 x 0.108
06
1.054
0.120
0.108 x 0.108
07
1.216
0.120
0.108 x 0.108
08
1.466
0.120
0.108 x 0.108
09
1.682
0.314
0.108 x 0.108
10
1.682
0.533
0.108 x 0.108
11
1.682
0.839
0.108 x 0.108
12
1.682
1.108
0.108 x 0.108
13
1.422
1.274
0.108 x 0.108
14
1.149
1.274
0.108 x 0.108
15
0.971
1.274
0.108 x 0.108
16
0.811
1.274
0.108 x 0.108
17
0.633
1.274
0.108 x 0.108
18
0.360
1.274
0.108 x 0.108
19
0.128
1.108
0.108 x 0.108
20
0.128
0.854
0.108 x 0.108