TECHNICAL DATA
IN74LV86
Quad 2-Input Exclusive OR Gate
1
14
1
14
N SUFFIX
PLASTIC
D SUFFIX
SOIC
ORDERING INFORMATION
IN74LV86N Plastic
IN74LV86D SOIC
T
A
= -40
to 125 C for all
packages
The 74LV86 is a low-voltage Si-gate CMOS device and is pin
and
function compatible with the 74HC/HCT86.
The 74LV86 provides the 2-input EXCLUSIVE-OR function.
Output voltage levels are compatible with input levels of
CMOS, NMOS and TTL IC
S
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0
; 0.1 at = 25
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5V
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=V
CC
PIN 08 = GND
FUNCTION TABLE
Inputs Outputs
An Bn Yn
L H H
L L L
H L H
H H L
H= high level
L = low level
1
IN74LV86
MAXIMUM RATINGS
*
Symbol Parameter
Value
Unit
V
CC
DC supply voltage
-0.5 to +5.0
V
I
IK
*
1
Input diode current
20
mA
I
OK
*
2
Output diode current
50
mA
I
O
*
3
Output source or sink current
25
mA
I
CC
V
CC
current
50
mA
I
GND
GND current
50
mA
P
D
Power dissipation per package: *
4
Plastic DIP
SO
750
500
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm
(SO Package) from Case for 4 Seconds
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V.
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V.
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V.
*
4
Derating - Plastic DIP: - 12 mW/
C from 70 to 125C
SO Package: : - 8 mW/
C from 70 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min
Max
Unit
V
CC
DC Supply Voltage
1.2
5.5
V
V
I
DC Input Voltage
0
V
CC
V
V
O
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
-40
+125
C
t
r
, t
f
Input Rise and Fall Time (Figure 1)
1.0
V
CC
<2.0
2.0
V
CC
<2.7
2.7
V
CC
<3.6
3.6
V
CC
5.5
0
0
0
0
500
200
100
50
ns/V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
IN74LV86
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
V
CC
Guaranteed Limit
Symbol Parameter conditions V
-40
C to 25C
85
C
125
C
Unit
min
max
min
max
min
max
V
IH
HIGH level input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
V
V
IL
LOW level input
voltage
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
V
V
OH
HIGH level output
voltage
V
I
= V
IH
or V
IL
I
O
= -100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
V
V
I
= V
IH
or V
IL
I
O
= -6 m
3.0
2.48 - 2.34
- 2.20 - V
V
I
= V
IH
or V
IL
I
O
= -12 m
4.5
3.70 - 3.60
- 3.50 - V
V
OL
LOW level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
1.2
2.0
2.7
3.0
3.6
4.5
5.5
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
V
V
I
= V
IH
or V
IL
I
O
= 6 m
3.0
- 0.33
- 0.40 - 0.50
V
V
I
= V
IH
or V
IL
I
O
= 12 m
4.5
- 0.40
- 0.55 - 0.65
V
I
I
Input current
V
I
= V
CC
or 0 V
5.5
-
0.1
-
1.0
-
1.0
I
CC
Supply current
V
I
=V
CC
or 0 V
I
O
= 0
5.5
- 4.0 - 20 - 40
I
CC1
Additional
quiescent supply
current per input
V
I
=V
CC
-
0.6 V
2.7
3.6
- 0.2
0.2
- 0.5
0.5
- 0.85
0.85
mA
3
IN74LV86
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, R
L
= 1 k
, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
Symbol Parameter conditions
V
-40
C to 25C
85
C
125
C
Unit
min
max
min
max
min
max
t
PHL,
t
PLH
Propagation delay ,
An ,Bn, to Yn
V
I
= 0 V or V
CC
Figure 1, 2
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
140
24
19
15
13
-
-
-
-
-
150
32
24
19
16
-
-
-
-
-
180
41
30
24
20
ns
C
I
Input capacitance
A
= 25
C
5.0
-
7.0 - - - - pF
C
PD
Power dissipation
capacitance (per gate)
V
I
= 0 V or V
CC
T
A
= 25
C
5.5
-
60 - - - - pF
90%
V
M
(1)
V
1
(2)
V
OL
V
OH
V
M
(1)
10%
t
t
t
t
f
r
PLH
PHL
GND
INPUT
A OR B
OUTPUT Y
Figure 1. Switching Waveforms
Note:
(1)
V
M
= 1.5 V at V
CC
= 2.7 V
V
M
= 0.5
V
CC
at V
CC
=1.2 V, 2.0 V, 3.0 V, 4.5 V
(2)
V
1
= V
CC
at V
CC
=1.2 V, 2.0 V, 2.7 V, 4.5 V
V
1
= 2.7 V at V
CC
= 3.0 V
DEVICE
UNDER
TEST
OUTPUT
C
L
*
R
L
TEST POINT
* Includes all probe and jig capacitance
Figure 4. Test Circuit
4
IN74LV86
N SUFFIX PLASTIC DIP
(MS - 001AA)
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
C
5.33
D
0.36
0.56
F
1.14
1.78
G
H
J
0
10
K
2.92
3.81
NOTES:
L
7.62
8.26
1.
Dimensions "A", "B" do not include mold flash or protrusions.
M
0.2
0.36
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
H
J
0
8
NOTES:
K
0.1
0.25
1.
Dimensions A and B do not include mold flash or protrusion.
M
0.19
0.25
2.
Maximum mold flash or protrusion 0.15 mm (0.006) per side
P
5.8
6.2
for A; for B 0.25 mm (0.010) per side.
R
0.25
0.5
Dimension, mm
1.27
5.27
2.54
7.62
Dimension, mm
A
B
H
C
K
C M
J
F
M
P
G
D
R x 45
SEATING
PLANE
0.25 (0.010) M T
-T-
1
14
7
8
A
B
F
G
D
L
H
SEATING
PLANE
N
K
0.25 (0.010) M T
M
J
-T-
C
1
14
7
8
5
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