IN90S2323D, IN90LS2323D
1
8-
BIT
M
ICROCONTROLLER WITH
2K
BYTES
B
UILD
-
IN
P
ROGRAMMABLE
F
LASH
Description
The IN90S2323D and IN90LS2323D is a low-power
CMOS 8-bit microcontrollers based on the AVR
enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the IN90S2323D and
IN90LS2323D achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power
consumption versus processing speed.
The AVR core combines a rich instruction set with
32 general purpose working registers. All the 32 registers
are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The
resulting architecture is more code efficient while
achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
1
8
Features
Utilizes the AVR
Enhanced RISC Architecture
AVR - High Performance and Low Power RISC Architecture
118 Powerful Instructions - Most Single Clock Cycle Execution
2K bytes of In-System Programmable ISP Flash
- SPI Serial Interface for In-System Programming
- Endurance: 1,000 Write/Erase Cycles
128 bytes EEPROM
- Endurance: 100,000 Write/Erase Cycles
128 bytes Internal RAM
32 x 8 General Purpose Working Registers
- 3 Programmable I/O Lines
V
CC
: 4.0 - 6.0V IN90S2323D
V
CC
: 2.7 - 6.0V IN90LS2323D
Power-On Reset Circuit
Speed Grades: 0 - 10 MHz IN90S2323D
Speed Grades: 0 - 4 MHz IN90LS2323D
Up to 10 MIPS Throughput at 10 MHz
One 8-Bit Timer/Counter with Separate Prescaler
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
Low Power Idle and Power Down Modes
Programming Lock for Flash Program and EEPROM Data Security
Selectable On-Chip RC Oscillator
8-Pin
Device
IN90S2323D, IN90LS2323D
3
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB2..PB0)
Port B is a 3-bit bi-directional I/O port. Port pins can provide
internal pull-up resistors (selected for each bit).
RESET
Reset input. A low on this pin for two machine cycles while the
oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Clock Sources
The IN90S2313D and IN90LS2313D contains an inverting amplifier which can be configured for use as
an on-chip oscillator. XTAL1 and XTAL2 are input and output respectively. Either a quartz crystal or a
ceramic resonator may be used.
Oscillator Connection
External Clock Drive Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit)
operation is executed. Two operands are output from the register file, the operation is executed, and the
result is stored back in the register file -in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space
addressing-enabling efficient address calculations. One of the three address pointers is also used as the
address pointer for the constant table look up function. These added function registers are the 16-bit X-
IN90S2323D, IN90LS2323D
4
register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or
between a constant and a register. Single register operations are also executed in the ALU. In addition to
the register operation, the conventional memory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses
($00 -$1F), allowing them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
Timer/Counters, A/D-converters, and other I/O functions. The I/O memory can be accessed directly, or as
the Data Space locations following those of the register file, $20 - $5F.
The AVR has Harvard architecture - with separate memories and buses for program and data. The
program memory is accessed with a two stage pipeline. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be executed in
every clock cycle. The program memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR
instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit
instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack.
The stack is effectively allocated in the general data SRAM, and consequently the stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
reset routine (before subroutines or interrupts are executed). The 8-bit stack pointer SP is read/write
accessible in the I/O space.
The 128 bytes data SRAM + register file and I/O registers can be easily accessed through the five
different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
AVR Architecture
PDF 
ZIP
