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Электронный компонент: IW4027BD

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TECHNICAL DATA
1
INTEGRAL
Dual JK Flip-Flop
The IW4027B is a Dual JK Flip-Flop which is edge-triggered and
features independent Set, Reset, and Clock inputs. Data is accepted
when the Clock is LOW and transferred to the output on the positive-
going edge of the Clock. The active HIGH asynchronous Reset and Set
are independent and override the J, K, or Clock inputs. The outputs are
buffered for best system performance.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
A at 18 V over full package-
temperature range; 100 nA at 18 V and 25
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4027B
ORDERING INFORMATION
IW4027BN Plastic
IW4027BD SOIC
IZ4027B Chip
T
A
= -55
to 125
C for all packages
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J
K
Q
n+1
Q
n+1
L
H
X
X
X
L
H
H
L
X
X
X
H
L
H
H
X
X
X
H
H
L
L
L
L
No change
L
L
H
L
H
L
L
L
L
H
L
H
L
L
H
H
Qn
Qn
X = don't care
Qn+1 = State After Clock Positive Transition
IW4027B
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
10
mA
P
D
Power Dissipation in Still Air, Plastic DIP, SOIC
Package
500**
mW
P
tot
Power Dissipation per Output Transistor
100
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating: - Plastic DIP from -55 to +100
C
- SOIC Package from -55 to +65
C
- Plastic DIP: - 10 mW/
C from +100 to +125
C
- SOIC Package: : - 7 mW/
C from +65 to +125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
3.0
18
V
V
IN
DC Input Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C


This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation V
IN
should be constrained to the range
GND
V
IN
V
CC
.
Unused inputs mu st always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IW4027B
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
-55
C
25
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.5 V or V
CC
- 0.5 V
V
OUT
=1.0 V or V
CC
- 1.0 V
V
OUT
=1.5 V or V
CC
- 1.5 V
5.0
10
15
3.5
7
11
3.5
7
11
3.5
7
11
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.5 V or V
CC
- 0.5 V
V
OUT
=1.0 V or V
CC
- 1.0 V
V
OUT
=1.5 V or V
CC
- 1.5 V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
V
OH
Minimum High-Level
Output Voltage
V
IN
=GND or V
CC
V
IL
=1.5V, V
IH
=3.5V, I
O
=-1A
V
IL
=3.0V, V
IH
=7.0V, I
O
=-1A
V
IL
=4.0V, V
IH
=11V, I
O
=-1A
5.0
10
15
5.0
10
15
4.95
9.95
14.95
4.5
9.0
13.5
4.95
9.95
14.95
4.5
9.0
13.5
4.95
9.95
14.95
4.5
9.0
13.5
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=GND or V
CC
V
IL
=1.5V, V
IH
=3.5V, I
O
=1A
V
IL
=3.0V, V
IH
=7.0V, I
O
=1A
V
IL
=4.0V, V
IH
=11V, I
O
=1A
5.0
10
15
5.0
10
15
0.05
0.05
0.05
0.5
1.0
1.5
0.05
0.05
0.05
0.5
1.0
1.5
0.05
0.05
0.05
0.5
1.0
1.5
V
I
IN
Maximum Input
Leakage Current
V
IN
= GND or V
CC
18
0.1
0.1
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
= GND or V
CC
5.0
10
15
20
1.0
2.0
4.0
20
1.0
2.0
4.0
20
30
60
120
600
A
I
OL
Minimum Output Low
(Sink) Current
V
IN
= GND or V
CC
V
OL
=0.4 V
V
OL
=0.5 V
V
OL
=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
I
OH
Minimum Output High
(Source) Current
V
IN
= GND or V
CC
V
OH
=4.6 V
V
OH
=2.5 V
V
OH
=9.5 V
V
OH
=13.5 V
5.0
5.0
10
15
-0.64
-2.0
-1.6
-4.2
-0.51
-1.6
-1.3
-3.4
-0.36
-1.15
-0.9
-2.4
mA
IW4027B
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
f
max
Maximum Clock Frequency
5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
t
PLH
Maximum Propagation Delay, Set to Q or Reset
to Q
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
t
PHL
Maximum Propagation Delay, Set to Q or Reset
to Q
5.0
10
15
400
170
120
400
170
120
800
340
240
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
C
IN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
t
w
Minimum Pulse Width, Clock
5.0
10
15
140
60
40
140
60
40
280
120
80
ns
t
w
Minimum Pulse Width, Set or Reset
5.0
10
15
180
80
50
180
80
50
360
160
100
ns
t
su
Minimum Data Setup Time
5.0
10
15
200
75
50
200
75
50
400
150
100
ns
t
r
, t
f
Maximum Input Rise or Fall Time, Clock
5.0
10
15
45
5
2
45
5
2
90
10
4
s
IW4027B
5
INTEGRAL




















































Figure 1. Switching Waveforms
V
CC
0.5
0.5
0.1
0.1
0.9
0.9
0.5
0.5
0.5V
CC
t
REM
t
PHL
(t
PLH
)
V
CC
V
CC
V
OL
V
OHCC
0 V
0 V
0 V
t
SU
t
W
t
HL
t
LH
SET
(RESET)
Q(Q)
CLOCK
K(J)
U
OL
V
CC
0.5V
CC
0.1
0.9
0.5
t
PHL
(t
PLH
)
V
CC
U
DD
V
OHCC
0 V
0 V
t
W2

Auoia nQ(nQ)

SET
(RESET)

Q(Q)
RESET
(SET)
t
THL
(t
TLH
)
0 V