ChipFind - документация

Электронный компонент: IW4040BD

Скачать:  PDF   ZIP
TECHNICAL DATA
1
INTEGRAL
12-Stage Binary Ripple Counter
High-Voltage Silicon-Gate CMOS
The IW4040B is ripple-carry binary counter. All counter stages are
master-slave flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the RESET line resets
the counter to its all zeros state. Schmitt trigger action on the input-pulse
line permits unlimited rise and fall times.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
A at 18 V over full package-temperature
range; 100 nA at 18 V and 25
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
IW4040B
N SUFFIX
PLASTIC DIP
1
16
1
16
ORDERING INFORMATION
IW4040BN Plastic DIP
IW4040BD SOIC
IZ4040B
chip
T
A
= -55
to 125
C
for all packages
FUNCTION TABLE
Inputs
Output
Clock
Reset
Output state
L
No change
L
Advance to next
state
X
H
All Outputs are low
H= high level
L = low level
X=don't care
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
10
9
7
6
5
3
2
4
13
12
14
11
15
1
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
1
2
3
5
4
6
7
8
16
15
14
13
12
11
10
9
GND
V CC
Q12
Q6
Q5
Q7
Q4
Q3
Q2
Q10
Q8
Q9
RESET
CLOCK
Q1
Q11
IW4040B
2
INTEGRAL
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +20
V
V
IN
DC Input Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
10
mA
P
D
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
500*
1
mW
P
tot
Power Dissipation per Output Transistor
100
mW
Tstg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
For T
A
=-55 to 100
C (package plastic DIP), for T
A
=-55 to 65
C (package SOIC)
+Derating - Plastic DIP: - 12 mW/
C from 100
to 125
C
SOIC Package: : - 7 mW/
C from 65
to 125
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
3.0
18
V
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
-55
+125
C


This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND
(V
IN
or
V
OUT
)
V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
IW4040B
3
INTEGRAL
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
-55
C
25
C
125
C
Unit
V
IH
Minimum High-Level
Input Voltage
V
OUT
=0.5 V or V
CC
- 0.5 V
V
OUT
=1.0 V or V
CC
- 1.0 V
V
OUT
=1.5 V or V
CC
- 1.5 V
5.0
10
15
3.5
7.0
11.0
3.5
7.0
11.0
3.5
7.0
11.0
V
V
IL
Maximum Low -Level
Input Voltage
V
OUT
=0.5 V or V
CC
- 0.5 V
V
OUT
=1.0 V or V
CC
- 1.0 V
V
OUT
=1.5 V or V
CC
- 1.5 V
5.0
10
15
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
OH
Minimum High-Level
Output Voltage
V
IN
= GND or V
CC
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
4.95
9.95
14.95
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
= GND or V
CC
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
I
IN
Maximum Input Leakage
Current
V
IN
= GND or V
CC
18
0.1
0.1
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
IN
= GND or V
CC
5.0
10
15
20
5
10
20
100
5
10
20
100
150
300
600
3000
A
I
OL
Minimum Output Low
(Sink) Current
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
mA
I
OH
Minimum Output High
(Source) Current
V
IN
= GND or V
CC
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
5.0
5.0
10
15
-2.0
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
IW4040B
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, R
L
=200 k
, t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
f
max
Maximum Clock Frequency (Figure 1)
5.0
10
15
3.5
8
12
3.5
8
12
1.75
4.0
6.0
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q1 (Figure 1)
5.0
10
15
360
160
130
360
160
130
720
320
260
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Q
n
to Q
n+1
(Figure 2)
5.0
10
15
330
80
60
330
80
60
660
160
120
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figure 3)
5.0
10
15
280
120
100
280
120
100
560
240
200
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
C
IN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS
(C
L
=50 pF, R
L
=200 k
, t
r
=t
f
=20 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
-55
C
25
C
125
C
Unit
t
w
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
140
60
40
140
60
40
280
120
80
ns
t
w
Minimum Pulse Width, Reset (Figure 3)
5.0
10
15
200
80
60
200
80
60
400
160
120
ns
t
rem
Minimum Removal Time, Reset(Figure 3)
5.0
10
15
350
150
100
350
150
100
700
300
200
ns
t
r,
t
f
Maximum Input Rise and Fall Times, Clock (Figure 1)
5.0
10
15
Unlimited
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
IW4040B
5
INTEGRAL
50%
50%
50%
t
t
w
rem
t
PHL
V
V
V
CC
CC
CC
GND
GND
GND
RESET
CLOCK
ANY Q
Figure 3. Switching Waveforms

TIMING DIAGRAM

EXPANDED LOGIC DIAGRAM
Clock
Reset
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
1
0
2
4
8
16
32
64
128
256
512
1024
2048
4096
CLOCK
RESET
Q1
CL1
CL1
FF1
Q1
Q1
Q1
R
CL2
CL2
FF2
Q2
Q2
R
CL7
CL7
FFI2
Q12
Q12
R
CL3
Q11
CL3
Q11
FF3-FF11
Q3
Q2
Q11
Q12