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Электронный компонент: 21150

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21150 PCI-to-PCI Bridge
Preliminary
Datasheet
Product Features
1.
For 21150-AB and later revisions only. The 21150-AA does not implement this feature.
s
Complies fully with the PCI Local Bus
Specification, Revision 2.1
s
Complies fully with the Advanced
Configuration Power Interface (ACPI)
Specification
s
Complies fully with the PCI Power
Management Specification, Revision 1.0
1
s
Complies fully with Revision 1.0 of the
PCI-to-PCI Bridge Architecture
Specification
s
Implements delayed transactions for all PCI
configuration, I/O, and memory read
commands--up to three transactions
simultaneously in each direction
s
Allows 88 bytes of buffering (data and
address) for posted memory write
commands in each direction--up to five
posted write transactions simultaneously in
each direction
s
Allows 72 bytes of read data buffering in
each direction
s
Provides concurrent primary and secondary
bus operation, to isolate traffic
s
Provides 10 secondary clock outputs with
the following features:
-- Low skew permits direct drive of option
slots
-- Individual clock disables, capable of
automatic configuration during reset
s
Provides arbitration support for nine
secondary bus devices:
-- A programmable 2-level arbiter
-- Hardware disable control, to permit use
of an external arbiter
s
Provides a 4-pin general-purpose I/O
interface, accessible through device-
specific configuration space
s
Provides enhanced address decoding:
-- A 32-bit I/O address range
-- A 32-bit memory-mapped I/O address
range
-- A 64-bit prefetchable memory address
range
-- ISA-aware mode for legacy support in
the first 64KB of I/O address range
-- VGA addressing and VGA palette
snooping support
s
Includes live insertion support
s
Supports PCI transaction forwarding for the
following commands:
-- All I/O and memory commands
-- Type 1 to Type 1 configuration
commands
-- Type 1 to Type 0 configuration
commands (downstream only)
-- All Type 1 to special cycle
configuration commands
s
Includes downstream lock support
s
Supports both 5-V and 3.3-V signaling
environments
s
Available in both 33 MHz and 66 MHz
versions
s
Provides an IEEE standard 1149.1 JTAG
interface.
Order Number: 278106-002
July 1998
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Preliminary
Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 21150 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Preliminary
Datasheet
iii
21150
Contents
1.0
Introduction......................................................................................................................... 1
1.1
Architecture ........................................................................................................... 3
1.2
Data Path .............................................................................................................. 5
1.3
Posted Write Queue .............................................................................................. 6
1.4
Delayed Transaction Queue.................................................................................. 6
1.5
Read Data Queue ................................................................................................. 6
2.0
Signal Pins ......................................................................................................................... 7
2.1
Primary PCI Bus Interface Signals ........................................................................ 8
2.2
Secondary PCI Bus Interface Signals .................................................................11
2.3
Secondary Bus Arbitration Signals......................................................................13
2.4
General-Purpose I/O Interface Signals ...............................................................14
2.5
Clock Signals.......................................................................................................14
2.6
Reset Signals ......................................................................................................15
2.7
Miscellaneous Signals.........................................................................................16
2.8
JTAG Signals ......................................................................................................17
3.0
Pin Assignments...............................................................................................................19
3.1
Numeric Pin Assignment .....................................................................................20
3.2
Alphabetic Pin Assignment..................................................................................24
4.0
PCI Bus Operation ...........................................................................................................27
4.1
Types of Transactions .........................................................................................27
4.2
Address Phase ....................................................................................................28
4.2.1
Single Address Phase ............................................................................28
4.2.2
Dual Address Phase...............................................................................28
4.3
Device Select (DEVSEL#) Generation ................................................................29
4.4
Data Phase..........................................................................................................29
4.5
Write Transactions ..............................................................................................29
4.5.1
Posted Write Transactions .....................................................................30
4.5.2
Memory Write and Invalidate Transactions ............................................32
4.5.3
Delayed Write Transactions ...................................................................32
4.5.4
Write Transaction Address Boundaries ..................................................34
4.5.5
Buffering Multiple Write Transactions.....................................................35
4.5.6
Fast Back-to-Back Write Transactions ...................................................35
4.6
Read Transactions ..............................................................................................36
4.6.1
Prefetchable Read Transactions ............................................................37
4.6.2
Nonprefetchable Read Transactions......................................................37
4.6.3
Read Prefetch Address Boundaries .......................................................38
4.6.4
Delayed Read Requests ........................................................................38
4.6.5
Delayed Read Completion with Target...................................................39
4.6.6
Delayed Read Completion on Initiator Bus ............................................39
4.7
Configuration Transactions .................................................................................42
4.7.1
Type 0 Access to the 21150 ...................................................................43
4.7.2
Type 1 to Type 0 Translation..................................................................44
4.7.3
Type 1 to Type 1 Forwarding .................................................................45
4.7.4
Special Cycles ........................................................................................46
21150
iv
Preliminary
Datasheet
4.8
Transaction Termination ..................................................................................... 47
4.8.1
Master Termination Initiated by the 21150 ............................................. 47
4.8.2
Master Abort Received by the 21150 ..................................................... 48
4.8.3
Target Termination Received by the 21150 ........................................... 50
4.8.3.1 Delayed Write Target Termination Response ........................... 50
4.8.3.2 Posted Write Target Termination Response ............................. 51
4.8.3.3 Delayed Read Target Termination Response ........................... 51
4.8.4
Target Termination Initiated by the 21150 ............................................. 53
4.8.4.1 Target Retry .............................................................................. 53
4.8.4.2 Target Disconnect ..................................................................... 54
4.8.4.3 Target Abort .............................................................................. 54
5.0
Address Decoding............................................................................................................ 55
5.1
Address Ranges.................................................................................................. 55
5.2
I/O Address Decoding ......................................................................................... 55
5.2.1
I/O Base and Limit Address Registers ................................................... 56
5.2.2
ISA Mode ............................................................................................... 57
5.3
Memory Address Decoding ................................................................................. 58
5.3.1
Memory-Mapped I/O Base and Limit Address Registers ....................... 59
5.3.2
Prefetchable Memory Base and Limit Address Registers ...................... 60
5.3.3
Prefetchable Memory 64-Bit Addressing Registers................................ 61
5.4
VGA Support ....................................................................................................... 62
5.4.1
VGA Mode.............................................................................................. 62
5.4.2
VGA Snoop Mode .................................................................................. 63
6.0
Transaction Ordering ....................................................................................................... 65
6.1
Transactions Governed by Ordering Rules ......................................................... 65
6.2
General Ordering Guidelines .............................................................................. 66
6.3
Ordering Rules .................................................................................................... 66
6.4
Data Synchronization .......................................................................................... 68
7.0
Error Handling .................................................................................................................. 69
7.1
Address Parity Errors .......................................................................................... 69
7.2
Data Parity Errors................................................................................................ 70
7.2.1
Configuration Write Transactions to 21150 Configuration Space .......... 70
7.2.2
Read Transactions ................................................................................. 70
7.2.3
Delayed Write Transactions ................................................................... 71
7.2.4
Posted Write Transactions ..................................................................... 73
7.3
Data Parity Error Reporting Summary ................................................................ 74
7.4
System Error (SERR#) Reporting ....................................................................... 78
8.0
Exclusive Access ............................................................................................................. 81
8.1
Concurrent Locks ................................................................................................ 81
8.2
Acquiring Exclusive Access Across the 21150 ................................................... 81
8.3
Ending Exclusive Access .................................................................................... 82
9.0
PCI Bus Arbitration........................................................................................................... 85
9.1
Primary PCI Bus Arbitration ................................................................................ 85
9.2
Secondary PCI Bus Arbitration ........................................................................... 85
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter............................. 85
9.2.2
Secondary Bus Arbitration Using an External Arbiter............................. 87
Preliminary
Datasheet
v
21150
9.2.3
Bus Parking ............................................................................................87
10.0
General-Purpose I/O Interface .........................................................................................89
10.1
gpio Control Registers.........................................................................................89
10.2
Secondary Clock Control.....................................................................................90
10.3
Live Insertion .......................................................................................................92
11.0
Clocks...............................................................................................................................95
11.1
Primary and Secondary Clock Inputs ..................................................................95
11.2
Secondary Clock Outputs....................................................................................95
11.3
Disabling Unused Secondary Clock Outputs ......................................................96
12.0
66-Mhz Operation.............................................................................................................97
13.0
PCI Power Management ..................................................................................................99
14.0
Reset ..............................................................................................................................101
14.1
Primary Interface Reset.....................................................................................101
14.2
Secondary Interface Reset................................................................................101
14.3
Chip Reset.........................................................................................................102
15.0
Configuration Space Registers.......................................................................................103
15.1
PCI-to-PCI Bridge Standard Configuration Registers .......................................105
15.1.1 Vendor ID Register--Offset 00h...........................................................105
15.1.2 Device ID Register--Offset 02h ...........................................................105
15.1.3 Primary Command Register--Offset 04h .............................................105
15.1.4 Primary Status Register--Offset 06h ...................................................107
15.1.5 Revision ID Register--Offset 08h ........................................................109
15.1.6 Programming Interface Register--Offset 09h ......................................109
15.1.7 Subclass Code Register--Offset 0Ah ..................................................109
15.1.8 Base Class Code Register--Offset 0Bh...............................................109
15.1.9 Cache Line Size Register--Offset 0Ch ................................................110
15.1.10 Primary Latency Timer Register--Offset 0Dh ......................................110
15.1.11 Header Type Register--Offset 0Eh......................................................110
15.1.12 Primary Bus Number Register--Offset 18h .........................................111
15.1.13 Secondary Bus Number Register--Offset 19h.....................................111
15.1.14 Subordinate Bus Number Register--Offset 1Ah ..................................111
15.1.15 Secondary Latency Timer Register--Offset 1Bh .................................112
15.1.16 I/O Base Address Register--Offset 1Ch ..............................................112
15.1.17 I/O Limit Address Register--Offset 1Dh...............................................113
15.1.18 Secondary Status Register--Offset 1Eh ..............................................113
15.1.19 Memory Base Address Register--Offset 20h ......................................115
15.1.20 Memory Limit Address Register--Offset 22h .......................................115
15.1.21 Prefetchable Memory Base Address Register--Offset 24h .................115
15.1.22 Prefetchable Memory Limit Address Register--Offset 26h ..................116
15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register--
Offset 28h..........................................................................................................116
15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register--
Offset 2Ch .........................................................................................................117
15.1.25 I/O Base Address Upper 16 Bits Register--Offset 30h ........................117
15.1.26 I/O Limit Address Upper 16 Bits Register--Offset 32h ........................118