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21285 Core Logic for SA-110
Microprocessor
Datasheet
September 1998
Order Number:
278115-001
21285 Core Logic for SA-110 Datasheet
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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Copyright Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
21285 Core Logic for SA-110 Datasheet
iii
Contents
1
Introduction.....................................................................................................................11
1.1
Features ............................................................................................................11
1.1.1
Power Management .............................................................................12
1.2
System Applications ..........................................................................................12
2
Signal Description ..........................................................................................................21
2.1
PCI Signals........................................................................................................21
2.2
SA-110 Signals..................................................................................................23
2.3
ROM Signals .....................................................................................................25
2.4
SDRAM Signals.................................................................................................25
2.5
Serial Port Signals.............................................................................................27
2.6
Miscellaneous Signals.......................................................................................27
2.7
X-Bus/Arbiter Signals ........................................................................................28
2.7.1
X-Bus Selection ....................................................................................29
2.7.2
PCI Arbiter Selection ..........................................................................210
2.8
JTAG Signals ..................................................................................................210
2.9
Pin State During Reset....................................................................................211
2.10
Pin Assignment ...............................................................................................212
2.11
Pins Listed in Numeric Order ..........................................................................213
2.12
Pins Listed in Alphabetic Order .......................................................................217
3
Transactions...................................................................................................................31
3.1
SA-110 Originated Transactions .......................................................................31
3.1.1
CSR Write ............................................................................................31
3.1.2
CSR Read ............................................................................................31
3.1.3
SDRAM All-Banks Precharge...............................................................32
3.1.4
SDRAM Mode Register Set..................................................................33
3.1.5
SDRAM Write .......................................................................................33
3.1.6
SDRAM First Read ...............................................................................33
3.1.6.1 Lock .........................................................................................33
3.1.7
ROM Read ...........................................................................................33
3.1.8
ROM Write............................................................................................33
3.1.9
PCI Memory Write ................................................................................34
3.1.10 PCI Memory Read ................................................................................34
3.1.11 PCI I/O Write ........................................................................................34
3.1.12 PCI I/O Read ........................................................................................35
3.1.13 PCI Configuration Write........................................................................35
3.1.14 PCI Configuration Read .......................................................................35
3.1.15 PCI Special Cycle.................................................................................35
3.1.16 PCI IACK Read ....................................................................................35
3.1.17 X-Bus Write ..........................................................................................35
3.1.18 X-Bus Read ..........................................................................................36
3.1.19 Outbound Write Flush ..........................................................................36
3.1.20 SA-110 Cache Flush ............................................................................36
3.1.21 Reserved Addresses ............................................................................36
3.2
PCI Target Transactions ...................................................................................36
iv
21285 Core Logic for SA-110 Datasheet
3.2.1
Unsupported PCI Cycles As Target ..................................................... 37
3.2.2
Memory Write to SDRAM ..................................................................... 37
3.2.3
Memory Read, Memory Read Line, Memory Read Multiple to
SDRAM ................................................................................................ 39
3.2.4
Type 0 Configuration Write ................................................................ 310
3.2.5
Type 0 Configuration Read ................................................................ 310
3.2.6
Write to CSR ...................................................................................... 311
3.2.7
Read to CSR ...................................................................................... 311
3.2.8
Write to I
2
O Address .......................................................................... 311
3.2.9
Read to I
2
O Address .......................................................................... 311
3.2.10 Memory Write to ROM........................................................................ 312
3.2.11 Memory Read to ROM ....................................................................... 312
3.3
PCI Master Transactions................................................................................. 313
3.3.1
Dual Address Cycles (DAC) Support ................................................. 313
3.3.1.1 For SA110 Accesses........................................................... 313
3.3.1.2 For DMA Accesses................................................................ 314
3.3.2
Memory Write, Memory Write and Invalidate ..................................... 314
3.3.2.1 From SA-110 ......................................................................... 314
3.3.2.2 From DMA ............................................................................. 315
3.3.2.3 Selecting PCI Command for Writes....................................... 315
3.3.3
Memory Read, Memory Read Line, Memory Read Multiple .............. 315
3.3.3.1 From SA-110 ......................................................................... 316
3.3.3.2 From DMA ............................................................................. 316
3.3.3.3 Read Bursting Policy ............................................................. 316
3.3.4
I/O Write ............................................................................................ 316
3.3.5
I/O Read ............................................................................................. 317
3.3.6
Configuration Write ............................................................................ 317
3.3.7
Configuration Read ............................................................................ 319
3.3.8
Special Cycle ..................................................................................... 319
3.3.9
IACK Read ......................................................................................... 319
3.3.10 PCI Request Operation ...................................................................... 319
3.3.11 Master Latency Timer ........................................................................ 320
3.4
PCI Error Summary ......................................................................................... 320
3.4.1
Errors As PCI Target .......................................................................... 320
3.4.1.1 Address Parity Error .............................................................. 320
3.4.1.2 Write Data Parity Error .......................................................... 321
3.4.1.3 Read Data Parity Error .......................................................... 321
3.4.2
Errors As PCI Master ......................................................................... 321
3.4.2.1 Master Abort.......................................................................... 321
3.4.2.2 Write Data Parity Error .......................................................... 322
3.4.2.3 Target Abort on Write ............................................................ 322
3.4.2.4 Read Data Parity Error .......................................................... 322
3.4.2.5 Target Abort on Read............................................................ 322
4
SDRAM and ROM Operation ......................................................................................... 41
4.1
SDRAM Control................................................................................................. 41
4.1.1
SDRAM Addresses .............................................................................. 42
4.1.2
Commands ........................................................................................... 43
4.1.3
Parity .................................................................................................... 44
4.2
ROM Control ..................................................................................................... 45
4.2.1
Addressing ........................................................................................... 45
21285 Core Logic for SA-110 Datasheet
v
4.2.2
Reads ...................................................................................................47
4.2.3
Writes ...................................................................................................47
4.2.4
Timing...................................................................................................47
4.2.5
Blank ROM Programming ....................................................................48
5
SA-110 Operation...........................................................................................................51
5.1
SA-110 Control ..................................................................................................51
5.1.1
Address Map Partitioning .....................................................................51
5.1.2
Byte Enables ........................................................................................52
5.1.3
SA-110 Bus Arbiter...............................................................................52
5.2
X-Bus Interface..................................................................................................53
5.2.1
Address and Data Bus Generation.......................................................54
5.2.2
Device Support.....................................................................................55
5.2.3
Timing...................................................................................................55
5.3
Ordering and Deadlock Avoidance....................................................................56
5.3.1
Transaction Ordering............................................................................56
5.3.2
Ordering Rules .....................................................................................57
5.3.3
Deadlock Avoidance.............................................................................57
6
Functional Units..............................................................................................................61
6.1
PCI Bus Arbiter..................................................................................................61
6.1.1
Priority Algorithm ..................................................................................61
6.1.2
Determining Priority..............................................................................62
6.2
DMA Channels ..................................................................................................62
6.2.1
DMA Channel Operation ......................................................................63
6.2.2
SDRAM-to-PCI Transfer.......................................................................66
6.2.3
PCI-to-SDRAM Transfer.......................................................................66
6.2.4
Channel Alignment ...............................................................................66
6.3
I
2
O Message Unit ..............................................................................................67
6.3.1
I
2
O Inbound FIFO Operation ................................................................69
6.3.2
I
2
O Outbound FIFO Operation .............................................................69
6.3.3
Circulation of MFAs ............................................................................610
6.4
Timers .............................................................................................................611
6.4.1
Timer 4 Application.............................................................................611
6.5
Serial Port........................................................................................................612
6.5.1
Data Handling.....................................................................................612
6.5.2
Initialization.........................................................................................612
6.5.3
Frame Format.....................................................................................612
6.5.4
Baud Rate Generation........................................................................613
6.5.5
Receive Operation..............................................................................613
6.5.6
Transmit Operation.............................................................................613
6.5.7
Serial Port Interrupts ..........................................................................614
6.6
UART Register Definitions ..............................................................................614
6.6.1
UARTDR--Offset 160h ......................................................................614
6.6.2
RXSTAT--Offset 164h .......................................................................615
6.6.3
H_UBRLCR--Offset 168h ..................................................................616
6.6.4
M_UBRLCR--Offset 16Ch .................................................................617
6.6.5
L_UBRLCR--Offset 170h ..................................................................617
6.6.6
UARTCON-Offset 174h ......................................................................618
6.6.7
UARTFLG--Offset 178h ....................................................................618