128-Mbit 1.8 Volt Intel
Wireless Flash
Memory (W18) + 32-Mbit PSRAM
Stacked-CSP Family
Datasheet
Product Features
Versatile and compact Stacked Chip Scale Package (Stacked-CSP) solutions have been created
by combining 128-Mbit 1.8 Volt Intel
Wireless Flash Memory (W18) with low-power 32-Mbit
PSRAM. Ideal for high-performance, low-power, board-constrained memory applications, the
W18 + 32-Mbit PSRAM Stacked-CSP family retains all of the features of the discrete 1.8 Volt
Intel
Wireless Flash Memory (W18) device: flexible, multi-partition architecture for Read-
While-Write / Read-While-Erase (RWW/RWE) dual operation and high performance
asynchronous/ synchronous burst reads. Device upgrades and migrations are easy with a
common package footprint and signal ballout for all Stacked-CSP combinations. Manufactured
on Intel
0.13 micron
ETOXTM VIII process technology,
W18 provides the highest levels of quality
and reliability.
Flash Architecture
-- Flexible, Multiple-Partition, Dual-
Operation: Read-While-Write / Read-
While-Erase
-- 32 Partitions, 4 Mbits each
--31 Main Partitions, 8 Main Blocks each
--1 Parameter Partition, 8 Parameter + 7
Main Blocks
--32-Kword Main Blocks, 4-Kword
Parameter Blocks
-- Single flash die- Top or Bottom Parameter
-- Dual flash die- Dual Parameter
Flash Performance
-- 65 ns Initial Access Speed
-- 25 ns Async 4-Word Page-Mode Reads
-- 14 ns Sync Burst-Read Speed
-- 4-, 8-, 16-, Continuous-Word Burst Lengths
-- Burst-/ Page-Mode Reads in all Blocks and
across all partition boundaries
-- Burst Suspend
-- Programmable WAIT Configuration
-- Enhanced Factory Programming Mode:
3.1s/Word
-- Flash Protection Register
--64 Unique Device Identifier Bits
--64 User-Programmable OTP Bits
Flash Automation Suspend Operations
-- Erase Suspend to Program or Read
-- Program Suspend to Read
-- 5s (typ) Program/Erase Suspend Latency
Flash Software
-- Intel
Flash Data Integrator (FDI)
Optimized
-- Common Flash Interface (CFI)
Flash Data Protection
-- Absolute Protection with VPP and WP#
-- Individual Dynamic Zero-Latency Block
Locking
-- Individual Block Lock-Down
-- Erase/Program Lockout during Power
Transitions
Stacked-CSP Architecture
-- Flash
-- Flash + Flash
-- Flash + PSRAM
-- Flash + Flash + PSRAM
-- Reduces Board Space Requirement
-- Simplifies PCB Design Complexity
-- Easy Migration to Future Stacked-CSP
Devices
Stacked-CSP Voltage
-- 1.7 V to 1.95 V V
CC
-- 1.7 V to 2.24 V V
CCQ
(Flash only)
-- 1.8 V to 1.95 V V
CCQ
(Flash + PSRAM)
Stacked-CSP Packaging
-- 0.8 mm Ball-Pitch Intel
Stacked-CSP
-- Area: 8x10 mm, Height: 1.2mm and 1.4mm
-- 88-Ball (8 x 10 Matrix): 80 Active Balls
with 2 Support Balls at Each Corner
PSRAM Architecture and Performance
-- 1.8 V to 1.95 V P-V
CC
-- 85 ns Access Speed
-- 8-Word Page Read
-- 30 ns for Page Read Speed
-- Low Power Mode
Flash Quality and Reliability
-- Extended Temperature: 25 C to +85 C
-- Minimum 100K Block Erase Cycles
-- 0.13 m ETOXTM VIII Process
252634-001
February 2003
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
2
Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The 128-Mbit 1.8 Volt Intel Wireless Flash Memory + 32-Mbit PSRAM Stacked-CSP family may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright Intel Corporation, 2003.
*Other names and brands may be claimed as the property of others.
Datasheet
3
Contents
1.0 Introduction
...............................................................................................................................7
1.1
Nomenclature .......................................................................................................................7
1.2
Conventions..........................................................................................................................7
2.0 Product Description
...............................................................................................................9
2.1
Product Overview .................................................................................................................9
2.2
Ballout Diagram ..................................................................................................................10
2.3
Signal Descriptions .............................................................................................................11
2.4
Block Diagram ....................................................................................................................13
2.5
Flash Memory Map and Partitioning ...................................................................................13
3.0 Device Operation
...................................................................................................................15
3.1
Bus Operations ...................................................................................................................15
3.2
Flash Command Definitions................................................................................................17
4.0 Flash Read Operations
........................................................................................................17
5.0 Flash Program Operations
................................................................................................17
6.0 Flash Erase Operations
......................................................................................................17
7.0 Flash Security Modes
..........................................................................................................17
8.0 Flash Read Configuration Register
................................................................................17
9.0 Flash Power Consumption
................................................................................................17
10.0 Electrical Specifications
.....................................................................................................18
10.1 Absolute Maximum Ratings ................................................................................................18
10.2 Operating Conditions ..........................................................................................................19
10.3 Capacitance........................................................................................................................19
10.4 DC Characteristics..............................................................................................................20
11.0 AC Characteristics
................................................................................................................21
11.1 Flash AC Characteristics ....................................................................................................21
11.2 PSRAM AC Characteristics ................................................................................................22
12.0 PSRAM Operations
...............................................................................................................26
12.1 Power-up Sequence and Initialization ................................................................................26
12.2 Mode Register ....................................................................................................................26
12.2.1 Mode Register Setting ...................................................................................................27
12.2.2 Cautions for setting Mode Register ...............................................................................28
12.3 Low Power mode ................................................................................................................29
Appendix A Write State Machine
.............................................................................................30
Appendix B Common Flash Interface
....................................................................................30
Appendix C Flash Flowcharts
...................................................................................................30
Appendix D Mechanical Package Information
...................................................................31
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